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1/* SPDX-License-Identifier: GPL-2.0 */
2/* head.S: Initial boot code for the Sparc64 port of Linux.
3 *
4 * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
5 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
6 * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 */
9
10#include <linux/version.h>
11#include <linux/errno.h>
12#include <linux/threads.h>
13#include <linux/init.h>
14#include <linux/linkage.h>
15#include <linux/pgtable.h>
16#include <asm/thread_info.h>
17#include <asm/asi.h>
18#include <asm/pstate.h>
19#include <asm/ptrace.h>
20#include <asm/spitfire.h>
21#include <asm/page.h>
22#include <asm/errno.h>
23#include <asm/signal.h>
24#include <asm/processor.h>
25#include <asm/lsu.h>
26#include <asm/dcr.h>
27#include <asm/dcu.h>
28#include <asm/head.h>
29#include <asm/ttable.h>
30#include <asm/mmu.h>
31#include <asm/cpudata.h>
32#include <asm/pil.h>
33#include <asm/estate.h>
34#include <asm/sfafsr.h>
35#include <asm/unistd.h>
36#include <asm/export.h>
37
38/* This section from from _start to sparc64_boot_end should fit into
39 * 0x0000000000404000 to 0x0000000000408000.
40 */
41 .text
42 .globl start, _start, stext, _stext
43_start:
44start:
45_stext:
46stext:
47! 0x0000000000404000
48 b sparc64_boot
49 flushw /* Flush register file. */
50
51/* This stuff has to be in sync with SILO and other potential boot loaders
52 * Fields should be kept upward compatible and whenever any change is made,
53 * HdrS version should be incremented.
54 */
55 .global root_flags, ram_flags, root_dev
56 .global sparc_ramdisk_image, sparc_ramdisk_size
57 .global sparc_ramdisk_image64
58
59 .ascii "HdrS"
60 .word LINUX_VERSION_CODE
61
62 /* History:
63 *
64 * 0x0300 : Supports being located at other than 0x4000
65 * 0x0202 : Supports kernel params string
66 * 0x0201 : Supports reboot_command
67 */
68 .half 0x0301 /* HdrS version */
69
70root_flags:
71 .half 1
72root_dev:
73 .half 0
74ram_flags:
75 .half 0
76sparc_ramdisk_image:
77 .word 0
78sparc_ramdisk_size:
79 .word 0
80 .xword reboot_command
81 .xword bootstr_info
82sparc_ramdisk_image64:
83 .xword 0
84 .word _end
85
86 /* PROM cif handler code address is in %o4. */
87sparc64_boot:
88 mov %o4, %l7
89
90 /* We need to remap the kernel. Use position independent
91 * code to remap us to KERNBASE.
92 *
93 * SILO can invoke us with 32-bit address masking enabled,
94 * so make sure that's clear.
95 */
96 rdpr %pstate, %g1
97 andn %g1, PSTATE_AM, %g1
98 wrpr %g1, 0x0, %pstate
99 ba,a,pt %xcc, 1f
100 nop
101
102 .globl prom_finddev_name, prom_chosen_path, prom_root_node
103 .globl prom_getprop_name, prom_mmu_name, prom_peer_name
104 .globl prom_callmethod_name, prom_translate_name, prom_root_compatible
105 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
106 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
107 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
108 .globl prom_compatible_name, prom_cpu_path, prom_cpu_compatible
109 .globl is_sun4v, sun4v_chip_type, prom_set_trap_table_name
110prom_peer_name:
111 .asciz "peer"
112prom_compatible_name:
113 .asciz "compatible"
114prom_finddev_name:
115 .asciz "finddevice"
116prom_chosen_path:
117 .asciz "/chosen"
118prom_cpu_path:
119 .asciz "/cpu"
120prom_getprop_name:
121 .asciz "getprop"
122prom_mmu_name:
123 .asciz "mmu"
124prom_callmethod_name:
125 .asciz "call-method"
126prom_translate_name:
127 .asciz "translate"
128prom_map_name:
129 .asciz "map"
130prom_unmap_name:
131 .asciz "unmap"
132prom_set_trap_table_name:
133 .asciz "SUNW,set-trap-table"
134prom_sun4v_name:
135 .asciz "sun4v"
136prom_niagara_prefix:
137 .asciz "SUNW,UltraSPARC-T"
138prom_sparc_prefix:
139 .asciz "SPARC-"
140prom_sparc64x_prefix:
141 .asciz "SPARC64-X"
142 .align 4
143prom_root_compatible:
144 .skip 64
145prom_cpu_compatible:
146 .skip 64
147prom_root_node:
148 .word 0
149EXPORT_SYMBOL(prom_root_node)
150prom_mmu_ihandle_cache:
151 .word 0
152prom_boot_mapped_pc:
153 .word 0
154prom_boot_mapping_mode:
155 .word 0
156 .align 8
157prom_boot_mapping_phys_high:
158 .xword 0
159prom_boot_mapping_phys_low:
160 .xword 0
161is_sun4v:
162 .word 0
163sun4v_chip_type:
164 .word SUN4V_CHIP_INVALID
165EXPORT_SYMBOL(sun4v_chip_type)
1661:
167 rd %pc, %l0
168
169 mov (1b - prom_peer_name), %l1
170 sub %l0, %l1, %l1
171 mov 0, %l2
172
173 /* prom_root_node = prom_peer(0) */
174 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
175 mov 1, %l3
176 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
177 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
178 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
179 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
180 call %l7
181 add %sp, (2047 + 128), %o0 ! argument array
182
183 ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
184 mov (1b - prom_root_node), %l1
185 sub %l0, %l1, %l1
186 stw %l4, [%l1]
187
188 mov (1b - prom_getprop_name), %l1
189 mov (1b - prom_compatible_name), %l2
190 mov (1b - prom_root_compatible), %l5
191 sub %l0, %l1, %l1
192 sub %l0, %l2, %l2
193 sub %l0, %l5, %l5
194
195 /* prom_getproperty(prom_root_node, "compatible",
196 * &prom_root_compatible, 64)
197 */
198 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
199 mov 4, %l3
200 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
201 mov 1, %l3
202 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
203 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
204 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
205 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
206 mov 64, %l3
207 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
208 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
209 call %l7
210 add %sp, (2047 + 128), %o0 ! argument array
211
212 mov (1b - prom_finddev_name), %l1
213 mov (1b - prom_chosen_path), %l2
214 mov (1b - prom_boot_mapped_pc), %l3
215 sub %l0, %l1, %l1
216 sub %l0, %l2, %l2
217 sub %l0, %l3, %l3
218 stw %l0, [%l3]
219 sub %sp, (192 + 128), %sp
220
221 /* chosen_node = prom_finddevice("/chosen") */
222 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
223 mov 1, %l3
224 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
225 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
226 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
227 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
228 call %l7
229 add %sp, (2047 + 128), %o0 ! argument array
230
231 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
232
233 mov (1b - prom_getprop_name), %l1
234 mov (1b - prom_mmu_name), %l2
235 mov (1b - prom_mmu_ihandle_cache), %l5
236 sub %l0, %l1, %l1
237 sub %l0, %l2, %l2
238 sub %l0, %l5, %l5
239
240 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
241 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
242 mov 4, %l3
243 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
244 mov 1, %l3
245 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
246 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
247 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
248 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
249 mov 4, %l3
250 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
251 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
252 call %l7
253 add %sp, (2047 + 128), %o0 ! argument array
254
255 mov (1b - prom_callmethod_name), %l1
256 mov (1b - prom_translate_name), %l2
257 sub %l0, %l1, %l1
258 sub %l0, %l2, %l2
259 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
260
261 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
262 mov 3, %l3
263 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
264 mov 5, %l3
265 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
266 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
267 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
268 /* PAGE align */
269 srlx %l0, 13, %l3
270 sllx %l3, 13, %l3
271 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
272 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
273 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
274 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
275 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
276 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
277 call %l7
278 add %sp, (2047 + 128), %o0 ! argument array
279
280 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
281 mov (1b - prom_boot_mapping_mode), %l4
282 sub %l0, %l4, %l4
283 stw %l1, [%l4]
284 mov (1b - prom_boot_mapping_phys_high), %l4
285 sub %l0, %l4, %l4
286 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
287 stx %l2, [%l4 + 0x0]
288 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
289 /* 4MB align */
290 srlx %l3, ILOG2_4MB, %l3
291 sllx %l3, ILOG2_4MB, %l3
292 stx %l3, [%l4 + 0x8]
293
294 /* Leave service as-is, "call-method" */
295 mov 7, %l3
296 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
297 mov 1, %l3
298 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
299 mov (1b - prom_map_name), %l3
300 sub %l0, %l3, %l3
301 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
302 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
303 mov -1, %l3
304 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
305 /* 4MB align the kernel image size. */
306 set (_end - KERNBASE), %l3
307 set ((4 * 1024 * 1024) - 1), %l4
308 add %l3, %l4, %l3
309 andn %l3, %l4, %l3
310 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: roundup(ksize, 4MB)
311 sethi %hi(KERNBASE), %l3
312 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
313 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
314 mov (1b - prom_boot_mapping_phys_low), %l3
315 sub %l0, %l3, %l3
316 ldx [%l3], %l3
317 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
318 call %l7
319 add %sp, (2047 + 128), %o0 ! argument array
320
321 add %sp, (192 + 128), %sp
322
323 sethi %hi(prom_root_compatible), %g1
324 or %g1, %lo(prom_root_compatible), %g1
325 sethi %hi(prom_sun4v_name), %g7
326 or %g7, %lo(prom_sun4v_name), %g7
327 mov 5, %g3
32890: ldub [%g7], %g2
329 ldub [%g1], %g4
330 cmp %g2, %g4
331 bne,pn %icc, 80f
332 add %g7, 1, %g7
333 subcc %g3, 1, %g3
334 bne,pt %xcc, 90b
335 add %g1, 1, %g1
336
337 sethi %hi(is_sun4v), %g1
338 or %g1, %lo(is_sun4v), %g1
339 mov 1, %g7
340 stw %g7, [%g1]
341
342 /* cpu_node = prom_finddevice("/cpu") */
343 mov (1b - prom_finddev_name), %l1
344 mov (1b - prom_cpu_path), %l2
345 sub %l0, %l1, %l1
346 sub %l0, %l2, %l2
347 sub %sp, (192 + 128), %sp
348
349 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
350 mov 1, %l3
351 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
352 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
353 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/cpu"
354 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
355 call %l7
356 add %sp, (2047 + 128), %o0 ! argument array
357
358 ldx [%sp + 2047 + 128 + 0x20], %l4 ! cpu device node
359
360 mov (1b - prom_getprop_name), %l1
361 mov (1b - prom_compatible_name), %l2
362 mov (1b - prom_cpu_compatible), %l5
363 sub %l0, %l1, %l1
364 sub %l0, %l2, %l2
365 sub %l0, %l5, %l5
366
367 /* prom_getproperty(cpu_node, "compatible",
368 * &prom_cpu_compatible, 64)
369 */
370 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
371 mov 4, %l3
372 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
373 mov 1, %l3
374 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
375 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, cpu_node
376 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
377 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_cpu_compatible
378 mov 64, %l3
379 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
380 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
381 call %l7
382 add %sp, (2047 + 128), %o0 ! argument array
383
384 add %sp, (192 + 128), %sp
385
386 sethi %hi(prom_cpu_compatible), %g1
387 or %g1, %lo(prom_cpu_compatible), %g1
388 sethi %hi(prom_niagara_prefix), %g7
389 or %g7, %lo(prom_niagara_prefix), %g7
390 mov 17, %g3
39190: ldub [%g7], %g2
392 ldub [%g1], %g4
393 cmp %g2, %g4
394 bne,pn %icc, 89f
395 add %g7, 1, %g7
396 subcc %g3, 1, %g3
397 bne,pt %xcc, 90b
398 add %g1, 1, %g1
399 ba,pt %xcc, 91f
400 nop
401
40289: sethi %hi(prom_cpu_compatible), %g1
403 or %g1, %lo(prom_cpu_compatible), %g1
404 sethi %hi(prom_sparc_prefix), %g7
405 or %g7, %lo(prom_sparc_prefix), %g7
406 mov 6, %g3
40790: ldub [%g7], %g2
408 ldub [%g1], %g4
409 cmp %g2, %g4
410 bne,pn %icc, 4f
411 add %g7, 1, %g7
412 subcc %g3, 1, %g3
413 bne,pt %xcc, 90b
414 add %g1, 1, %g1
415
416 sethi %hi(prom_cpu_compatible), %g1
417 or %g1, %lo(prom_cpu_compatible), %g1
418 ldub [%g1 + 6], %g2
419 cmp %g2, 'T'
420 be,pt %xcc, 70f
421 cmp %g2, 'M'
422 be,pt %xcc, 70f
423 cmp %g2, 'S'
424 bne,pn %xcc, 49f
425 nop
426
42770: ldub [%g1 + 7], %g2
428 cmp %g2, CPU_ID_NIAGARA3
429 be,pt %xcc, 5f
430 mov SUN4V_CHIP_NIAGARA3, %g4
431 cmp %g2, CPU_ID_NIAGARA4
432 be,pt %xcc, 5f
433 mov SUN4V_CHIP_NIAGARA4, %g4
434 cmp %g2, CPU_ID_NIAGARA5
435 be,pt %xcc, 5f
436 mov SUN4V_CHIP_NIAGARA5, %g4
437 cmp %g2, CPU_ID_M6
438 be,pt %xcc, 5f
439 mov SUN4V_CHIP_SPARC_M6, %g4
440 cmp %g2, CPU_ID_M7
441 be,pt %xcc, 5f
442 mov SUN4V_CHIP_SPARC_M7, %g4
443 cmp %g2, CPU_ID_M8
444 be,pt %xcc, 5f
445 mov SUN4V_CHIP_SPARC_M8, %g4
446 cmp %g2, CPU_ID_SONOMA1
447 be,pt %xcc, 5f
448 mov SUN4V_CHIP_SPARC_SN, %g4
449 ba,pt %xcc, 49f
450 nop
451
45291: sethi %hi(prom_cpu_compatible), %g1
453 or %g1, %lo(prom_cpu_compatible), %g1
454 ldub [%g1 + 17], %g2
455 cmp %g2, CPU_ID_NIAGARA1
456 be,pt %xcc, 5f
457 mov SUN4V_CHIP_NIAGARA1, %g4
458 cmp %g2, CPU_ID_NIAGARA2
459 be,pt %xcc, 5f
460 mov SUN4V_CHIP_NIAGARA2, %g4
461
4624:
463 /* Athena */
464 sethi %hi(prom_cpu_compatible), %g1
465 or %g1, %lo(prom_cpu_compatible), %g1
466 sethi %hi(prom_sparc64x_prefix), %g7
467 or %g7, %lo(prom_sparc64x_prefix), %g7
468 mov 9, %g3
46941: ldub [%g7], %g2
470 ldub [%g1], %g4
471 cmp %g2, %g4
472 bne,pn %icc, 49f
473 add %g7, 1, %g7
474 subcc %g3, 1, %g3
475 bne,pt %xcc, 41b
476 add %g1, 1, %g1
477 ba,pt %xcc, 5f
478 mov SUN4V_CHIP_SPARC64X, %g4
479
48049:
481 mov SUN4V_CHIP_UNKNOWN, %g4
4825: sethi %hi(sun4v_chip_type), %g2
483 or %g2, %lo(sun4v_chip_type), %g2
484 stw %g4, [%g2]
485
48680:
487 BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
488 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
489 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
490 ba,pt %xcc, spitfire_boot
491 nop
492
493cheetah_plus_boot:
494 /* Preserve OBP chosen DCU and DCR register settings. */
495 ba,pt %xcc, cheetah_generic_boot
496 nop
497
498cheetah_boot:
499 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
500 wr %g1, %asr18
501
502 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
503 or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
504 sllx %g7, 32, %g7
505 or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
506 stxa %g7, [%g0] ASI_DCU_CONTROL_REG
507 membar #Sync
508
509cheetah_generic_boot:
510 mov TSB_EXTENSION_P, %g3
511 stxa %g0, [%g3] ASI_DMMU
512 stxa %g0, [%g3] ASI_IMMU
513 membar #Sync
514
515 mov TSB_EXTENSION_S, %g3
516 stxa %g0, [%g3] ASI_DMMU
517 membar #Sync
518
519 mov TSB_EXTENSION_N, %g3
520 stxa %g0, [%g3] ASI_DMMU
521 stxa %g0, [%g3] ASI_IMMU
522 membar #Sync
523
524 ba,a,pt %xcc, jump_to_sun4u_init
525
526spitfire_boot:
527 /* Typically PROM has already enabled both MMU's and both on-chip
528 * caches, but we do it here anyway just to be paranoid.
529 */
530 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
531 stxa %g1, [%g0] ASI_LSU_CONTROL
532 membar #Sync
533
534jump_to_sun4u_init:
535 /*
536 * Make sure we are in privileged mode, have address masking,
537 * using the ordinary globals and have enabled floating
538 * point.
539 *
540 * Again, typically PROM has left %pil at 13 or similar, and
541 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
542 */
543 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
544 wr %g0, 0, %fprs
545
546 set sun4u_init, %g2
547 jmpl %g2 + %g0, %g0
548 nop
549
550 __REF
551sun4u_init:
552 BRANCH_IF_SUN4V(g1, sun4v_init)
553
554 /* Set ctx 0 */
555 mov PRIMARY_CONTEXT, %g7
556 stxa %g0, [%g7] ASI_DMMU
557 membar #Sync
558
559 mov SECONDARY_CONTEXT, %g7
560 stxa %g0, [%g7] ASI_DMMU
561 membar #Sync
562
563 ba,a,pt %xcc, sun4u_continue
564
565sun4v_init:
566 /* Set ctx 0 */
567 mov PRIMARY_CONTEXT, %g7
568 stxa %g0, [%g7] ASI_MMU
569 membar #Sync
570
571 mov SECONDARY_CONTEXT, %g7
572 stxa %g0, [%g7] ASI_MMU
573 membar #Sync
574 ba,a,pt %xcc, niagara_tlb_fixup
575
576sun4u_continue:
577 BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
578
579 ba,a,pt %xcc, spitfire_tlb_fixup
580
581niagara_tlb_fixup:
582 mov 3, %g2 /* Set TLB type to hypervisor. */
583 sethi %hi(tlb_type), %g1
584 stw %g2, [%g1 + %lo(tlb_type)]
585
586 /* Patch copy/clear ops. */
587 sethi %hi(sun4v_chip_type), %g1
588 lduw [%g1 + %lo(sun4v_chip_type)], %g1
589 cmp %g1, SUN4V_CHIP_NIAGARA1
590 be,pt %xcc, niagara_patch
591 cmp %g1, SUN4V_CHIP_NIAGARA2
592 be,pt %xcc, niagara2_patch
593 nop
594 cmp %g1, SUN4V_CHIP_NIAGARA3
595 be,pt %xcc, niagara2_patch
596 nop
597 cmp %g1, SUN4V_CHIP_NIAGARA4
598 be,pt %xcc, niagara4_patch
599 nop
600 cmp %g1, SUN4V_CHIP_NIAGARA5
601 be,pt %xcc, niagara4_patch
602 nop
603 cmp %g1, SUN4V_CHIP_SPARC_M6
604 be,pt %xcc, niagara4_patch
605 nop
606 cmp %g1, SUN4V_CHIP_SPARC_M7
607 be,pt %xcc, sparc_m7_patch
608 nop
609 cmp %g1, SUN4V_CHIP_SPARC_M8
610 be,pt %xcc, sparc_m7_patch
611 nop
612 cmp %g1, SUN4V_CHIP_SPARC_SN
613 be,pt %xcc, niagara4_patch
614 nop
615
616 call generic_patch_copyops
617 nop
618 call generic_patch_bzero
619 nop
620 call generic_patch_pageops
621 nop
622
623 ba,a,pt %xcc, 80f
624 nop
625
626sparc_m7_patch:
627 call m7_patch_copyops
628 nop
629 call m7_patch_bzero
630 nop
631 call m7_patch_pageops
632 nop
633
634 ba,a,pt %xcc, 80f
635 nop
636
637niagara4_patch:
638 call niagara4_patch_copyops
639 nop
640 call niagara4_patch_bzero
641 nop
642 call niagara4_patch_pageops
643 nop
644 call niagara4_patch_fls
645 nop
646
647 ba,a,pt %xcc, 80f
648 nop
649
650niagara2_patch:
651 call niagara2_patch_copyops
652 nop
653 call niagara_patch_bzero
654 nop
655 call niagara_patch_pageops
656 nop
657
658 ba,a,pt %xcc, 80f
659 nop
660
661niagara_patch:
662 call niagara_patch_copyops
663 nop
664 call niagara_patch_bzero
665 nop
666 call niagara_patch_pageops
667 nop
668
66980:
670 /* Patch TLB/cache ops. */
671 call hypervisor_patch_cachetlbops
672 nop
673
674 ba,a,pt %xcc, tlb_fixup_done
675
676cheetah_tlb_fixup:
677 mov 2, %g2 /* Set TLB type to cheetah+. */
678 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
679
680 mov 1, %g2 /* Set TLB type to cheetah. */
681
6821: sethi %hi(tlb_type), %g1
683 stw %g2, [%g1 + %lo(tlb_type)]
684
685 /* Patch copy/page operations to cheetah optimized versions. */
686 call cheetah_patch_copyops
687 nop
688 call cheetah_patch_copy_page
689 nop
690 call cheetah_patch_cachetlbops
691 nop
692
693 ba,a,pt %xcc, tlb_fixup_done
694
695spitfire_tlb_fixup:
696 /* Set TLB type to spitfire. */
697 mov 0, %g2
698 sethi %hi(tlb_type), %g1
699 stw %g2, [%g1 + %lo(tlb_type)]
700
701tlb_fixup_done:
702 sethi %hi(init_thread_union), %g6
703 or %g6, %lo(init_thread_union), %g6
704 ldx [%g6 + TI_TASK], %g4
705
706 wr %g0, ASI_P, %asi
707 mov 1, %g1
708 sllx %g1, THREAD_SHIFT, %g1
709 sub %g1, (STACKFRAME_SZ + STACK_BIAS + TRACEREG_SZ), %g1
710 add %g6, %g1, %sp
711
712 /* Set per-cpu pointer initially to zero, this makes
713 * the boot-cpu use the in-kernel-image per-cpu areas
714 * before setup_per_cpu_area() is invoked.
715 */
716 clr %g5
717
718 wrpr %g0, 0, %wstate
719 wrpr %g0, 0x0, %tl
720
721 /* Clear the bss */
722 sethi %hi(__bss_start), %o0
723 or %o0, %lo(__bss_start), %o0
724 sethi %hi(_end), %o1
725 or %o1, %lo(_end), %o1
726 call __bzero
727 sub %o1, %o0, %o1
728
729 call prom_init
730 mov %l7, %o0 ! OpenPROM cif handler
731
732 /* To create a one-register-window buffer between the kernel's
733 * initial stack and the last stack frame we use from the firmware,
734 * do the rest of the boot from a C helper function.
735 */
736 call start_early_boot
737 nop
738 /* Not reached... */
739
740 .previous
741
742 /* This is meant to allow the sharing of this code between
743 * boot processor invocation (via setup_tba() below) and
744 * secondary processor startup (via trampoline.S). The
745 * former does use this code, the latter does not yet due
746 * to some complexities. That should be fixed up at some
747 * point.
748 *
749 * There used to be enormous complexity wrt. transferring
750 * over from the firmware's trap table to the Linux kernel's.
751 * For example, there was a chicken & egg problem wrt. building
752 * the OBP page tables, yet needing to be on the Linux kernel
753 * trap table (to translate PAGE_OFFSET addresses) in order to
754 * do that.
755 *
756 * We now handle OBP tlb misses differently, via linear lookups
757 * into the prom_trans[] array. So that specific problem no
758 * longer exists. Yet, unfortunately there are still some issues
759 * preventing trampoline.S from using this code... ho hum.
760 */
761 .globl setup_trap_table
762setup_trap_table:
763 save %sp, -192, %sp
764
765 /* Force interrupts to be disabled. */
766 rdpr %pstate, %l0
767 andn %l0, PSTATE_IE, %o1
768 wrpr %o1, 0x0, %pstate
769 rdpr %pil, %l1
770 wrpr %g0, PIL_NORMAL_MAX, %pil
771
772 /* Make the firmware call to jump over to the Linux trap table. */
773 sethi %hi(is_sun4v), %o0
774 lduw [%o0 + %lo(is_sun4v)], %o0
775 brz,pt %o0, 1f
776 nop
777
778 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
779 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
780 stxa %g2, [%g0] ASI_SCRATCHPAD
781
782 /* Compute physical address:
783 *
784 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
785 */
786 sethi %hi(KERNBASE), %g3
787 sub %g2, %g3, %g2
788 sethi %hi(kern_base), %g3
789 ldx [%g3 + %lo(kern_base)], %g3
790 add %g2, %g3, %o1
791 sethi %hi(sparc64_ttable_tl0), %o0
792
793 set prom_set_trap_table_name, %g2
794 stx %g2, [%sp + 2047 + 128 + 0x00]
795 mov 2, %g2
796 stx %g2, [%sp + 2047 + 128 + 0x08]
797 mov 0, %g2
798 stx %g2, [%sp + 2047 + 128 + 0x10]
799 stx %o0, [%sp + 2047 + 128 + 0x18]
800 stx %o1, [%sp + 2047 + 128 + 0x20]
801 sethi %hi(p1275buf), %g2
802 or %g2, %lo(p1275buf), %g2
803 ldx [%g2 + 0x08], %o1
804 call %o1
805 add %sp, (2047 + 128), %o0
806
807 ba,a,pt %xcc, 2f
808
8091: sethi %hi(sparc64_ttable_tl0), %o0
810 set prom_set_trap_table_name, %g2
811 stx %g2, [%sp + 2047 + 128 + 0x00]
812 mov 1, %g2
813 stx %g2, [%sp + 2047 + 128 + 0x08]
814 mov 0, %g2
815 stx %g2, [%sp + 2047 + 128 + 0x10]
816 stx %o0, [%sp + 2047 + 128 + 0x18]
817 sethi %hi(p1275buf), %g2
818 or %g2, %lo(p1275buf), %g2
819 ldx [%g2 + 0x08], %o1
820 call %o1
821 add %sp, (2047 + 128), %o0
822
823 /* Start using proper page size encodings in ctx register. */
8242: sethi %hi(sparc64_kern_pri_context), %g3
825 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
826
827 mov PRIMARY_CONTEXT, %g1
828
829661: stxa %g2, [%g1] ASI_DMMU
830 .section .sun4v_1insn_patch, "ax"
831 .word 661b
832 stxa %g2, [%g1] ASI_MMU
833 .previous
834
835 membar #Sync
836
837 BRANCH_IF_SUN4V(o2, 1f)
838
839 /* Kill PROM timer */
840 sethi %hi(0x80000000), %o2
841 sllx %o2, 32, %o2
842 wr %o2, 0, %tick_cmpr
843
844 BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
845
846 ba,a,pt %xcc, 2f
847
848 /* Disable STICK_INT interrupts. */
8491:
850 sethi %hi(0x80000000), %o2
851 sllx %o2, 32, %o2
852 wr %o2, %asr25
853
8542:
855 wrpr %g0, %g0, %wstate
856
857 call init_irqwork_curcpu
858 nop
859
860 /* Now we can restore interrupt state. */
861 wrpr %l0, 0, %pstate
862 wrpr %l1, 0x0, %pil
863
864 ret
865 restore
866
867 .globl setup_tba
868setup_tba:
869 save %sp, -192, %sp
870
871 /* The boot processor is the only cpu which invokes this
872 * routine, the other cpus set things up via trampoline.S.
873 * So save the OBP trap table address here.
874 */
875 rdpr %tba, %g7
876 sethi %hi(prom_tba), %o1
877 or %o1, %lo(prom_tba), %o1
878 stx %g7, [%o1]
879
880 call setup_trap_table
881 nop
882
883 ret
884 restore
885sparc64_boot_end:
886
887#include "etrap_64.S"
888#include "rtrap_64.S"
889#include "winfixup.S"
890#include "fpu_traps.S"
891#include "ivec.S"
892#include "getsetcc.S"
893#include "utrap.S"
894#include "spiterrs.S"
895#include "cherrs.S"
896#include "misctrap.S"
897#include "syscalls.S"
898#include "helpers.S"
899#include "sun4v_tlb_miss.S"
900#include "sun4v_mcd.S"
901#include "sun4v_ivec.S"
902#include "ktlb.S"
903#include "tsb.S"
904
905/*
906 * The following skip makes sure the trap table in ttable.S is aligned
907 * on a 32K boundary as required by the v9 specs for TBA register.
908 *
909 * We align to a 32K boundary, then we have the 32K kernel TSB,
910 * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
911 */
9121:
913 .skip 0x4000 + _start - 1b
914
915! 0x0000000000408000
916
917 .globl swapper_tsb
918swapper_tsb:
919 .skip (32 * 1024)
920
921 .globl swapper_4m_tsb
922swapper_4m_tsb:
923 .skip (64 * 1024)
924
925! 0x0000000000420000
926
927 /* Some care needs to be exercised if you try to move the
928 * location of the trap table relative to other things. For
929 * one thing there are br* instructions in some of the
930 * trap table entires which branch back to code in ktlb.S
931 * Those instructions can only handle a signed 16-bit
932 * displacement.
933 *
934 * There is a binutils bug (bugzilla #4558) which causes
935 * the relocation overflow checks for such instructions to
936 * not be done correctly. So bintuils will not notice the
937 * error and will instead write junk into the relocation and
938 * you'll have an unbootable kernel.
939 */
940#include "ttable_64.S"
941
942! 0x0000000000428000
943
944#include "hvcalls.S"
945#include "systbls_64.S"
946
947 .data
948 .align 8
949 .globl prom_tba, tlb_type
950prom_tba: .xword 0
951tlb_type: .word 0 /* Must NOT end up in BSS */
952EXPORT_SYMBOL(tlb_type)
953 .section ".fixup",#alloc,#execinstr
954
955ENTRY(__retl_efault)
956 retl
957 mov -EFAULT, %o0
958ENDPROC(__retl_efault)
959
960ENTRY(__retl_o1)
961 retl
962 mov %o1, %o0
963ENDPROC(__retl_o1)
964
965ENTRY(__retl_o1_asi)
966 wr %o5, 0x0, %asi
967 retl
968 mov %o1, %o0
969ENDPROC(__retl_o1_asi)
1/* head.S: Initial boot code for the Sparc64 port of Linux.
2 *
3 * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
5 * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 */
8
9#include <linux/version.h>
10#include <linux/errno.h>
11#include <linux/threads.h>
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/thread_info.h>
15#include <asm/asi.h>
16#include <asm/pstate.h>
17#include <asm/ptrace.h>
18#include <asm/spitfire.h>
19#include <asm/page.h>
20#include <asm/pgtable.h>
21#include <asm/errno.h>
22#include <asm/signal.h>
23#include <asm/processor.h>
24#include <asm/lsu.h>
25#include <asm/dcr.h>
26#include <asm/dcu.h>
27#include <asm/head.h>
28#include <asm/ttable.h>
29#include <asm/mmu.h>
30#include <asm/cpudata.h>
31#include <asm/pil.h>
32#include <asm/estate.h>
33#include <asm/sfafsr.h>
34#include <asm/unistd.h>
35
36/* This section from from _start to sparc64_boot_end should fit into
37 * 0x0000000000404000 to 0x0000000000408000.
38 */
39 .text
40 .globl start, _start, stext, _stext
41_start:
42start:
43_stext:
44stext:
45! 0x0000000000404000
46 b sparc64_boot
47 flushw /* Flush register file. */
48
49/* This stuff has to be in sync with SILO and other potential boot loaders
50 * Fields should be kept upward compatible and whenever any change is made,
51 * HdrS version should be incremented.
52 */
53 .global root_flags, ram_flags, root_dev
54 .global sparc_ramdisk_image, sparc_ramdisk_size
55 .global sparc_ramdisk_image64
56
57 .ascii "HdrS"
58 .word LINUX_VERSION_CODE
59
60 /* History:
61 *
62 * 0x0300 : Supports being located at other than 0x4000
63 * 0x0202 : Supports kernel params string
64 * 0x0201 : Supports reboot_command
65 */
66 .half 0x0301 /* HdrS version */
67
68root_flags:
69 .half 1
70root_dev:
71 .half 0
72ram_flags:
73 .half 0
74sparc_ramdisk_image:
75 .word 0
76sparc_ramdisk_size:
77 .word 0
78 .xword reboot_command
79 .xword bootstr_info
80sparc_ramdisk_image64:
81 .xword 0
82 .word _end
83
84 /* PROM cif handler code address is in %o4. */
85sparc64_boot:
86 mov %o4, %l7
87
88 /* We need to remap the kernel. Use position independent
89 * code to remap us to KERNBASE.
90 *
91 * SILO can invoke us with 32-bit address masking enabled,
92 * so make sure that's clear.
93 */
94 rdpr %pstate, %g1
95 andn %g1, PSTATE_AM, %g1
96 wrpr %g1, 0x0, %pstate
97 ba,a,pt %xcc, 1f
98
99 .globl prom_finddev_name, prom_chosen_path, prom_root_node
100 .globl prom_getprop_name, prom_mmu_name, prom_peer_name
101 .globl prom_callmethod_name, prom_translate_name, prom_root_compatible
102 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
103 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
104 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
105 .globl prom_compatible_name, prom_cpu_path, prom_cpu_compatible
106 .globl is_sun4v, sun4v_chip_type, prom_set_trap_table_name
107prom_peer_name:
108 .asciz "peer"
109prom_compatible_name:
110 .asciz "compatible"
111prom_finddev_name:
112 .asciz "finddevice"
113prom_chosen_path:
114 .asciz "/chosen"
115prom_cpu_path:
116 .asciz "/cpu"
117prom_getprop_name:
118 .asciz "getprop"
119prom_mmu_name:
120 .asciz "mmu"
121prom_callmethod_name:
122 .asciz "call-method"
123prom_translate_name:
124 .asciz "translate"
125prom_map_name:
126 .asciz "map"
127prom_unmap_name:
128 .asciz "unmap"
129prom_set_trap_table_name:
130 .asciz "SUNW,set-trap-table"
131prom_sun4v_name:
132 .asciz "sun4v"
133prom_niagara_prefix:
134 .asciz "SUNW,UltraSPARC-T"
135prom_sparc_prefix:
136 .asciz "SPARC-"
137prom_sparc64x_prefix:
138 .asciz "SPARC64-X"
139 .align 4
140prom_root_compatible:
141 .skip 64
142prom_cpu_compatible:
143 .skip 64
144prom_root_node:
145 .word 0
146prom_mmu_ihandle_cache:
147 .word 0
148prom_boot_mapped_pc:
149 .word 0
150prom_boot_mapping_mode:
151 .word 0
152 .align 8
153prom_boot_mapping_phys_high:
154 .xword 0
155prom_boot_mapping_phys_low:
156 .xword 0
157is_sun4v:
158 .word 0
159sun4v_chip_type:
160 .word SUN4V_CHIP_INVALID
1611:
162 rd %pc, %l0
163
164 mov (1b - prom_peer_name), %l1
165 sub %l0, %l1, %l1
166 mov 0, %l2
167
168 /* prom_root_node = prom_peer(0) */
169 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
170 mov 1, %l3
171 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
172 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
173 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
174 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
175 call %l7
176 add %sp, (2047 + 128), %o0 ! argument array
177
178 ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
179 mov (1b - prom_root_node), %l1
180 sub %l0, %l1, %l1
181 stw %l4, [%l1]
182
183 mov (1b - prom_getprop_name), %l1
184 mov (1b - prom_compatible_name), %l2
185 mov (1b - prom_root_compatible), %l5
186 sub %l0, %l1, %l1
187 sub %l0, %l2, %l2
188 sub %l0, %l5, %l5
189
190 /* prom_getproperty(prom_root_node, "compatible",
191 * &prom_root_compatible, 64)
192 */
193 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
194 mov 4, %l3
195 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
196 mov 1, %l3
197 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
198 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
199 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
200 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
201 mov 64, %l3
202 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
203 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
204 call %l7
205 add %sp, (2047 + 128), %o0 ! argument array
206
207 mov (1b - prom_finddev_name), %l1
208 mov (1b - prom_chosen_path), %l2
209 mov (1b - prom_boot_mapped_pc), %l3
210 sub %l0, %l1, %l1
211 sub %l0, %l2, %l2
212 sub %l0, %l3, %l3
213 stw %l0, [%l3]
214 sub %sp, (192 + 128), %sp
215
216 /* chosen_node = prom_finddevice("/chosen") */
217 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
218 mov 1, %l3
219 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
220 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
221 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
222 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
223 call %l7
224 add %sp, (2047 + 128), %o0 ! argument array
225
226 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
227
228 mov (1b - prom_getprop_name), %l1
229 mov (1b - prom_mmu_name), %l2
230 mov (1b - prom_mmu_ihandle_cache), %l5
231 sub %l0, %l1, %l1
232 sub %l0, %l2, %l2
233 sub %l0, %l5, %l5
234
235 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
236 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
237 mov 4, %l3
238 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
239 mov 1, %l3
240 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
241 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
242 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
243 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
244 mov 4, %l3
245 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
246 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
247 call %l7
248 add %sp, (2047 + 128), %o0 ! argument array
249
250 mov (1b - prom_callmethod_name), %l1
251 mov (1b - prom_translate_name), %l2
252 sub %l0, %l1, %l1
253 sub %l0, %l2, %l2
254 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
255
256 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
257 mov 3, %l3
258 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
259 mov 5, %l3
260 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
261 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
262 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
263 /* PAGE align */
264 srlx %l0, 13, %l3
265 sllx %l3, 13, %l3
266 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
267 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
268 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
269 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
270 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
271 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
272 call %l7
273 add %sp, (2047 + 128), %o0 ! argument array
274
275 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
276 mov (1b - prom_boot_mapping_mode), %l4
277 sub %l0, %l4, %l4
278 stw %l1, [%l4]
279 mov (1b - prom_boot_mapping_phys_high), %l4
280 sub %l0, %l4, %l4
281 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
282 stx %l2, [%l4 + 0x0]
283 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
284 /* 4MB align */
285 srlx %l3, ILOG2_4MB, %l3
286 sllx %l3, ILOG2_4MB, %l3
287 stx %l3, [%l4 + 0x8]
288
289 /* Leave service as-is, "call-method" */
290 mov 7, %l3
291 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
292 mov 1, %l3
293 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
294 mov (1b - prom_map_name), %l3
295 sub %l0, %l3, %l3
296 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
297 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
298 mov -1, %l3
299 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
300 /* 4MB align the kernel image size. */
301 set (_end - KERNBASE), %l3
302 set ((4 * 1024 * 1024) - 1), %l4
303 add %l3, %l4, %l3
304 andn %l3, %l4, %l3
305 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: roundup(ksize, 4MB)
306 sethi %hi(KERNBASE), %l3
307 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
308 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
309 mov (1b - prom_boot_mapping_phys_low), %l3
310 sub %l0, %l3, %l3
311 ldx [%l3], %l3
312 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
313 call %l7
314 add %sp, (2047 + 128), %o0 ! argument array
315
316 add %sp, (192 + 128), %sp
317
318 sethi %hi(prom_root_compatible), %g1
319 or %g1, %lo(prom_root_compatible), %g1
320 sethi %hi(prom_sun4v_name), %g7
321 or %g7, %lo(prom_sun4v_name), %g7
322 mov 5, %g3
32390: ldub [%g7], %g2
324 ldub [%g1], %g4
325 cmp %g2, %g4
326 bne,pn %icc, 80f
327 add %g7, 1, %g7
328 subcc %g3, 1, %g3
329 bne,pt %xcc, 90b
330 add %g1, 1, %g1
331
332 sethi %hi(is_sun4v), %g1
333 or %g1, %lo(is_sun4v), %g1
334 mov 1, %g7
335 stw %g7, [%g1]
336
337 /* cpu_node = prom_finddevice("/cpu") */
338 mov (1b - prom_finddev_name), %l1
339 mov (1b - prom_cpu_path), %l2
340 sub %l0, %l1, %l1
341 sub %l0, %l2, %l2
342 sub %sp, (192 + 128), %sp
343
344 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
345 mov 1, %l3
346 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
347 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
348 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/cpu"
349 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
350 call %l7
351 add %sp, (2047 + 128), %o0 ! argument array
352
353 ldx [%sp + 2047 + 128 + 0x20], %l4 ! cpu device node
354
355 mov (1b - prom_getprop_name), %l1
356 mov (1b - prom_compatible_name), %l2
357 mov (1b - prom_cpu_compatible), %l5
358 sub %l0, %l1, %l1
359 sub %l0, %l2, %l2
360 sub %l0, %l5, %l5
361
362 /* prom_getproperty(cpu_node, "compatible",
363 * &prom_cpu_compatible, 64)
364 */
365 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
366 mov 4, %l3
367 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
368 mov 1, %l3
369 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
370 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, cpu_node
371 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
372 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_cpu_compatible
373 mov 64, %l3
374 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
375 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
376 call %l7
377 add %sp, (2047 + 128), %o0 ! argument array
378
379 add %sp, (192 + 128), %sp
380
381 sethi %hi(prom_cpu_compatible), %g1
382 or %g1, %lo(prom_cpu_compatible), %g1
383 sethi %hi(prom_niagara_prefix), %g7
384 or %g7, %lo(prom_niagara_prefix), %g7
385 mov 17, %g3
38690: ldub [%g7], %g2
387 ldub [%g1], %g4
388 cmp %g2, %g4
389 bne,pn %icc, 89f
390 add %g7, 1, %g7
391 subcc %g3, 1, %g3
392 bne,pt %xcc, 90b
393 add %g1, 1, %g1
394 ba,pt %xcc, 91f
395 nop
396
39789: sethi %hi(prom_cpu_compatible), %g1
398 or %g1, %lo(prom_cpu_compatible), %g1
399 sethi %hi(prom_sparc_prefix), %g7
400 or %g7, %lo(prom_sparc_prefix), %g7
401 mov 6, %g3
40290: ldub [%g7], %g2
403 ldub [%g1], %g4
404 cmp %g2, %g4
405 bne,pn %icc, 4f
406 add %g7, 1, %g7
407 subcc %g3, 1, %g3
408 bne,pt %xcc, 90b
409 add %g1, 1, %g1
410
411 sethi %hi(prom_cpu_compatible), %g1
412 or %g1, %lo(prom_cpu_compatible), %g1
413 ldub [%g1 + 6], %g2
414 cmp %g2, 'T'
415 be,pt %xcc, 70f
416 cmp %g2, 'M'
417 be,pt %xcc, 70f
418 cmp %g2, 'S'
419 bne,pn %xcc, 49f
420 nop
421
42270: ldub [%g1 + 7], %g2
423 cmp %g2, '3'
424 be,pt %xcc, 5f
425 mov SUN4V_CHIP_NIAGARA3, %g4
426 cmp %g2, '4'
427 be,pt %xcc, 5f
428 mov SUN4V_CHIP_NIAGARA4, %g4
429 cmp %g2, '5'
430 be,pt %xcc, 5f
431 mov SUN4V_CHIP_NIAGARA5, %g4
432 cmp %g2, '6'
433 be,pt %xcc, 5f
434 mov SUN4V_CHIP_SPARC_M6, %g4
435 cmp %g2, '7'
436 be,pt %xcc, 5f
437 mov SUN4V_CHIP_SPARC_M7, %g4
438 cmp %g2, 'N'
439 be,pt %xcc, 5f
440 mov SUN4V_CHIP_SPARC_SN, %g4
441 ba,pt %xcc, 49f
442 nop
443
44491: sethi %hi(prom_cpu_compatible), %g1
445 or %g1, %lo(prom_cpu_compatible), %g1
446 ldub [%g1 + 17], %g2
447 cmp %g2, '1'
448 be,pt %xcc, 5f
449 mov SUN4V_CHIP_NIAGARA1, %g4
450 cmp %g2, '2'
451 be,pt %xcc, 5f
452 mov SUN4V_CHIP_NIAGARA2, %g4
453
4544:
455 /* Athena */
456 sethi %hi(prom_cpu_compatible), %g1
457 or %g1, %lo(prom_cpu_compatible), %g1
458 sethi %hi(prom_sparc64x_prefix), %g7
459 or %g7, %lo(prom_sparc64x_prefix), %g7
460 mov 9, %g3
46141: ldub [%g7], %g2
462 ldub [%g1], %g4
463 cmp %g2, %g4
464 bne,pn %icc, 49f
465 add %g7, 1, %g7
466 subcc %g3, 1, %g3
467 bne,pt %xcc, 41b
468 add %g1, 1, %g1
469 ba,pt %xcc, 5f
470 mov SUN4V_CHIP_SPARC64X, %g4
471
47249:
473 mov SUN4V_CHIP_UNKNOWN, %g4
4745: sethi %hi(sun4v_chip_type), %g2
475 or %g2, %lo(sun4v_chip_type), %g2
476 stw %g4, [%g2]
477
47880:
479 BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
480 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
481 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
482 ba,pt %xcc, spitfire_boot
483 nop
484
485cheetah_plus_boot:
486 /* Preserve OBP chosen DCU and DCR register settings. */
487 ba,pt %xcc, cheetah_generic_boot
488 nop
489
490cheetah_boot:
491 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
492 wr %g1, %asr18
493
494 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
495 or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
496 sllx %g7, 32, %g7
497 or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
498 stxa %g7, [%g0] ASI_DCU_CONTROL_REG
499 membar #Sync
500
501cheetah_generic_boot:
502 mov TSB_EXTENSION_P, %g3
503 stxa %g0, [%g3] ASI_DMMU
504 stxa %g0, [%g3] ASI_IMMU
505 membar #Sync
506
507 mov TSB_EXTENSION_S, %g3
508 stxa %g0, [%g3] ASI_DMMU
509 membar #Sync
510
511 mov TSB_EXTENSION_N, %g3
512 stxa %g0, [%g3] ASI_DMMU
513 stxa %g0, [%g3] ASI_IMMU
514 membar #Sync
515
516 ba,a,pt %xcc, jump_to_sun4u_init
517
518spitfire_boot:
519 /* Typically PROM has already enabled both MMU's and both on-chip
520 * caches, but we do it here anyway just to be paranoid.
521 */
522 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
523 stxa %g1, [%g0] ASI_LSU_CONTROL
524 membar #Sync
525
526jump_to_sun4u_init:
527 /*
528 * Make sure we are in privileged mode, have address masking,
529 * using the ordinary globals and have enabled floating
530 * point.
531 *
532 * Again, typically PROM has left %pil at 13 or similar, and
533 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
534 */
535 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
536 wr %g0, 0, %fprs
537
538 set sun4u_init, %g2
539 jmpl %g2 + %g0, %g0
540 nop
541
542 __REF
543sun4u_init:
544 BRANCH_IF_SUN4V(g1, sun4v_init)
545
546 /* Set ctx 0 */
547 mov PRIMARY_CONTEXT, %g7
548 stxa %g0, [%g7] ASI_DMMU
549 membar #Sync
550
551 mov SECONDARY_CONTEXT, %g7
552 stxa %g0, [%g7] ASI_DMMU
553 membar #Sync
554
555 ba,a,pt %xcc, sun4u_continue
556
557sun4v_init:
558 /* Set ctx 0 */
559 mov PRIMARY_CONTEXT, %g7
560 stxa %g0, [%g7] ASI_MMU
561 membar #Sync
562
563 mov SECONDARY_CONTEXT, %g7
564 stxa %g0, [%g7] ASI_MMU
565 membar #Sync
566 ba,a,pt %xcc, niagara_tlb_fixup
567
568sun4u_continue:
569 BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
570
571 ba,a,pt %xcc, spitfire_tlb_fixup
572
573niagara_tlb_fixup:
574 mov 3, %g2 /* Set TLB type to hypervisor. */
575 sethi %hi(tlb_type), %g1
576 stw %g2, [%g1 + %lo(tlb_type)]
577
578 /* Patch copy/clear ops. */
579 sethi %hi(sun4v_chip_type), %g1
580 lduw [%g1 + %lo(sun4v_chip_type)], %g1
581 cmp %g1, SUN4V_CHIP_NIAGARA1
582 be,pt %xcc, niagara_patch
583 cmp %g1, SUN4V_CHIP_NIAGARA2
584 be,pt %xcc, niagara2_patch
585 nop
586 cmp %g1, SUN4V_CHIP_NIAGARA3
587 be,pt %xcc, niagara2_patch
588 nop
589 cmp %g1, SUN4V_CHIP_NIAGARA4
590 be,pt %xcc, niagara4_patch
591 nop
592 cmp %g1, SUN4V_CHIP_NIAGARA5
593 be,pt %xcc, niagara4_patch
594 nop
595 cmp %g1, SUN4V_CHIP_SPARC_M6
596 be,pt %xcc, niagara4_patch
597 nop
598 cmp %g1, SUN4V_CHIP_SPARC_M7
599 be,pt %xcc, niagara4_patch
600 nop
601 cmp %g1, SUN4V_CHIP_SPARC_SN
602 be,pt %xcc, niagara4_patch
603 nop
604
605 call generic_patch_copyops
606 nop
607 call generic_patch_bzero
608 nop
609 call generic_patch_pageops
610 nop
611
612 ba,a,pt %xcc, 80f
613niagara4_patch:
614 call niagara4_patch_copyops
615 nop
616 call niagara4_patch_bzero
617 nop
618 call niagara4_patch_pageops
619 nop
620
621 ba,a,pt %xcc, 80f
622
623niagara2_patch:
624 call niagara2_patch_copyops
625 nop
626 call niagara_patch_bzero
627 nop
628 call niagara_patch_pageops
629 nop
630
631 ba,a,pt %xcc, 80f
632
633niagara_patch:
634 call niagara_patch_copyops
635 nop
636 call niagara_patch_bzero
637 nop
638 call niagara_patch_pageops
639 nop
640
64180:
642 /* Patch TLB/cache ops. */
643 call hypervisor_patch_cachetlbops
644 nop
645
646 ba,a,pt %xcc, tlb_fixup_done
647
648cheetah_tlb_fixup:
649 mov 2, %g2 /* Set TLB type to cheetah+. */
650 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
651
652 mov 1, %g2 /* Set TLB type to cheetah. */
653
6541: sethi %hi(tlb_type), %g1
655 stw %g2, [%g1 + %lo(tlb_type)]
656
657 /* Patch copy/page operations to cheetah optimized versions. */
658 call cheetah_patch_copyops
659 nop
660 call cheetah_patch_copy_page
661 nop
662 call cheetah_patch_cachetlbops
663 nop
664
665 ba,a,pt %xcc, tlb_fixup_done
666
667spitfire_tlb_fixup:
668 /* Set TLB type to spitfire. */
669 mov 0, %g2
670 sethi %hi(tlb_type), %g1
671 stw %g2, [%g1 + %lo(tlb_type)]
672
673tlb_fixup_done:
674 sethi %hi(init_thread_union), %g6
675 or %g6, %lo(init_thread_union), %g6
676 ldx [%g6 + TI_TASK], %g4
677
678 wr %g0, ASI_P, %asi
679 mov 1, %g1
680 sllx %g1, THREAD_SHIFT, %g1
681 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
682 add %g6, %g1, %sp
683
684 /* Set per-cpu pointer initially to zero, this makes
685 * the boot-cpu use the in-kernel-image per-cpu areas
686 * before setup_per_cpu_area() is invoked.
687 */
688 clr %g5
689
690 wrpr %g0, 0, %wstate
691 wrpr %g0, 0x0, %tl
692
693 /* Clear the bss */
694 sethi %hi(__bss_start), %o0
695 or %o0, %lo(__bss_start), %o0
696 sethi %hi(_end), %o1
697 or %o1, %lo(_end), %o1
698 call __bzero
699 sub %o1, %o0, %o1
700
701 call prom_init
702 mov %l7, %o0 ! OpenPROM cif handler
703
704 /* To create a one-register-window buffer between the kernel's
705 * initial stack and the last stack frame we use from the firmware,
706 * do the rest of the boot from a C helper function.
707 */
708 call start_early_boot
709 nop
710 /* Not reached... */
711
712 .previous
713
714 /* This is meant to allow the sharing of this code between
715 * boot processor invocation (via setup_tba() below) and
716 * secondary processor startup (via trampoline.S). The
717 * former does use this code, the latter does not yet due
718 * to some complexities. That should be fixed up at some
719 * point.
720 *
721 * There used to be enormous complexity wrt. transferring
722 * over from the firmware's trap table to the Linux kernel's.
723 * For example, there was a chicken & egg problem wrt. building
724 * the OBP page tables, yet needing to be on the Linux kernel
725 * trap table (to translate PAGE_OFFSET addresses) in order to
726 * do that.
727 *
728 * We now handle OBP tlb misses differently, via linear lookups
729 * into the prom_trans[] array. So that specific problem no
730 * longer exists. Yet, unfortunately there are still some issues
731 * preventing trampoline.S from using this code... ho hum.
732 */
733 .globl setup_trap_table
734setup_trap_table:
735 save %sp, -192, %sp
736
737 /* Force interrupts to be disabled. */
738 rdpr %pstate, %l0
739 andn %l0, PSTATE_IE, %o1
740 wrpr %o1, 0x0, %pstate
741 rdpr %pil, %l1
742 wrpr %g0, PIL_NORMAL_MAX, %pil
743
744 /* Make the firmware call to jump over to the Linux trap table. */
745 sethi %hi(is_sun4v), %o0
746 lduw [%o0 + %lo(is_sun4v)], %o0
747 brz,pt %o0, 1f
748 nop
749
750 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
751 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
752 stxa %g2, [%g0] ASI_SCRATCHPAD
753
754 /* Compute physical address:
755 *
756 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
757 */
758 sethi %hi(KERNBASE), %g3
759 sub %g2, %g3, %g2
760 sethi %hi(kern_base), %g3
761 ldx [%g3 + %lo(kern_base)], %g3
762 add %g2, %g3, %o1
763 sethi %hi(sparc64_ttable_tl0), %o0
764
765 set prom_set_trap_table_name, %g2
766 stx %g2, [%sp + 2047 + 128 + 0x00]
767 mov 2, %g2
768 stx %g2, [%sp + 2047 + 128 + 0x08]
769 mov 0, %g2
770 stx %g2, [%sp + 2047 + 128 + 0x10]
771 stx %o0, [%sp + 2047 + 128 + 0x18]
772 stx %o1, [%sp + 2047 + 128 + 0x20]
773 sethi %hi(p1275buf), %g2
774 or %g2, %lo(p1275buf), %g2
775 ldx [%g2 + 0x08], %o1
776 call %o1
777 add %sp, (2047 + 128), %o0
778
779 ba,a,pt %xcc, 2f
780
7811: sethi %hi(sparc64_ttable_tl0), %o0
782 set prom_set_trap_table_name, %g2
783 stx %g2, [%sp + 2047 + 128 + 0x00]
784 mov 1, %g2
785 stx %g2, [%sp + 2047 + 128 + 0x08]
786 mov 0, %g2
787 stx %g2, [%sp + 2047 + 128 + 0x10]
788 stx %o0, [%sp + 2047 + 128 + 0x18]
789 sethi %hi(p1275buf), %g2
790 or %g2, %lo(p1275buf), %g2
791 ldx [%g2 + 0x08], %o1
792 call %o1
793 add %sp, (2047 + 128), %o0
794
795 /* Start using proper page size encodings in ctx register. */
7962: sethi %hi(sparc64_kern_pri_context), %g3
797 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
798
799 mov PRIMARY_CONTEXT, %g1
800
801661: stxa %g2, [%g1] ASI_DMMU
802 .section .sun4v_1insn_patch, "ax"
803 .word 661b
804 stxa %g2, [%g1] ASI_MMU
805 .previous
806
807 membar #Sync
808
809 BRANCH_IF_SUN4V(o2, 1f)
810
811 /* Kill PROM timer */
812 sethi %hi(0x80000000), %o2
813 sllx %o2, 32, %o2
814 wr %o2, 0, %tick_cmpr
815
816 BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
817
818 ba,a,pt %xcc, 2f
819
820 /* Disable STICK_INT interrupts. */
8211:
822 sethi %hi(0x80000000), %o2
823 sllx %o2, 32, %o2
824 wr %o2, %asr25
825
8262:
827 wrpr %g0, %g0, %wstate
828
829 call init_irqwork_curcpu
830 nop
831
832 /* Now we can restore interrupt state. */
833 wrpr %l0, 0, %pstate
834 wrpr %l1, 0x0, %pil
835
836 ret
837 restore
838
839 .globl setup_tba
840setup_tba:
841 save %sp, -192, %sp
842
843 /* The boot processor is the only cpu which invokes this
844 * routine, the other cpus set things up via trampoline.S.
845 * So save the OBP trap table address here.
846 */
847 rdpr %tba, %g7
848 sethi %hi(prom_tba), %o1
849 or %o1, %lo(prom_tba), %o1
850 stx %g7, [%o1]
851
852 call setup_trap_table
853 nop
854
855 ret
856 restore
857sparc64_boot_end:
858
859#include "etrap_64.S"
860#include "rtrap_64.S"
861#include "winfixup.S"
862#include "fpu_traps.S"
863#include "ivec.S"
864#include "getsetcc.S"
865#include "utrap.S"
866#include "spiterrs.S"
867#include "cherrs.S"
868#include "misctrap.S"
869#include "syscalls.S"
870#include "helpers.S"
871#include "hvcalls.S"
872#include "sun4v_tlb_miss.S"
873#include "sun4v_ivec.S"
874#include "ktlb.S"
875#include "tsb.S"
876
877/*
878 * The following skip makes sure the trap table in ttable.S is aligned
879 * on a 32K boundary as required by the v9 specs for TBA register.
880 *
881 * We align to a 32K boundary, then we have the 32K kernel TSB,
882 * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
883 */
8841:
885 .skip 0x4000 + _start - 1b
886
887! 0x0000000000408000
888
889 .globl swapper_tsb
890swapper_tsb:
891 .skip (32 * 1024)
892
893 .globl swapper_4m_tsb
894swapper_4m_tsb:
895 .skip (64 * 1024)
896
897! 0x0000000000420000
898
899 /* Some care needs to be exercised if you try to move the
900 * location of the trap table relative to other things. For
901 * one thing there are br* instructions in some of the
902 * trap table entires which branch back to code in ktlb.S
903 * Those instructions can only handle a signed 16-bit
904 * displacement.
905 *
906 * There is a binutils bug (bugzilla #4558) which causes
907 * the relocation overflow checks for such instructions to
908 * not be done correctly. So bintuils will not notice the
909 * error and will instead write junk into the relocation and
910 * you'll have an unbootable kernel.
911 */
912#include "ttable_64.S"
913
914! 0x0000000000428000
915
916#include "systbls_64.S"
917
918 .data
919 .align 8
920 .globl prom_tba, tlb_type
921prom_tba: .xword 0
922tlb_type: .word 0 /* Must NOT end up in BSS */
923 .section ".fixup",#alloc,#execinstr
924
925 .globl __ret_efault, __retl_efault, __ret_one, __retl_one
926ENTRY(__ret_efault)
927 ret
928 restore %g0, -EFAULT, %o0
929ENDPROC(__ret_efault)
930
931ENTRY(__retl_efault)
932 retl
933 mov -EFAULT, %o0
934ENDPROC(__retl_efault)
935
936ENTRY(__retl_one)
937 retl
938 mov 1, %o0
939ENDPROC(__retl_one)
940
941ENTRY(__retl_one_fp)
942 VISExitHalf
943 retl
944 mov 1, %o0
945ENDPROC(__retl_one_fp)
946
947ENTRY(__ret_one_asi)
948 wr %g0, ASI_AIUS, %asi
949 ret
950 restore %g0, 1, %o0
951ENDPROC(__ret_one_asi)
952
953ENTRY(__retl_one_asi)
954 wr %g0, ASI_AIUS, %asi
955 retl
956 mov 1, %o0
957ENDPROC(__retl_one_asi)
958
959ENTRY(__retl_one_asi_fp)
960 wr %g0, ASI_AIUS, %asi
961 VISExitHalf
962 retl
963 mov 1, %o0
964ENDPROC(__retl_one_asi_fp)
965
966ENTRY(__retl_o1)
967 retl
968 mov %o1, %o0
969ENDPROC(__retl_o1)