1// SPDX-License-Identifier: GPL-2.0-or-later
 2/*
 3 * P1020 RDB Device Tree Source (36-bit address map)
 4 *
 5 * Copyright 2009-2011 Freescale Semiconductor Inc.
 
 
 
 
 
 6 */
 7
 8/include/ "p1020si-pre.dtsi"
 9/ {
10	model = "fsl,P1020RDB";
11	compatible = "fsl,P1020RDB";
12
13	memory {
14		device_type = "memory";
15	};
16
17	board_lbc: lbc: localbus@fffe05000 {
18		reg = <0xf 0xffe05000 0 0x1000>;
19
20		/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
21		ranges = <0x0 0x0 0xf 0xef000000 0x01000000
22			  0x1 0x0 0xf 0xffa00000 0x00040000
23			  0x2 0x0 0xf 0xffb00000 0x00020000>;
24	};
25
26	board_soc: soc: soc@fffe00000 {
27		ranges = <0x0 0xf 0xffe00000 0x100000>;
28	};
29
30	pci0: pcie@fffe09000 {
31		reg = <0xf 0xffe09000 0 0x1000>;
32		ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
33			  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
34		pcie@0 {
35			ranges = <0x2000000 0x0 0xc0000000
36				  0x2000000 0x0 0xc0000000
37				  0x0 0x20000000
38
39				  0x1000000 0x0 0x0
40				  0x1000000 0x0 0x0
41				  0x0 0x100000>;
42		};
43	};
44
45	pci1: pcie@fffe0a000 {
46		reg = <0xf 0xffe0a000 0 0x1000>;
47		ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
48			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
49		pcie@0 {
50			ranges = <0x2000000 0x0 0x80000000
51				  0x2000000 0x0 0x80000000
52				  0x0 0x20000000
53
54				  0x1000000 0x0 0x0
55				  0x1000000 0x0 0x0
56				  0x0 0x100000>;
57		};
58	};
59};
60
61/include/ "p1020rdb.dtsi"
62/include/ "p1020si-post.dtsi"

 
 1/*
 2 * P1020 RDB Device Tree Source (36-bit address map)
 3 *
 4 * Copyright 2009-2011 Freescale Semiconductor Inc.
 5 *
 6 * This program is free software; you can redistribute  it and/or modify it
 7 * under  the terms of  the GNU General  Public License as published by the
 8 * Free Software Foundation;  either version 2 of the  License, or (at your
 9 * option) any later version.
10 */
11
12/include/ "p1020si-pre.dtsi"
13/ {
14	model = "fsl,P1020RDB";
15	compatible = "fsl,P1020RDB";
16
17	memory {
18		device_type = "memory";
19	};
20
21	board_lbc: lbc: localbus@fffe05000 {
22		reg = <0xf 0xffe05000 0 0x1000>;
23
24		/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
25		ranges = <0x0 0x0 0xf 0xef000000 0x01000000
26			  0x1 0x0 0xf 0xffa00000 0x00040000
27			  0x2 0x0 0xf 0xffb00000 0x00020000>;
28	};
29
30	board_soc: soc: soc@fffe00000 {
31		ranges = <0x0 0xf 0xffe00000 0x100000>;
32	};
33
34	pci0: pcie@fffe09000 {
35		reg = <0xf 0xffe09000 0 0x1000>;
36		ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
37			  0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
38		pcie@0 {
39			ranges = <0x2000000 0x0 0xc0000000
40				  0x2000000 0x0 0xc0000000
41				  0x0 0x20000000
42
43				  0x1000000 0x0 0x0
44				  0x1000000 0x0 0x0
45				  0x0 0x100000>;
46		};
47	};
48
49	pci1: pcie@fffe0a000 {
50		reg = <0xf 0xffe0a000 0 0x1000>;
51		ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
52			  0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
53		pcie@0 {
54			ranges = <0x2000000 0x0 0x80000000
55				  0x2000000 0x0 0x80000000
56				  0x0 0x20000000
57
58				  0x1000000 0x0 0x0
59				  0x1000000 0x0 0x0
60				  0x0 0x100000>;
61		};
62	};
63};
64
65/include/ "p1020rdb.dtsi"
66/include/ "p1020si-post.dtsi"