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1/*
2 * Switch a MMU context.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 */
11#ifndef _ASM_MMU_CONTEXT_H
12#define _ASM_MMU_CONTEXT_H
13
14#include <linux/errno.h>
15#include <linux/sched.h>
16#include <linux/mm_types.h>
17#include <linux/smp.h>
18#include <linux/slab.h>
19
20#include <asm/barrier.h>
21#include <asm/cacheflush.h>
22#include <asm/dsemul.h>
23#include <asm/ginvt.h>
24#include <asm/hazards.h>
25#include <asm/tlbflush.h>
26#include <asm-generic/mm_hooks.h>
27
28#define htw_set_pwbase(pgd) \
29do { \
30 if (cpu_has_htw) { \
31 write_c0_pwbase(pgd); \
32 back_to_back_c0_hazard(); \
33 } \
34} while (0)
35
36extern void tlbmiss_handler_setup_pgd(unsigned long);
37extern char tlbmiss_handler_setup_pgd_end[];
38
39/* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */
40#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
41do { \
42 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
43 htw_set_pwbase((unsigned long)pgd); \
44} while (0)
45
46#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
47
48#define TLBMISS_HANDLER_RESTORE() \
49 write_c0_xcontext((unsigned long) smp_processor_id() << \
50 SMP_CPUID_REGSHIFT)
51
52#define TLBMISS_HANDLER_SETUP() \
53 do { \
54 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
55 TLBMISS_HANDLER_RESTORE(); \
56 } while (0)
57
58#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
59
60/*
61 * For the fast tlb miss handlers, we keep a per cpu array of pointers
62 * to the current pgd for each processor. Also, the proc. id is stuffed
63 * into the context register.
64 */
65extern unsigned long pgd_current[];
66
67#define TLBMISS_HANDLER_RESTORE() \
68 write_c0_context((unsigned long) smp_processor_id() << \
69 SMP_CPUID_REGSHIFT)
70
71#define TLBMISS_HANDLER_SETUP() \
72 TLBMISS_HANDLER_RESTORE(); \
73 back_to_back_c0_hazard(); \
74 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
75#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
76
77/*
78 * The ginvt instruction will invalidate wired entries when its type field
79 * targets anything other than the entire TLB. That means that if we were to
80 * allow the kernel to create wired entries with the MMID of current->active_mm
81 * then those wired entries could be invalidated when we later use ginvt to
82 * invalidate TLB entries with that MMID.
83 *
84 * In order to prevent ginvt from trashing wired entries, we reserve one MMID
85 * for use by the kernel when creating wired entries. This MMID will never be
86 * assigned to a struct mm, and we'll never target it with a ginvt instruction.
87 */
88#define MMID_KERNEL_WIRED 0
89
90/*
91 * All unused by hardware upper bits will be considered
92 * as a software asid extension.
93 */
94static inline u64 asid_version_mask(unsigned int cpu)
95{
96 unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]);
97
98 return ~(u64)(asid_mask | (asid_mask - 1));
99}
100
101static inline u64 asid_first_version(unsigned int cpu)
102{
103 return ~asid_version_mask(cpu) + 1;
104}
105
106static inline u64 cpu_context(unsigned int cpu, const struct mm_struct *mm)
107{
108 if (cpu_has_mmid)
109 return atomic64_read(&mm->context.mmid);
110
111 return mm->context.asid[cpu];
112}
113
114static inline void set_cpu_context(unsigned int cpu,
115 struct mm_struct *mm, u64 ctx)
116{
117 if (cpu_has_mmid)
118 atomic64_set(&mm->context.mmid, ctx);
119 else
120 mm->context.asid[cpu] = ctx;
121}
122
123#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
124#define cpu_asid(cpu, mm) \
125 (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))
126
127extern void get_new_mmu_context(struct mm_struct *mm);
128extern void check_mmu_context(struct mm_struct *mm);
129extern void check_switch_mmu_context(struct mm_struct *mm);
130
131/*
132 * Initialize the context related info for a new mm_struct
133 * instance.
134 */
135#define init_new_context init_new_context
136static inline int
137init_new_context(struct task_struct *tsk, struct mm_struct *mm)
138{
139 int i;
140
141 if (cpu_has_mmid) {
142 set_cpu_context(0, mm, 0);
143 } else {
144 for_each_possible_cpu(i)
145 set_cpu_context(i, mm, 0);
146 }
147
148 mm->context.bd_emupage_allocmap = NULL;
149 spin_lock_init(&mm->context.bd_emupage_lock);
150 init_waitqueue_head(&mm->context.bd_emupage_queue);
151
152 return 0;
153}
154
155static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
156 struct task_struct *tsk)
157{
158 unsigned int cpu = smp_processor_id();
159 unsigned long flags;
160 local_irq_save(flags);
161
162 htw_stop();
163 check_switch_mmu_context(next);
164
165 /*
166 * Mark current->active_mm as not "active" anymore.
167 * We don't want to mislead possible IPI tlb flush routines.
168 */
169 cpumask_clear_cpu(cpu, mm_cpumask(prev));
170 cpumask_set_cpu(cpu, mm_cpumask(next));
171 htw_start();
172
173 local_irq_restore(flags);
174}
175
176/*
177 * Destroy context related info for an mm_struct that is about
178 * to be put to rest.
179 */
180#define destroy_context destroy_context
181static inline void destroy_context(struct mm_struct *mm)
182{
183 dsemul_mm_cleanup(mm);
184}
185
186static inline void
187drop_mmu_context(struct mm_struct *mm)
188{
189 unsigned long flags;
190 unsigned int cpu;
191 u32 old_mmid;
192 u64 ctx;
193
194 local_irq_save(flags);
195
196 cpu = smp_processor_id();
197 ctx = cpu_context(cpu, mm);
198
199 if (!ctx) {
200 /* no-op */
201 } else if (cpu_has_mmid) {
202 /*
203 * Globally invalidating TLB entries associated with the MMID
204 * is pretty cheap using the GINVT instruction, so we'll do
205 * that rather than incur the overhead of allocating a new
206 * MMID. The latter would be especially difficult since MMIDs
207 * are global & other CPUs may be actively using ctx.
208 */
209 htw_stop();
210 old_mmid = read_c0_memorymapid();
211 write_c0_memorymapid(ctx & cpu_asid_mask(&cpu_data[cpu]));
212 mtc0_tlbw_hazard();
213 ginvt_mmid();
214 sync_ginv();
215 write_c0_memorymapid(old_mmid);
216 instruction_hazard();
217 htw_start();
218 } else if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
219 /*
220 * mm is currently active, so we can't really drop it.
221 * Instead we bump the ASID.
222 */
223 htw_stop();
224 get_new_mmu_context(mm);
225 write_c0_entryhi(cpu_asid(cpu, mm));
226 htw_start();
227 } else {
228 /* will get a new context next time */
229 set_cpu_context(cpu, mm, 0);
230 }
231
232 local_irq_restore(flags);
233}
234
235#include <asm-generic/mmu_context.h>
236
237#endif /* _ASM_MMU_CONTEXT_H */
1/*
2 * Switch a MMU context.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 */
11#ifndef _ASM_MMU_CONTEXT_H
12#define _ASM_MMU_CONTEXT_H
13
14#include <linux/errno.h>
15#include <linux/sched.h>
16#include <linux/smp.h>
17#include <linux/slab.h>
18#include <asm/cacheflush.h>
19#include <asm/hazards.h>
20#include <asm/tlbflush.h>
21#include <asm-generic/mm_hooks.h>
22
23#define htw_set_pwbase(pgd) \
24do { \
25 if (cpu_has_htw) { \
26 write_c0_pwbase(pgd); \
27 back_to_back_c0_hazard(); \
28 } \
29} while (0)
30
31#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
32do { \
33 extern void tlbmiss_handler_setup_pgd(unsigned long); \
34 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
35 htw_set_pwbase((unsigned long)pgd); \
36} while (0)
37
38#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
39
40#define TLBMISS_HANDLER_RESTORE() \
41 write_c0_xcontext((unsigned long) smp_processor_id() << \
42 SMP_CPUID_REGSHIFT)
43
44#define TLBMISS_HANDLER_SETUP() \
45 do { \
46 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
47 TLBMISS_HANDLER_RESTORE(); \
48 } while (0)
49
50#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
51
52/*
53 * For the fast tlb miss handlers, we keep a per cpu array of pointers
54 * to the current pgd for each processor. Also, the proc. id is stuffed
55 * into the context register.
56 */
57extern unsigned long pgd_current[];
58
59#define TLBMISS_HANDLER_RESTORE() \
60 write_c0_context((unsigned long) smp_processor_id() << \
61 SMP_CPUID_REGSHIFT)
62
63#define TLBMISS_HANDLER_SETUP() \
64 TLBMISS_HANDLER_RESTORE(); \
65 back_to_back_c0_hazard(); \
66 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
67#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
68#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
69
70#define ASID_INC 0x40
71#define ASID_MASK 0xfc0
72
73#elif defined(CONFIG_CPU_R8000)
74
75#define ASID_INC 0x10
76#define ASID_MASK 0xff0
77
78#else /* FIXME: not correct for R6000 */
79
80#define ASID_INC 0x1
81#define ASID_MASK 0xff
82
83#endif
84
85#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
86#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
87#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
88
89static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
90{
91}
92
93/*
94 * All unused by hardware upper bits will be considered
95 * as a software asid extension.
96 */
97#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
98#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
99
100/* Normal, classic MIPS get_new_mmu_context */
101static inline void
102get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
103{
104 extern void kvm_local_flush_tlb_all(void);
105 unsigned long asid = asid_cache(cpu);
106
107 if (! ((asid += ASID_INC) & ASID_MASK) ) {
108 if (cpu_has_vtag_icache)
109 flush_icache_all();
110#ifdef CONFIG_KVM
111 kvm_local_flush_tlb_all(); /* start new asid cycle */
112#else
113 local_flush_tlb_all(); /* start new asid cycle */
114#endif
115 if (!asid) /* fix version if needed */
116 asid = ASID_FIRST_VERSION;
117 }
118
119 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
120}
121
122/*
123 * Initialize the context related info for a new mm_struct
124 * instance.
125 */
126static inline int
127init_new_context(struct task_struct *tsk, struct mm_struct *mm)
128{
129 int i;
130
131 for_each_possible_cpu(i)
132 cpu_context(i, mm) = 0;
133
134 atomic_set(&mm->context.fp_mode_switching, 0);
135
136 return 0;
137}
138
139static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
140 struct task_struct *tsk)
141{
142 unsigned int cpu = smp_processor_id();
143 unsigned long flags;
144 local_irq_save(flags);
145
146 htw_stop();
147 /* Check if our ASID is of an older version and thus invalid */
148 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
149 get_new_mmu_context(next, cpu);
150 write_c0_entryhi(cpu_asid(cpu, next));
151 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
152
153 /*
154 * Mark current->active_mm as not "active" anymore.
155 * We don't want to mislead possible IPI tlb flush routines.
156 */
157 cpumask_clear_cpu(cpu, mm_cpumask(prev));
158 cpumask_set_cpu(cpu, mm_cpumask(next));
159 htw_start();
160
161 local_irq_restore(flags);
162}
163
164/*
165 * Destroy context related info for an mm_struct that is about
166 * to be put to rest.
167 */
168static inline void destroy_context(struct mm_struct *mm)
169{
170}
171
172#define deactivate_mm(tsk, mm) do { } while (0)
173
174/*
175 * After we have set current->mm to a new value, this activates
176 * the context for the new mm so we see the new mappings.
177 */
178static inline void
179activate_mm(struct mm_struct *prev, struct mm_struct *next)
180{
181 unsigned long flags;
182 unsigned int cpu = smp_processor_id();
183
184 local_irq_save(flags);
185
186 htw_stop();
187 /* Unconditionally get a new ASID. */
188 get_new_mmu_context(next, cpu);
189
190 write_c0_entryhi(cpu_asid(cpu, next));
191 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
192
193 /* mark mmu ownership change */
194 cpumask_clear_cpu(cpu, mm_cpumask(prev));
195 cpumask_set_cpu(cpu, mm_cpumask(next));
196 htw_start();
197
198 local_irq_restore(flags);
199}
200
201/*
202 * If mm is currently active_mm, we can't really drop it. Instead,
203 * we will get a new one for it.
204 */
205static inline void
206drop_mmu_context(struct mm_struct *mm, unsigned cpu)
207{
208 unsigned long flags;
209
210 local_irq_save(flags);
211 htw_stop();
212
213 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
214 get_new_mmu_context(mm, cpu);
215 write_c0_entryhi(cpu_asid(cpu, mm));
216 } else {
217 /* will get a new context next time */
218 cpu_context(cpu, mm) = 0;
219 }
220 htw_start();
221 local_irq_restore(flags);
222}
223
224#endif /* _ASM_MMU_CONTEXT_H */