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1// SPDX-License-Identifier: GPL-2.0
2#include "versatile-ab.dts"
3
4/ {
5 model = "ARM Versatile PB";
6 compatible = "arm,versatile-pb";
7
8 amba {
9 /* The Versatile PB is using more SIC IRQ lines than the AB */
10 sic: interrupt-controller@10003000 {
11 clear-mask = <0xffffffff>;
12 /*
13 * Valid interrupt lines mask according to
14 * figure 3-30 page 3-74 of ARM DUI 0224B
15 */
16 valid-mask = <0x7fe003ff>;
17 };
18
19 gpio2: gpio@101e6000 {
20 compatible = "arm,pl061", "arm,primecell";
21 reg = <0x101e6000 0x1000>;
22 interrupts = <8>;
23 gpio-controller;
24 #gpio-cells = <2>;
25 interrupt-controller;
26 #interrupt-cells = <2>;
27 clocks = <&pclk>;
28 clock-names = "apb_pclk";
29 };
30
31 gpio3: gpio@101e7000 {
32 compatible = "arm,pl061", "arm,primecell";
33 reg = <0x101e7000 0x1000>;
34 interrupts = <9>;
35 gpio-controller;
36 #gpio-cells = <2>;
37 interrupt-controller;
38 #interrupt-cells = <2>;
39 clocks = <&pclk>;
40 clock-names = "apb_pclk";
41 };
42
43 pci@10001000 {
44 compatible = "arm,versatile-pci";
45 device_type = "pci";
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
50 #address-cells = <3>;
51 #size-cells = <2>;
52 #interrupt-cells = <1>;
53
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
56 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
57
58 interrupt-map-mask = <0x1800 0 0 7>;
59 interrupt-map = <0x1800 0 0 1 &sic 28
60 0x1800 0 0 2 &sic 29
61 0x1800 0 0 3 &sic 30
62 0x1800 0 0 4 &sic 27
63
64 0x1000 0 0 1 &sic 27
65 0x1000 0 0 2 &sic 28
66 0x1000 0 0 3 &sic 29
67 0x1000 0 0 4 &sic 30
68
69 0x0800 0 0 1 &sic 30
70 0x0800 0 0 2 &sic 27
71 0x0800 0 0 3 &sic 28
72 0x0800 0 0 4 &sic 29
73
74 0x0000 0 0 1 &sic 29
75 0x0000 0 0 2 &sic 30
76 0x0000 0 0 3 &sic 27
77 0x0000 0 0 4 &sic 28>;
78 };
79
80 fpga {
81 mmc@5000 {
82 /*
83 * Overrides the interrupt assignment from
84 * the Versatile AB board file.
85 */
86 interrupts-extended = <&sic 22 &sic 23>;
87 };
88 uart@9000 {
89 compatible = "arm,pl011", "arm,primecell";
90 reg = <0x9000 0x1000>;
91 interrupt-parent = <&sic>;
92 interrupts = <6>;
93 clocks = <&xtal24mhz>, <&pclk>;
94 clock-names = "uartclk", "apb_pclk";
95 };
96 sci@a000 {
97 compatible = "arm,primecell";
98 reg = <0xa000 0x1000>;
99 interrupt-parent = <&sic>;
100 interrupts = <5>;
101 clocks = <&xtal24mhz>;
102 clock-names = "apb_pclk";
103 };
104 mmc@b000 {
105 compatible = "arm,pl180", "arm,primecell";
106 reg = <0xb000 0x1000>;
107 interrupt-parent = <&sic>;
108 interrupts = <1>, <2>;
109 clocks = <&xtal24mhz>, <&pclk>;
110 clock-names = "mclk", "apb_pclk";
111 };
112 };
113 };
114};
1#include <versatile-ab.dts>
2
3/ {
4 model = "ARM Versatile PB";
5 compatible = "arm,versatile-pb";
6
7 amba {
8 /* The Versatile PB is using more SIC IRQ lines than the AB */
9 sic: intc@10003000 {
10 clear-mask = <0xffffffff>;
11 /*
12 * Valid interrupt lines mask according to
13 * figure 3-30 page 3-74 of ARM DUI 0224B
14 */
15 valid-mask = <0x7fe003ff>;
16 };
17
18 gpio2: gpio@101e6000 {
19 compatible = "arm,pl061", "arm,primecell";
20 reg = <0x101e6000 0x1000>;
21 interrupts = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
26 clocks = <&pclk>;
27 clock-names = "apb_pclk";
28 };
29
30 gpio3: gpio@101e7000 {
31 compatible = "arm,pl061", "arm,primecell";
32 reg = <0x101e7000 0x1000>;
33 interrupts = <9>;
34 gpio-controller;
35 #gpio-cells = <2>;
36 interrupt-controller;
37 #interrupt-cells = <2>;
38 clocks = <&pclk>;
39 clock-names = "apb_pclk";
40 };
41
42 pci-controller@10001000 {
43 compatible = "arm,versatile-pci";
44 device_type = "pci";
45 reg = <0x10001000 0x1000
46 0x41000000 0x10000
47 0x42000000 0x100000>;
48 bus-range = <0 0xff>;
49 #address-cells = <3>;
50 #size-cells = <2>;
51 #interrupt-cells = <1>;
52
53 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
54 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
55 0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
56
57 interrupt-map-mask = <0x1800 0 0 7>;
58 interrupt-map = <0x1800 0 0 1 &sic 28
59 0x1800 0 0 2 &sic 29
60 0x1800 0 0 3 &sic 30
61 0x1800 0 0 4 &sic 27
62
63 0x1000 0 0 1 &sic 27
64 0x1000 0 0 2 &sic 28
65 0x1000 0 0 3 &sic 29
66 0x1000 0 0 4 &sic 30
67
68 0x0800 0 0 1 &sic 30
69 0x0800 0 0 2 &sic 27
70 0x0800 0 0 3 &sic 28
71 0x0800 0 0 4 &sic 29
72
73 0x0000 0 0 1 &sic 29
74 0x0000 0 0 2 &sic 30
75 0x0000 0 0 3 &sic 27
76 0x0000 0 0 4 &sic 28>;
77 };
78
79 fpga {
80 mmc@5000 {
81 /*
82 * Overrides the interrupt assignment from
83 * the Versatile AB board file.
84 */
85 interrupts-extended = <&sic 22 &sic 23>;
86 };
87 uart@9000 {
88 compatible = "arm,pl011", "arm,primecell";
89 reg = <0x9000 0x1000>;
90 interrupt-parent = <&sic>;
91 interrupts = <6>;
92 clocks = <&xtal24mhz>, <&pclk>;
93 clock-names = "uartclk", "apb_pclk";
94 };
95 sci@a000 {
96 compatible = "arm,primecell";
97 reg = <0xa000 0x1000>;
98 interrupt-parent = <&sic>;
99 interrupts = <5>;
100 clocks = <&xtal24mhz>;
101 clock-names = "apb_pclk";
102 };
103 mmc@b000 {
104 compatible = "arm,pl180", "arm,primecell";
105 reg = <0xb000 0x1000>;
106 interrupt-parent = <&sic>;
107 interrupts = <1>, <2>;
108 clocks = <&xtal24mhz>, <&pclk>;
109 clock-names = "mclk", "apb_pclk";
110 };
111 };
112 };
113};