1/*
  2 * Device Tree Source for UniPhier PH1-sLD8 SoC
  3 *
  4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  5 *
  6 * This file is dual-licensed: you can use it either under the terms
  7 * of the GPL or the X11 license, at your option. Note that this dual
  8 * licensing only applies to this file, and not this project as a
  9 * whole.
 10 *
 11 *  a) This file is free software; you can redistribute it and/or
 12 *     modify it under the terms of the GNU General Public License as
 13 *     published by the Free Software Foundation; either version 2 of the
 14 *     License, or (at your option) any later version.
 15 *
 16 *     This file is distributed in the hope that it will be useful,
 17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19 *     GNU General Public License for more details.
 20 *
 21 * Or, alternatively,
 22 *
 23 *  b) Permission is hereby granted, free of charge, to any person
 24 *     obtaining a copy of this software and associated documentation
 25 *     files (the "Software"), to deal in the Software without
 26 *     restriction, including without limitation the rights to use,
 27 *     copy, modify, merge, publish, distribute, sublicense, and/or
 28 *     sell copies of the Software, and to permit persons to whom the
 29 *     Software is furnished to do so, subject to the following
 30 *     conditions:
 31 *
 32 *     The above copyright notice and this permission notice shall be
 33 *     included in all copies or substantial portions of the Software.
 34 *
 35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 42 *     OTHER DEALINGS IN THE SOFTWARE.
 43 */
 44
 45/include/ "uniphier-common32.dtsi"
 46
 47/ {
 48	compatible = "socionext,ph1-sld8";
 49
 50	cpus {
 51		#address-cells = <1>;
 52		#size-cells = <0>;
 53
 54		cpu@0 {
 55			device_type = "cpu";
 56			compatible = "arm,cortex-a9";
 57			reg = <0>;
 58			next-level-cache = <&l2>;
 59		};
 60	};
 61
 62	clocks {
 63		arm_timer_clk: arm_timer_clk {
 64			#clock-cells = <0>;
 65			compatible = "fixed-clock";
 66			clock-frequency = <50000000>;
 67		};
 68
 69		uart_clk: uart_clk {
 70			#clock-cells = <0>;
 71			compatible = "fixed-clock";
 72			clock-frequency = <80000000>;
 73		};
 74
 75		iobus_clk: iobus_clk {
 76			#clock-cells = <0>;
 77			compatible = "fixed-clock";
 78			clock-frequency = <100000000>;
 79		};
 80	};
 81};
 82
 83&soc {
 84	l2: l2-cache@500c0000 {
 85		compatible = "socionext,uniphier-system-cache";
 86		reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
 87		interrupts = <0 174 4>, <0 175 4>;
 88		cache-unified;
 89		cache-size = <(256 * 1024)>;
 90		cache-sets = <256>;
 91		cache-line-size = <128>;
 92		cache-level = <2>;
 93	};
 94
 95	i2c0: i2c@58400000 {
 96		compatible = "socionext,uniphier-i2c";
 97		status = "disabled";
 98		reg = <0x58400000 0x40>;
 99		#address-cells = <1>;
100		#size-cells = <0>;
101		interrupts = <0 41 1>;
102		pinctrl-names = "default";
103		pinctrl-0 = <&pinctrl_i2c0>;
104		clocks = <&iobus_clk>;
105		clock-frequency = <100000>;
106	};
107
108	i2c1: i2c@58480000 {
109		compatible = "socionext,uniphier-i2c";
110		status = "disabled";
111		reg = <0x58480000 0x40>;
112		#address-cells = <1>;
113		#size-cells = <0>;
114		interrupts = <0 42 1>;
115		pinctrl-names = "default";
116		pinctrl-0 = <&pinctrl_i2c1>;
117		clocks = <&iobus_clk>;
118		clock-frequency = <100000>;
119	};
120
121	/* chip-internal connection for DMD */
122	i2c2: i2c@58500000 {
123		compatible = "socionext,uniphier-i2c";
124		reg = <0x58500000 0x40>;
125		#address-cells = <1>;
126		#size-cells = <0>;
127		interrupts = <0 43 1>;
128		pinctrl-names = "default";
129		pinctrl-0 = <&pinctrl_i2c2>;
130		clocks = <&iobus_clk>;
131		clock-frequency = <400000>;
132	};
133
134	i2c3: i2c@58580000 {
135		compatible = "socionext,uniphier-i2c";
136		status = "disabled";
137		reg = <0x58580000 0x40>;
138		#address-cells = <1>;
139		#size-cells = <0>;
140		interrupts = <0 44 1>;
141		pinctrl-names = "default";
142		pinctrl-0 = <&pinctrl_i2c3>;
143		clocks = <&iobus_clk>;
144		clock-frequency = <100000>;
145	};
146
147	usb0: usb@5a800100 {
148		compatible = "socionext,uniphier-ehci", "generic-ehci";
149		status = "disabled";
150		reg = <0x5a800100 0x100>;
151		interrupts = <0 80 4>;
152		pinctrl-names = "default";
153		pinctrl-0 = <&pinctrl_usb0>;
154	};
155
156	usb1: usb@5a810100 {
157		compatible = "socionext,uniphier-ehci", "generic-ehci";
158		status = "disabled";
159		reg = <0x5a810100 0x100>;
160		interrupts = <0 81 4>;
161		pinctrl-names = "default";
162		pinctrl-0 = <&pinctrl_usb1>;
163	};
164
165	usb2: usb@5a820100 {
166		compatible = "socionext,uniphier-ehci", "generic-ehci";
167		status = "disabled";
168		reg = <0x5a820100 0x100>;
169		interrupts = <0 82 4>;
170		pinctrl-names = "default";
171		pinctrl-0 = <&pinctrl_usb2>;
172	};
173};
174
175&refclk {
176	clock-frequency = <25000000>;
177};
178
179&serial3 {
180	interrupts = <0 29 4>;
181};
182
183&pinctrl {
184	compatible = "socionext,ph1-sld8-pinctrl", "syscon";
185};