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1/*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "armv7-m.dtsi"
49#include <dt-bindings/clock/stm32fx-clock.h>
50#include <dt-bindings/mfd/stm32f4-rcc.h>
51
52/ {
53 #address-cells = <1>;
54 #size-cells = <1>;
55
56 clocks {
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
61 };
62
63 clk_lse: clk-lse {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 };
68
69 clk_lsi: clk-lsi {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
73 };
74
75 clk_i2s_ckin: i2s-ckin {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
79 };
80 };
81
82 soc {
83 romem: efuse@1fff7800 {
84 compatible = "st,stm32f4-otp";
85 reg = <0x1fff7800 0x400>;
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ts_cal1: calib@22c {
89 reg = <0x22c 0x2>;
90 };
91 ts_cal2: calib@22e {
92 reg = <0x22e 0x2>;
93 };
94 };
95
96 timers2: timers@40000000 {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "st,stm32-timers";
100 reg = <0x40000000 0x400>;
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
102 clock-names = "int";
103 status = "disabled";
104
105 pwm {
106 compatible = "st,stm32-pwm";
107 #pwm-cells = <3>;
108 status = "disabled";
109 };
110
111 timer@1 {
112 compatible = "st,stm32-timer-trigger";
113 reg = <1>;
114 status = "disabled";
115 };
116 };
117
118 timers3: timers@40000400 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "st,stm32-timers";
122 reg = <0x40000400 0x400>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
124 clock-names = "int";
125 status = "disabled";
126
127 pwm {
128 compatible = "st,stm32-pwm";
129 #pwm-cells = <3>;
130 status = "disabled";
131 };
132
133 timer@2 {
134 compatible = "st,stm32-timer-trigger";
135 reg = <2>;
136 status = "disabled";
137 };
138 };
139
140 timers4: timers@40000800 {
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "st,stm32-timers";
144 reg = <0x40000800 0x400>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
146 clock-names = "int";
147 status = "disabled";
148
149 pwm {
150 compatible = "st,stm32-pwm";
151 #pwm-cells = <3>;
152 status = "disabled";
153 };
154
155 timer@3 {
156 compatible = "st,stm32-timer-trigger";
157 reg = <3>;
158 status = "disabled";
159 };
160 };
161
162 timers5: timers@40000c00 {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "st,stm32-timers";
166 reg = <0x40000C00 0x400>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
168 clock-names = "int";
169 status = "disabled";
170
171 pwm {
172 compatible = "st,stm32-pwm";
173 #pwm-cells = <3>;
174 status = "disabled";
175 };
176
177 timer@4 {
178 compatible = "st,stm32-timer-trigger";
179 reg = <4>;
180 status = "disabled";
181 };
182 };
183
184 timers6: timers@40001000 {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 compatible = "st,stm32-timers";
188 reg = <0x40001000 0x400>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
190 clock-names = "int";
191 status = "disabled";
192
193 timer@5 {
194 compatible = "st,stm32-timer-trigger";
195 reg = <5>;
196 status = "disabled";
197 };
198 };
199
200 timers7: timers@40001400 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "st,stm32-timers";
204 reg = <0x40001400 0x400>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
206 clock-names = "int";
207 status = "disabled";
208
209 timer@6 {
210 compatible = "st,stm32-timer-trigger";
211 reg = <6>;
212 status = "disabled";
213 };
214 };
215
216 timers12: timers@40001800 {
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "st,stm32-timers";
220 reg = <0x40001800 0x400>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
222 clock-names = "int";
223 status = "disabled";
224
225 pwm {
226 compatible = "st,stm32-pwm";
227 #pwm-cells = <3>;
228 status = "disabled";
229 };
230
231 timer@11 {
232 compatible = "st,stm32-timer-trigger";
233 reg = <11>;
234 status = "disabled";
235 };
236 };
237
238 timers13: timers@40001c00 {
239 compatible = "st,stm32-timers";
240 reg = <0x40001C00 0x400>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
242 clock-names = "int";
243 status = "disabled";
244
245 pwm {
246 compatible = "st,stm32-pwm";
247 #pwm-cells = <3>;
248 status = "disabled";
249 };
250 };
251
252 timers14: timers@40002000 {
253 compatible = "st,stm32-timers";
254 reg = <0x40002000 0x400>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
256 clock-names = "int";
257 status = "disabled";
258
259 pwm {
260 compatible = "st,stm32-pwm";
261 #pwm-cells = <3>;
262 status = "disabled";
263 };
264 };
265
266 rtc: rtc@40002800 {
267 compatible = "st,stm32-rtc";
268 reg = <0x40002800 0x400>;
269 clocks = <&rcc 1 CLK_RTC>;
270 assigned-clocks = <&rcc 1 CLK_RTC>;
271 assigned-clock-parents = <&rcc 1 CLK_LSE>;
272 interrupt-parent = <&exti>;
273 interrupts = <17 1>;
274 st,syscfg = <&pwrcfg 0x00 0x100>;
275 status = "disabled";
276 };
277
278 iwdg: watchdog@40003000 {
279 compatible = "st,stm32-iwdg";
280 reg = <0x40003000 0x400>;
281 clocks = <&clk_lsi>;
282 clock-names = "lsi";
283 status = "disabled";
284 };
285
286 spi2: spi@40003800 {
287 #address-cells = <1>;
288 #size-cells = <0>;
289 compatible = "st,stm32f4-spi";
290 reg = <0x40003800 0x400>;
291 interrupts = <36>;
292 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
293 status = "disabled";
294 };
295
296 spi3: spi@40003c00 {
297 #address-cells = <1>;
298 #size-cells = <0>;
299 compatible = "st,stm32f4-spi";
300 reg = <0x40003c00 0x400>;
301 interrupts = <51>;
302 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
303 status = "disabled";
304 };
305
306 usart2: serial@40004400 {
307 compatible = "st,stm32-uart";
308 reg = <0x40004400 0x400>;
309 interrupts = <38>;
310 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
311 status = "disabled";
312 };
313
314 usart3: serial@40004800 {
315 compatible = "st,stm32-uart";
316 reg = <0x40004800 0x400>;
317 interrupts = <39>;
318 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
319 status = "disabled";
320 dmas = <&dma1 1 4 0x400 0x0>,
321 <&dma1 3 4 0x400 0x0>;
322 dma-names = "rx", "tx";
323 };
324
325 usart4: serial@40004c00 {
326 compatible = "st,stm32-uart";
327 reg = <0x40004c00 0x400>;
328 interrupts = <52>;
329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
330 status = "disabled";
331 };
332
333 usart5: serial@40005000 {
334 compatible = "st,stm32-uart";
335 reg = <0x40005000 0x400>;
336 interrupts = <53>;
337 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
338 status = "disabled";
339 };
340
341 i2c1: i2c@40005400 {
342 compatible = "st,stm32f4-i2c";
343 reg = <0x40005400 0x400>;
344 interrupts = <31>,
345 <32>;
346 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
347 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 status = "disabled";
351 };
352
353 i2c3: i2c@40005c00 {
354 compatible = "st,stm32f4-i2c";
355 reg = <0x40005c00 0x400>;
356 interrupts = <72>,
357 <73>;
358 resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
359 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
360 #address-cells = <1>;
361 #size-cells = <0>;
362 status = "disabled";
363 };
364
365 dac: dac@40007400 {
366 compatible = "st,stm32f4-dac-core";
367 reg = <0x40007400 0x400>;
368 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
369 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
370 clock-names = "pclk";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 status = "disabled";
374
375 dac1: dac@1 {
376 compatible = "st,stm32-dac";
377 #io-channel-cells = <1>;
378 reg = <1>;
379 status = "disabled";
380 };
381
382 dac2: dac@2 {
383 compatible = "st,stm32-dac";
384 #io-channel-cells = <1>;
385 reg = <2>;
386 status = "disabled";
387 };
388 };
389
390 usart7: serial@40007800 {
391 compatible = "st,stm32-uart";
392 reg = <0x40007800 0x400>;
393 interrupts = <82>;
394 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
395 status = "disabled";
396 };
397
398 usart8: serial@40007c00 {
399 compatible = "st,stm32-uart";
400 reg = <0x40007c00 0x400>;
401 interrupts = <83>;
402 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
403 status = "disabled";
404 };
405
406 timers1: timers@40010000 {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 compatible = "st,stm32-timers";
410 reg = <0x40010000 0x400>;
411 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
412 clock-names = "int";
413 status = "disabled";
414
415 pwm {
416 compatible = "st,stm32-pwm";
417 #pwm-cells = <3>;
418 status = "disabled";
419 };
420
421 timer@0 {
422 compatible = "st,stm32-timer-trigger";
423 reg = <0>;
424 status = "disabled";
425 };
426 };
427
428 timers8: timers@40010400 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "st,stm32-timers";
432 reg = <0x40010400 0x400>;
433 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
434 clock-names = "int";
435 status = "disabled";
436
437 pwm {
438 compatible = "st,stm32-pwm";
439 #pwm-cells = <3>;
440 status = "disabled";
441 };
442
443 timer@7 {
444 compatible = "st,stm32-timer-trigger";
445 reg = <7>;
446 status = "disabled";
447 };
448 };
449
450 usart1: serial@40011000 {
451 compatible = "st,stm32-uart";
452 reg = <0x40011000 0x400>;
453 interrupts = <37>;
454 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
455 status = "disabled";
456 dmas = <&dma2 2 4 0x400 0x0>,
457 <&dma2 7 4 0x400 0x0>;
458 dma-names = "rx", "tx";
459 };
460
461 usart6: serial@40011400 {
462 compatible = "st,stm32-uart";
463 reg = <0x40011400 0x400>;
464 interrupts = <71>;
465 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
466 status = "disabled";
467 };
468
469 adc: adc@40012000 {
470 compatible = "st,stm32f4-adc-core";
471 reg = <0x40012000 0x400>;
472 interrupts = <18>;
473 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
474 clock-names = "adc";
475 interrupt-controller;
476 #interrupt-cells = <1>;
477 #address-cells = <1>;
478 #size-cells = <0>;
479 status = "disabled";
480
481 adc1: adc@0 {
482 compatible = "st,stm32f4-adc";
483 #io-channel-cells = <1>;
484 reg = <0x0>;
485 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
486 interrupt-parent = <&adc>;
487 interrupts = <0>;
488 dmas = <&dma2 0 0 0x400 0x0>;
489 dma-names = "rx";
490 status = "disabled";
491 };
492
493 adc2: adc@100 {
494 compatible = "st,stm32f4-adc";
495 #io-channel-cells = <1>;
496 reg = <0x100>;
497 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
498 interrupt-parent = <&adc>;
499 interrupts = <1>;
500 dmas = <&dma2 3 1 0x400 0x0>;
501 dma-names = "rx";
502 status = "disabled";
503 };
504
505 adc3: adc@200 {
506 compatible = "st,stm32f4-adc";
507 #io-channel-cells = <1>;
508 reg = <0x200>;
509 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
510 interrupt-parent = <&adc>;
511 interrupts = <2>;
512 dmas = <&dma2 1 2 0x400 0x0>;
513 dma-names = "rx";
514 status = "disabled";
515 };
516 };
517
518 sdio: mmc@40012c00 {
519 compatible = "arm,pl180", "arm,primecell";
520 arm,primecell-periphid = <0x00880180>;
521 reg = <0x40012c00 0x400>;
522 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
523 clock-names = "apb_pclk";
524 interrupts = <49>;
525 max-frequency = <48000000>;
526 status = "disabled";
527 };
528
529 spi1: spi@40013000 {
530 #address-cells = <1>;
531 #size-cells = <0>;
532 compatible = "st,stm32f4-spi";
533 reg = <0x40013000 0x400>;
534 interrupts = <35>;
535 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
536 status = "disabled";
537 };
538
539 spi4: spi@40013400 {
540 #address-cells = <1>;
541 #size-cells = <0>;
542 compatible = "st,stm32f4-spi";
543 reg = <0x40013400 0x400>;
544 interrupts = <84>;
545 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
546 status = "disabled";
547 };
548
549 syscfg: syscon@40013800 {
550 compatible = "st,stm32-syscfg", "syscon";
551 reg = <0x40013800 0x400>;
552 };
553
554 exti: interrupt-controller@40013c00 {
555 compatible = "st,stm32-exti";
556 interrupt-controller;
557 #interrupt-cells = <2>;
558 reg = <0x40013C00 0x400>;
559 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
560 };
561
562 timers9: timers@40014000 {
563 #address-cells = <1>;
564 #size-cells = <0>;
565 compatible = "st,stm32-timers";
566 reg = <0x40014000 0x400>;
567 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
568 clock-names = "int";
569 status = "disabled";
570
571 pwm {
572 compatible = "st,stm32-pwm";
573 #pwm-cells = <3>;
574 status = "disabled";
575 };
576
577 timer@8 {
578 compatible = "st,stm32-timer-trigger";
579 reg = <8>;
580 status = "disabled";
581 };
582 };
583
584 timers10: timers@40014400 {
585 compatible = "st,stm32-timers";
586 reg = <0x40014400 0x400>;
587 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
588 clock-names = "int";
589 status = "disabled";
590
591 pwm {
592 compatible = "st,stm32-pwm";
593 #pwm-cells = <3>;
594 status = "disabled";
595 };
596 };
597
598 timers11: timers@40014800 {
599 compatible = "st,stm32-timers";
600 reg = <0x40014800 0x400>;
601 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
602 clock-names = "int";
603 status = "disabled";
604
605 pwm {
606 compatible = "st,stm32-pwm";
607 #pwm-cells = <3>;
608 status = "disabled";
609 };
610 };
611
612 spi5: spi@40015000 {
613 #address-cells = <1>;
614 #size-cells = <0>;
615 compatible = "st,stm32f4-spi";
616 reg = <0x40015000 0x400>;
617 interrupts = <85>;
618 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
619 dmas = <&dma2 3 2 0x400 0x0>,
620 <&dma2 4 2 0x400 0x0>;
621 dma-names = "rx", "tx";
622 status = "disabled";
623 };
624
625 spi6: spi@40015400 {
626 #address-cells = <1>;
627 #size-cells = <0>;
628 compatible = "st,stm32f4-spi";
629 reg = <0x40015400 0x400>;
630 interrupts = <86>;
631 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
632 status = "disabled";
633 };
634
635 pwrcfg: power-config@40007000 {
636 compatible = "st,stm32-power-config", "syscon";
637 reg = <0x40007000 0x400>;
638 };
639
640 ltdc: display-controller@40016800 {
641 compatible = "st,stm32-ltdc";
642 reg = <0x40016800 0x200>;
643 interrupts = <88>, <89>;
644 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
645 clocks = <&rcc 1 CLK_LCD>;
646 clock-names = "lcd";
647 status = "disabled";
648 };
649
650 crc: crc@40023000 {
651 compatible = "st,stm32f4-crc";
652 reg = <0x40023000 0x400>;
653 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
654 status = "disabled";
655 };
656
657 rcc: rcc@40023800 {
658 #reset-cells = <1>;
659 #clock-cells = <2>;
660 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
661 reg = <0x40023800 0x400>;
662 clocks = <&clk_hse>, <&clk_i2s_ckin>;
663 st,syscfg = <&pwrcfg>;
664 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
665 assigned-clock-rates = <1000000>;
666 };
667
668 dma1: dma-controller@40026000 {
669 compatible = "st,stm32-dma";
670 reg = <0x40026000 0x400>;
671 interrupts = <11>,
672 <12>,
673 <13>,
674 <14>,
675 <15>,
676 <16>,
677 <17>,
678 <47>;
679 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
680 #dma-cells = <4>;
681 };
682
683 dma2: dma-controller@40026400 {
684 compatible = "st,stm32-dma";
685 reg = <0x40026400 0x400>;
686 interrupts = <56>,
687 <57>,
688 <58>,
689 <59>,
690 <60>,
691 <68>,
692 <69>,
693 <70>;
694 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
695 #dma-cells = <4>;
696 st,mem2mem;
697 };
698
699 mac: ethernet@40028000 {
700 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
701 reg = <0x40028000 0x8000>;
702 reg-names = "stmmaceth";
703 interrupts = <61>;
704 interrupt-names = "macirq";
705 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
706 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
707 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
708 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
709 st,syscon = <&syscfg 0x4>;
710 snps,pbl = <8>;
711 snps,mixed-burst;
712 status = "disabled";
713 };
714
715 dma2d: dma2d@4002b000 {
716 compatible = "st,stm32-dma2d";
717 reg = <0x4002b000 0xc00>;
718 interrupts = <90>;
719 resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
720 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
721 clock-names = "dma2d";
722 status = "disabled";
723 };
724
725 usbotg_hs: usb@40040000 {
726 compatible = "snps,dwc2";
727 reg = <0x40040000 0x40000>;
728 interrupts = <77>;
729 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
730 clock-names = "otg";
731 status = "disabled";
732 };
733
734 usbotg_fs: usb@50000000 {
735 compatible = "st,stm32f4x9-fsotg";
736 reg = <0x50000000 0x40000>;
737 interrupts = <67>;
738 clocks = <&rcc 0 39>;
739 clock-names = "otg";
740 status = "disabled";
741 };
742
743 dcmi: dcmi@50050000 {
744 compatible = "st,stm32-dcmi";
745 reg = <0x50050000 0x400>;
746 interrupts = <78>;
747 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
748 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
749 clock-names = "mclk";
750 pinctrl-names = "default";
751 pinctrl-0 = <&dcmi_pins>;
752 dmas = <&dma2 1 1 0x414 0x3>;
753 dma-names = "tx";
754 status = "disabled";
755 };
756
757 rng: rng@50060800 {
758 compatible = "st,stm32-rng";
759 reg = <0x50060800 0x400>;
760 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
761
762 };
763 };
764};
765
766&systick {
767 clocks = <&rcc 1 SYSTICK>;
768 status = "okay";
769};
1/*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "armv7-m.dtsi"
49#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
50
51/ {
52 clocks {
53 clk_hse: clk-hse {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
56 clock-frequency = <0>;
57 };
58 };
59
60 soc {
61 dma-ranges = <0xc0000000 0x0 0x10000000>;
62
63 timer2: timer@40000000 {
64 compatible = "st,stm32-timer";
65 reg = <0x40000000 0x400>;
66 interrupts = <28>;
67 clocks = <&rcc 0 128>;
68 status = "disabled";
69 };
70
71 timer3: timer@40000400 {
72 compatible = "st,stm32-timer";
73 reg = <0x40000400 0x400>;
74 interrupts = <29>;
75 clocks = <&rcc 0 129>;
76 status = "disabled";
77 };
78
79 timer4: timer@40000800 {
80 compatible = "st,stm32-timer";
81 reg = <0x40000800 0x400>;
82 interrupts = <30>;
83 clocks = <&rcc 0 130>;
84 status = "disabled";
85 };
86
87 timer5: timer@40000c00 {
88 compatible = "st,stm32-timer";
89 reg = <0x40000c00 0x400>;
90 interrupts = <50>;
91 clocks = <&rcc 0 131>;
92 };
93
94 timer6: timer@40001000 {
95 compatible = "st,stm32-timer";
96 reg = <0x40001000 0x400>;
97 interrupts = <54>;
98 clocks = <&rcc 0 132>;
99 status = "disabled";
100 };
101
102 timer7: timer@40001400 {
103 compatible = "st,stm32-timer";
104 reg = <0x40001400 0x400>;
105 interrupts = <55>;
106 clocks = <&rcc 0 133>;
107 status = "disabled";
108 };
109
110 usart2: serial@40004400 {
111 compatible = "st,stm32-usart", "st,stm32-uart";
112 reg = <0x40004400 0x400>;
113 interrupts = <38>;
114 clocks = <&rcc 0 145>;
115 status = "disabled";
116 };
117
118 usart3: serial@40004800 {
119 compatible = "st,stm32-usart", "st,stm32-uart";
120 reg = <0x40004800 0x400>;
121 interrupts = <39>;
122 clocks = <&rcc 0 146>;
123 status = "disabled";
124 };
125
126 usart4: serial@40004c00 {
127 compatible = "st,stm32-uart";
128 reg = <0x40004c00 0x400>;
129 interrupts = <52>;
130 clocks = <&rcc 0 147>;
131 status = "disabled";
132 };
133
134 usart5: serial@40005000 {
135 compatible = "st,stm32-uart";
136 reg = <0x40005000 0x400>;
137 interrupts = <53>;
138 clocks = <&rcc 0 148>;
139 status = "disabled";
140 };
141
142 usart7: serial@40007800 {
143 compatible = "st,stm32-usart", "st,stm32-uart";
144 reg = <0x40007800 0x400>;
145 interrupts = <82>;
146 clocks = <&rcc 0 158>;
147 status = "disabled";
148 };
149
150 usart8: serial@40007c00 {
151 compatible = "st,stm32-usart", "st,stm32-uart";
152 reg = <0x40007c00 0x400>;
153 interrupts = <83>;
154 clocks = <&rcc 0 159>;
155 status = "disabled";
156 };
157
158 usart1: serial@40011000 {
159 compatible = "st,stm32-usart", "st,stm32-uart";
160 reg = <0x40011000 0x400>;
161 interrupts = <37>;
162 clocks = <&rcc 0 164>;
163 status = "disabled";
164 };
165
166 usart6: serial@40011400 {
167 compatible = "st,stm32-usart", "st,stm32-uart";
168 reg = <0x40011400 0x400>;
169 interrupts = <71>;
170 clocks = <&rcc 0 165>;
171 status = "disabled";
172 };
173
174 syscfg: system-config@40013800 {
175 compatible = "syscon";
176 reg = <0x40013800 0x400>;
177 };
178
179 pin-controller {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 compatible = "st,stm32f429-pinctrl";
183 ranges = <0 0x40020000 0x3000>;
184 pins-are-numbered;
185
186 gpioa: gpio@40020000 {
187 gpio-controller;
188 #gpio-cells = <2>;
189 reg = <0x0 0x400>;
190 clocks = <&rcc 0 0>;
191 st,bank-name = "GPIOA";
192 };
193
194 gpiob: gpio@40020400 {
195 gpio-controller;
196 #gpio-cells = <2>;
197 reg = <0x400 0x400>;
198 clocks = <&rcc 0 1>;
199 st,bank-name = "GPIOB";
200 };
201
202 gpioc: gpio@40020800 {
203 gpio-controller;
204 #gpio-cells = <2>;
205 reg = <0x800 0x400>;
206 clocks = <&rcc 0 2>;
207 st,bank-name = "GPIOC";
208 };
209
210 gpiod: gpio@40020c00 {
211 gpio-controller;
212 #gpio-cells = <2>;
213 reg = <0xc00 0x400>;
214 clocks = <&rcc 0 3>;
215 st,bank-name = "GPIOD";
216 };
217
218 gpioe: gpio@40021000 {
219 gpio-controller;
220 #gpio-cells = <2>;
221 reg = <0x1000 0x400>;
222 clocks = <&rcc 0 4>;
223 st,bank-name = "GPIOE";
224 };
225
226 gpiof: gpio@40021400 {
227 gpio-controller;
228 #gpio-cells = <2>;
229 reg = <0x1400 0x400>;
230 clocks = <&rcc 0 5>;
231 st,bank-name = "GPIOF";
232 };
233
234 gpiog: gpio@40021800 {
235 gpio-controller;
236 #gpio-cells = <2>;
237 reg = <0x1800 0x400>;
238 clocks = <&rcc 0 6>;
239 st,bank-name = "GPIOG";
240 };
241
242 gpioh: gpio@40021c00 {
243 gpio-controller;
244 #gpio-cells = <2>;
245 reg = <0x1c00 0x400>;
246 clocks = <&rcc 0 7>;
247 st,bank-name = "GPIOH";
248 };
249
250 gpioi: gpio@40022000 {
251 gpio-controller;
252 #gpio-cells = <2>;
253 reg = <0x2000 0x400>;
254 clocks = <&rcc 0 8>;
255 st,bank-name = "GPIOI";
256 };
257
258 gpioj: gpio@40022400 {
259 gpio-controller;
260 #gpio-cells = <2>;
261 reg = <0x2400 0x400>;
262 clocks = <&rcc 0 9>;
263 st,bank-name = "GPIOJ";
264 };
265
266 gpiok: gpio@40022800 {
267 gpio-controller;
268 #gpio-cells = <2>;
269 reg = <0x2800 0x400>;
270 clocks = <&rcc 0 10>;
271 st,bank-name = "GPIOK";
272 };
273
274 usart1_pins_a: usart1@0 {
275 pins1 {
276 pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
277 bias-disable;
278 drive-push-pull;
279 slew-rate = <0>;
280 };
281 pins2 {
282 pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
283 bias-disable;
284 };
285 };
286
287 usbotg_hs_pins_a: usbotg_hs@0 {
288 pins {
289 pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
290 <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
291 <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
292 <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
293 <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
294 <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
295 <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
296 <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
297 <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
298 <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
299 <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
300 <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
301 bias-disable;
302 drive-push-pull;
303 slew-rate = <2>;
304 };
305 };
306
307 ethernet0_mii: mii@0 {
308 pins {
309 pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
310 <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
311 <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
312 <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
313 <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
314 <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
315 <STM32F429_PA2_FUNC_ETH_MDIO>,
316 <STM32F429_PC1_FUNC_ETH_MDC>,
317 <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
318 <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
319 <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
320 <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
321 <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
322 <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
323 slew-rate = <2>;
324 };
325 };
326 };
327
328 rcc: rcc@40023810 {
329 #clock-cells = <2>;
330 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
331 reg = <0x40023800 0x400>;
332 clocks = <&clk_hse>;
333 };
334
335 dma1: dma-controller@40026000 {
336 compatible = "st,stm32-dma";
337 reg = <0x40026000 0x400>;
338 interrupts = <11>,
339 <12>,
340 <13>,
341 <14>,
342 <15>,
343 <16>,
344 <17>,
345 <47>;
346 clocks = <&rcc 0 21>;
347 #dma-cells = <4>;
348 };
349
350 dma2: dma-controller@40026400 {
351 compatible = "st,stm32-dma";
352 reg = <0x40026400 0x400>;
353 interrupts = <56>,
354 <57>,
355 <58>,
356 <59>,
357 <60>,
358 <68>,
359 <69>,
360 <70>;
361 clocks = <&rcc 0 22>;
362 #dma-cells = <4>;
363 st,mem2mem;
364 };
365
366 ethernet0: dwmac@40028000 {
367 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
368 reg = <0x40028000 0x8000>;
369 reg-names = "stmmaceth";
370 interrupts = <61>, <62>;
371 interrupt-names = "macirq", "eth_wake_irq";
372 clock-names = "stmmaceth", "tx-clk", "rx-clk";
373 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
374 st,syscon = <&syscfg 0x4>;
375 snps,pbl = <8>;
376 snps,mixed-burst;
377 dma-ranges;
378 status = "disabled";
379 };
380
381 usbotg_hs: usb@40040000 {
382 compatible = "snps,dwc2";
383 dma-ranges;
384 reg = <0x40040000 0x40000>;
385 interrupts = <77>;
386 clocks = <&rcc 0 29>;
387 clock-names = "otg";
388 status = "disabled";
389 };
390
391 rng: rng@50060800 {
392 compatible = "st,stm32-rng";
393 reg = <0x50060800 0x400>;
394 interrupts = <80>;
395 clocks = <&rcc 0 38>;
396 };
397 };
398};
399
400&systick {
401 clocks = <&rcc 1 0>;
402 status = "okay";
403};