1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with
 4 * CAN support
 5 *
 6 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 
 
 7 */
 8
 9#include <dt-bindings/pinctrl/at91.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13	ahb {
14		apb {
15			pinctrl@fffff200 {
16				can0 {
17					pinctrl_can0_rx_tx: can0_rx_tx {
18						atmel,pins =
19							<AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
20							 AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
21					};
22				};
23
24				can1 {
25					pinctrl_can1_rx_tx: can1_rx_tx {
26						atmel,pins =
27							<AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB14 periph B RX, conflicts with GCRS */
28							 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB15 periph B TX, conflicts with GCOL */
29					};
30				};
31
32			};
33
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
34			can0: can@f000c000 {
35				compatible = "atmel,at91sam9x5-can";
36				reg = <0xf000c000 0x300>;
37				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
38				pinctrl-names = "default";
39				pinctrl-0 = <&pinctrl_can0_rx_tx>;
40				clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
41				clock-names = "can_clk";
42				status = "disabled";
43			};
44
45			can1: can@f8010000 {
46				compatible = "atmel,at91sam9x5-can";
47				reg = <0xf8010000 0x300>;
48				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
49				pinctrl-names = "default";
50				pinctrl-0 = <&pinctrl_can1_rx_tx>;
51				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
52				clock-names = "can_clk";
53				status = "disabled";
54			};
55		};
56	};
57};

 
 1/*
 2 * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with
 3 * CAN support
 4 *
 5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
 6 *
 7 * Licensed under GPLv2.
 8 */
 9
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14	ahb {
15		apb {
16			pinctrl@fffff200 {
17				can0 {
18					pinctrl_can0_rx_tx: can0_rx_tx {
19						atmel,pins =
20							<AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE	/* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
21							 AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>;	/* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
22					};
23				};
24
25				can1 {
26					pinctrl_can1_rx_tx: can1_rx_tx {
27						atmel,pins =
28							<AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PB14 periph B RX, conflicts with GCRS */
29							 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB15 periph B TX, conflicts with GCOL */
30					};
31				};
32
33			};
34
35			pmc: pmc@fffffc00 {
36				periphck {
37					can0_clk: can0_clk {
38						#clock-cells = <0>;
39						reg = <40>;
40						atmel,clk-output-range = <0 66000000>;
41					};
42
43					can1_clk: can1_clk {
44						#clock-cells = <0>;
45						reg = <41>;
46						atmel,clk-output-range = <0 66000000>;
47					};
48				};
49			};
50
51			can0: can@f000c000 {
52				compatible = "atmel,at91sam9x5-can";
53				reg = <0xf000c000 0x300>;
54				interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
55				pinctrl-names = "default";
56				pinctrl-0 = <&pinctrl_can0_rx_tx>;
57				clocks = <&can0_clk>;
58				clock-names = "can_clk";
59				status = "disabled";
60			};
61
62			can1: can@f8010000 {
63				compatible = "atmel,at91sam9x5-can";
64				reg = <0xf8010000 0x300>;
65				interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
66				pinctrl-names = "default";
67				pinctrl-0 = <&pinctrl_can1_rx_tx>;
68				clocks = <&can1_clk>;
69				clock-names = "can_clk";
70				status = "disabled";
71			};
72		};
73	};
74};