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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car E2 (R8A77940) SoC
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2014 Ulrich Hecht
7 */
8
9#include <dt-bindings/clock/r8a7794-cpg-mssr.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/power/r8a7794-sysc.h>
13
14/ {
15 compatible = "renesas,r8a7794";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 i2c0 = &i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 i2c4 = &i2c4;
25 i2c5 = &i2c5;
26 i2c6 = &i2c6;
27 i2c7 = &i2c7;
28 spi0 = &qspi;
29 vin0 = &vin0;
30 vin1 = &vin1;
31 };
32
33 /*
34 * The external audio clocks are configured as 0 Hz fixed frequency
35 * clocks by default.
36 * Boards that provide audio clocks should override them.
37 */
38 audio_clka: audio_clka {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <0>;
42 };
43 audio_clkb: audio_clkb {
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <0>;
47 };
48 audio_clkc: audio_clkc {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <0>;
52 };
53
54 /* External CAN clock */
55 can_clk: can {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 /* This value must be overridden by the board. */
59 clock-frequency = <0>;
60 };
61
62 cpus {
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 cpu0: cpu@0 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a7";
69 reg = <0>;
70 clock-frequency = <1000000000>;
71 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
72 power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
73 enable-method = "renesas,apmu";
74 next-level-cache = <&L2_CA7>;
75 };
76
77 cpu1: cpu@1 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a7";
80 reg = <1>;
81 clock-frequency = <1000000000>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
83 power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
84 enable-method = "renesas,apmu";
85 next-level-cache = <&L2_CA7>;
86 };
87
88 L2_CA7: cache-controller-0 {
89 compatible = "cache";
90 power-domains = <&sysc R8A7794_PD_CA7_SCU>;
91 cache-unified;
92 cache-level = <2>;
93 };
94 };
95
96 /* External root clock */
97 extal_clk: extal {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 /* This value must be overridden by the board. */
101 clock-frequency = <0>;
102 };
103
104 pmu {
105 compatible = "arm,cortex-a7-pmu";
106 interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
107 <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-affinity = <&cpu0>, <&cpu1>;
109 };
110
111 /* External SCIF clock */
112 scif_clk: scif {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 /* This value must be overridden by the board. */
116 clock-frequency = <0>;
117 };
118
119 soc {
120 compatible = "simple-bus";
121 interrupt-parent = <&gic>;
122
123 #address-cells = <2>;
124 #size-cells = <2>;
125 ranges;
126
127 rwdt: watchdog@e6020000 {
128 compatible = "renesas,r8a7794-wdt",
129 "renesas,rcar-gen2-wdt";
130 reg = <0 0xe6020000 0 0x0c>;
131 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&cpg CPG_MOD 402>;
133 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
134 resets = <&cpg 402>;
135 status = "disabled";
136 };
137
138 gpio0: gpio@e6050000 {
139 compatible = "renesas,gpio-r8a7794",
140 "renesas,rcar-gen2-gpio";
141 reg = <0 0xe6050000 0 0x50>;
142 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
143 #gpio-cells = <2>;
144 gpio-controller;
145 gpio-ranges = <&pfc 0 0 32>;
146 #interrupt-cells = <2>;
147 interrupt-controller;
148 clocks = <&cpg CPG_MOD 912>;
149 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
150 resets = <&cpg 912>;
151 };
152
153 gpio1: gpio@e6051000 {
154 compatible = "renesas,gpio-r8a7794",
155 "renesas,rcar-gen2-gpio";
156 reg = <0 0xe6051000 0 0x50>;
157 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
158 #gpio-cells = <2>;
159 gpio-controller;
160 gpio-ranges = <&pfc 0 32 26>;
161 #interrupt-cells = <2>;
162 interrupt-controller;
163 clocks = <&cpg CPG_MOD 911>;
164 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
165 resets = <&cpg 911>;
166 };
167
168 gpio2: gpio@e6052000 {
169 compatible = "renesas,gpio-r8a7794",
170 "renesas,rcar-gen2-gpio";
171 reg = <0 0xe6052000 0 0x50>;
172 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
173 #gpio-cells = <2>;
174 gpio-controller;
175 gpio-ranges = <&pfc 0 64 32>;
176 #interrupt-cells = <2>;
177 interrupt-controller;
178 clocks = <&cpg CPG_MOD 910>;
179 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
180 resets = <&cpg 910>;
181 };
182
183 gpio3: gpio@e6053000 {
184 compatible = "renesas,gpio-r8a7794",
185 "renesas,rcar-gen2-gpio";
186 reg = <0 0xe6053000 0 0x50>;
187 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
188 #gpio-cells = <2>;
189 gpio-controller;
190 gpio-ranges = <&pfc 0 96 32>;
191 #interrupt-cells = <2>;
192 interrupt-controller;
193 clocks = <&cpg CPG_MOD 909>;
194 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
195 resets = <&cpg 909>;
196 };
197
198 gpio4: gpio@e6054000 {
199 compatible = "renesas,gpio-r8a7794",
200 "renesas,rcar-gen2-gpio";
201 reg = <0 0xe6054000 0 0x50>;
202 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
203 #gpio-cells = <2>;
204 gpio-controller;
205 gpio-ranges = <&pfc 0 128 32>;
206 #interrupt-cells = <2>;
207 interrupt-controller;
208 clocks = <&cpg CPG_MOD 908>;
209 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
210 resets = <&cpg 908>;
211 };
212
213 gpio5: gpio@e6055000 {
214 compatible = "renesas,gpio-r8a7794",
215 "renesas,rcar-gen2-gpio";
216 reg = <0 0xe6055000 0 0x50>;
217 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
218 #gpio-cells = <2>;
219 gpio-controller;
220 gpio-ranges = <&pfc 0 160 28>;
221 #interrupt-cells = <2>;
222 interrupt-controller;
223 clocks = <&cpg CPG_MOD 907>;
224 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
225 resets = <&cpg 907>;
226 };
227
228 gpio6: gpio@e6055400 {
229 compatible = "renesas,gpio-r8a7794",
230 "renesas,rcar-gen2-gpio";
231 reg = <0 0xe6055400 0 0x50>;
232 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
233 #gpio-cells = <2>;
234 gpio-controller;
235 gpio-ranges = <&pfc 0 192 26>;
236 #interrupt-cells = <2>;
237 interrupt-controller;
238 clocks = <&cpg CPG_MOD 905>;
239 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
240 resets = <&cpg 905>;
241 };
242
243 pfc: pinctrl@e6060000 {
244 compatible = "renesas,pfc-r8a7794";
245 reg = <0 0xe6060000 0 0x11c>;
246 };
247
248 cpg: clock-controller@e6150000 {
249 compatible = "renesas,r8a7794-cpg-mssr";
250 reg = <0 0xe6150000 0 0x1000>;
251 clocks = <&extal_clk>, <&usb_extal_clk>;
252 clock-names = "extal", "usb_extal";
253 #clock-cells = <2>;
254 #power-domain-cells = <0>;
255 #reset-cells = <1>;
256 };
257
258 apmu@e6151000 {
259 compatible = "renesas,r8a7794-apmu", "renesas,apmu";
260 reg = <0 0xe6151000 0 0x188>;
261 cpus = <&cpu0>, <&cpu1>;
262 };
263
264 rst: reset-controller@e6160000 {
265 compatible = "renesas,r8a7794-rst";
266 reg = <0 0xe6160000 0 0x0100>;
267 };
268
269 sysc: system-controller@e6180000 {
270 compatible = "renesas,r8a7794-sysc";
271 reg = <0 0xe6180000 0 0x0200>;
272 #power-domain-cells = <1>;
273 };
274
275 irqc0: interrupt-controller@e61c0000 {
276 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
277 #interrupt-cells = <2>;
278 interrupt-controller;
279 reg = <0 0xe61c0000 0 0x200>;
280 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&cpg CPG_MOD 407>;
291 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
292 resets = <&cpg 407>;
293 };
294
295 ipmmu_sy0: iommu@e6280000 {
296 compatible = "renesas,ipmmu-r8a7794",
297 "renesas,ipmmu-vmsa";
298 reg = <0 0xe6280000 0 0x1000>;
299 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
301 #iommu-cells = <1>;
302 status = "disabled";
303 };
304
305 ipmmu_sy1: iommu@e6290000 {
306 compatible = "renesas,ipmmu-r8a7794",
307 "renesas,ipmmu-vmsa";
308 reg = <0 0xe6290000 0 0x1000>;
309 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
310 #iommu-cells = <1>;
311 status = "disabled";
312 };
313
314 ipmmu_ds: iommu@e6740000 {
315 compatible = "renesas,ipmmu-r8a7794",
316 "renesas,ipmmu-vmsa";
317 reg = <0 0xe6740000 0 0x1000>;
318 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
320 #iommu-cells = <1>;
321 status = "disabled";
322 };
323
324 ipmmu_mp: iommu@ec680000 {
325 compatible = "renesas,ipmmu-r8a7794",
326 "renesas,ipmmu-vmsa";
327 reg = <0 0xec680000 0 0x1000>;
328 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
329 #iommu-cells = <1>;
330 status = "disabled";
331 };
332
333 ipmmu_mx: iommu@fe951000 {
334 compatible = "renesas,ipmmu-r8a7794",
335 "renesas,ipmmu-vmsa";
336 reg = <0 0xfe951000 0 0x1000>;
337 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
339 #iommu-cells = <1>;
340 status = "disabled";
341 };
342
343 ipmmu_gp: iommu@e62a0000 {
344 compatible = "renesas,ipmmu-r8a7794",
345 "renesas,ipmmu-vmsa";
346 reg = <0 0xe62a0000 0 0x1000>;
347 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
349 #iommu-cells = <1>;
350 status = "disabled";
351 };
352
353 icram0: sram@e63a0000 {
354 compatible = "mmio-sram";
355 reg = <0 0xe63a0000 0 0x12000>;
356 #address-cells = <1>;
357 #size-cells = <1>;
358 ranges = <0 0 0xe63a0000 0x12000>;
359 };
360
361 icram1: sram@e63c0000 {
362 compatible = "mmio-sram";
363 reg = <0 0xe63c0000 0 0x1000>;
364 #address-cells = <1>;
365 #size-cells = <1>;
366 ranges = <0 0 0xe63c0000 0x1000>;
367
368 smp-sram@0 {
369 compatible = "renesas,smp-sram";
370 reg = <0 0x100>;
371 };
372 };
373
374 /* The memory map in the User's Manual maps the cores to
375 * bus numbers
376 */
377 i2c0: i2c@e6508000 {
378 compatible = "renesas,i2c-r8a7794",
379 "renesas,rcar-gen2-i2c";
380 reg = <0 0xe6508000 0 0x40>;
381 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&cpg CPG_MOD 931>;
383 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
384 resets = <&cpg 931>;
385 #address-cells = <1>;
386 #size-cells = <0>;
387 i2c-scl-internal-delay-ns = <6>;
388 status = "disabled";
389 };
390
391 i2c1: i2c@e6518000 {
392 compatible = "renesas,i2c-r8a7794",
393 "renesas,rcar-gen2-i2c";
394 reg = <0 0xe6518000 0 0x40>;
395 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cpg CPG_MOD 930>;
397 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
398 resets = <&cpg 930>;
399 #address-cells = <1>;
400 #size-cells = <0>;
401 i2c-scl-internal-delay-ns = <6>;
402 status = "disabled";
403 };
404
405 i2c2: i2c@e6530000 {
406 compatible = "renesas,i2c-r8a7794",
407 "renesas,rcar-gen2-i2c";
408 reg = <0 0xe6530000 0 0x40>;
409 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&cpg CPG_MOD 929>;
411 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
412 resets = <&cpg 929>;
413 #address-cells = <1>;
414 #size-cells = <0>;
415 i2c-scl-internal-delay-ns = <6>;
416 status = "disabled";
417 };
418
419 i2c3: i2c@e6540000 {
420 compatible = "renesas,i2c-r8a7794",
421 "renesas,rcar-gen2-i2c";
422 reg = <0 0xe6540000 0 0x40>;
423 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&cpg CPG_MOD 928>;
425 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
426 resets = <&cpg 928>;
427 #address-cells = <1>;
428 #size-cells = <0>;
429 i2c-scl-internal-delay-ns = <6>;
430 status = "disabled";
431 };
432
433 i2c4: i2c@e6520000 {
434 compatible = "renesas,i2c-r8a7794",
435 "renesas,rcar-gen2-i2c";
436 reg = <0 0xe6520000 0 0x40>;
437 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&cpg CPG_MOD 927>;
439 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
440 resets = <&cpg 927>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 i2c-scl-internal-delay-ns = <6>;
444 status = "disabled";
445 };
446
447 i2c5: i2c@e6528000 {
448 compatible = "renesas,i2c-r8a7794",
449 "renesas,rcar-gen2-i2c";
450 reg = <0 0xe6528000 0 0x40>;
451 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&cpg CPG_MOD 925>;
453 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
454 resets = <&cpg 925>;
455 #address-cells = <1>;
456 #size-cells = <0>;
457 i2c-scl-internal-delay-ns = <6>;
458 status = "disabled";
459 };
460
461 i2c6: i2c@e6500000 {
462 compatible = "renesas,iic-r8a7794",
463 "renesas,rcar-gen2-iic",
464 "renesas,rmobile-iic";
465 reg = <0 0xe6500000 0 0x425>;
466 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&cpg CPG_MOD 318>;
468 dmas = <&dmac0 0x61>, <&dmac0 0x62>,
469 <&dmac1 0x61>, <&dmac1 0x62>;
470 dma-names = "tx", "rx", "tx", "rx";
471 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
472 resets = <&cpg 318>;
473 #address-cells = <1>;
474 #size-cells = <0>;
475 status = "disabled";
476 };
477
478 i2c7: i2c@e6510000 {
479 compatible = "renesas,iic-r8a7794",
480 "renesas,rcar-gen2-iic",
481 "renesas,rmobile-iic";
482 reg = <0 0xe6510000 0 0x425>;
483 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cpg CPG_MOD 323>;
485 dmas = <&dmac0 0x65>, <&dmac0 0x66>,
486 <&dmac1 0x65>, <&dmac1 0x66>;
487 dma-names = "tx", "rx", "tx", "rx";
488 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
489 resets = <&cpg 323>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 status = "disabled";
493 };
494
495 hsusb: usb@e6590000 {
496 compatible = "renesas,usbhs-r8a7794",
497 "renesas,rcar-gen2-usbhs";
498 reg = <0 0xe6590000 0 0x100>;
499 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&cpg CPG_MOD 704>;
501 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
502 resets = <&cpg 704>;
503 renesas,buswait = <4>;
504 phys = <&usb0 1>;
505 phy-names = "usb";
506 status = "disabled";
507 };
508
509 usbphy: usb-phy-controller@e6590100 {
510 compatible = "renesas,usb-phy-r8a7794",
511 "renesas,rcar-gen2-usb-phy";
512 reg = <0 0xe6590100 0 0x100>;
513 #address-cells = <1>;
514 #size-cells = <0>;
515 clocks = <&cpg CPG_MOD 704>;
516 clock-names = "usbhs";
517 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
518 resets = <&cpg 704>;
519 status = "disabled";
520
521 usb0: usb-phy@0 {
522 reg = <0>;
523 #phy-cells = <1>;
524 };
525 usb2: usb-phy@2 {
526 reg = <2>;
527 #phy-cells = <1>;
528 };
529 };
530
531 dmac0: dma-controller@e6700000 {
532 compatible = "renesas,dmac-r8a7794",
533 "renesas,rcar-dmac";
534 reg = <0 0xe6700000 0 0x20000>;
535 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
551 interrupt-names = "error",
552 "ch0", "ch1", "ch2", "ch3",
553 "ch4", "ch5", "ch6", "ch7",
554 "ch8", "ch9", "ch10", "ch11",
555 "ch12", "ch13", "ch14";
556 clocks = <&cpg CPG_MOD 219>;
557 clock-names = "fck";
558 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
559 resets = <&cpg 219>;
560 #dma-cells = <1>;
561 dma-channels = <15>;
562 };
563
564 dmac1: dma-controller@e6720000 {
565 compatible = "renesas,dmac-r8a7794",
566 "renesas,rcar-dmac";
567 reg = <0 0xe6720000 0 0x20000>;
568 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
584 interrupt-names = "error",
585 "ch0", "ch1", "ch2", "ch3",
586 "ch4", "ch5", "ch6", "ch7",
587 "ch8", "ch9", "ch10", "ch11",
588 "ch12", "ch13", "ch14";
589 clocks = <&cpg CPG_MOD 218>;
590 clock-names = "fck";
591 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
592 resets = <&cpg 218>;
593 #dma-cells = <1>;
594 dma-channels = <15>;
595 };
596
597 avb: ethernet@e6800000 {
598 compatible = "renesas,etheravb-r8a7794",
599 "renesas,etheravb-rcar-gen2";
600 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
601 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&cpg CPG_MOD 812>;
603 clock-names = "fck";
604 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
605 resets = <&cpg 812>;
606 #address-cells = <1>;
607 #size-cells = <0>;
608 status = "disabled";
609 };
610
611 qspi: spi@e6b10000 {
612 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
613 reg = <0 0xe6b10000 0 0x2c>;
614 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&cpg CPG_MOD 917>;
616 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
617 <&dmac1 0x17>, <&dmac1 0x18>;
618 dma-names = "tx", "rx", "tx", "rx";
619 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
620 resets = <&cpg 917>;
621 num-cs = <1>;
622 #address-cells = <1>;
623 #size-cells = <0>;
624 status = "disabled";
625 };
626
627 scifa0: serial@e6c40000 {
628 compatible = "renesas,scifa-r8a7794",
629 "renesas,rcar-gen2-scifa", "renesas,scifa";
630 reg = <0 0xe6c40000 0 64>;
631 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&cpg CPG_MOD 204>;
633 clock-names = "fck";
634 dmas = <&dmac0 0x21>, <&dmac0 0x22>,
635 <&dmac1 0x21>, <&dmac1 0x22>;
636 dma-names = "tx", "rx", "tx", "rx";
637 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
638 resets = <&cpg 204>;
639 status = "disabled";
640 };
641
642 scifa1: serial@e6c50000 {
643 compatible = "renesas,scifa-r8a7794",
644 "renesas,rcar-gen2-scifa", "renesas,scifa";
645 reg = <0 0xe6c50000 0 64>;
646 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&cpg CPG_MOD 203>;
648 clock-names = "fck";
649 dmas = <&dmac0 0x25>, <&dmac0 0x26>,
650 <&dmac1 0x25>, <&dmac1 0x26>;
651 dma-names = "tx", "rx", "tx", "rx";
652 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
653 resets = <&cpg 203>;
654 status = "disabled";
655 };
656
657 scifa2: serial@e6c60000 {
658 compatible = "renesas,scifa-r8a7794",
659 "renesas,rcar-gen2-scifa", "renesas,scifa";
660 reg = <0 0xe6c60000 0 64>;
661 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&cpg CPG_MOD 202>;
663 clock-names = "fck";
664 dmas = <&dmac0 0x27>, <&dmac0 0x28>,
665 <&dmac1 0x27>, <&dmac1 0x28>;
666 dma-names = "tx", "rx", "tx", "rx";
667 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
668 resets = <&cpg 202>;
669 status = "disabled";
670 };
671
672 scifa3: serial@e6c70000 {
673 compatible = "renesas,scifa-r8a7794",
674 "renesas,rcar-gen2-scifa", "renesas,scifa";
675 reg = <0 0xe6c70000 0 64>;
676 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&cpg CPG_MOD 1106>;
678 clock-names = "fck";
679 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
680 <&dmac1 0x1b>, <&dmac1 0x1c>;
681 dma-names = "tx", "rx", "tx", "rx";
682 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
683 resets = <&cpg 1106>;
684 status = "disabled";
685 };
686
687 scifa4: serial@e6c78000 {
688 compatible = "renesas,scifa-r8a7794",
689 "renesas,rcar-gen2-scifa", "renesas,scifa";
690 reg = <0 0xe6c78000 0 64>;
691 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&cpg CPG_MOD 1107>;
693 clock-names = "fck";
694 dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
695 <&dmac1 0x1f>, <&dmac1 0x20>;
696 dma-names = "tx", "rx", "tx", "rx";
697 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
698 resets = <&cpg 1107>;
699 status = "disabled";
700 };
701
702 scifa5: serial@e6c80000 {
703 compatible = "renesas,scifa-r8a7794",
704 "renesas,rcar-gen2-scifa", "renesas,scifa";
705 reg = <0 0xe6c80000 0 64>;
706 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&cpg CPG_MOD 1108>;
708 clock-names = "fck";
709 dmas = <&dmac0 0x23>, <&dmac0 0x24>,
710 <&dmac1 0x23>, <&dmac1 0x24>;
711 dma-names = "tx", "rx", "tx", "rx";
712 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
713 resets = <&cpg 1108>;
714 status = "disabled";
715 };
716
717 scifb0: serial@e6c20000 {
718 compatible = "renesas,scifb-r8a7794",
719 "renesas,rcar-gen2-scifb", "renesas,scifb";
720 reg = <0 0xe6c20000 0 0x100>;
721 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&cpg CPG_MOD 206>;
723 clock-names = "fck";
724 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
725 <&dmac1 0x3d>, <&dmac1 0x3e>;
726 dma-names = "tx", "rx", "tx", "rx";
727 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
728 resets = <&cpg 206>;
729 status = "disabled";
730 };
731
732 scifb1: serial@e6c30000 {
733 compatible = "renesas,scifb-r8a7794",
734 "renesas,rcar-gen2-scifb", "renesas,scifb";
735 reg = <0 0xe6c30000 0 0x100>;
736 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 207>;
738 clock-names = "fck";
739 dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
740 <&dmac1 0x19>, <&dmac1 0x1a>;
741 dma-names = "tx", "rx", "tx", "rx";
742 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
743 resets = <&cpg 207>;
744 status = "disabled";
745 };
746
747 scifb2: serial@e6ce0000 {
748 compatible = "renesas,scifb-r8a7794",
749 "renesas,rcar-gen2-scifb", "renesas,scifb";
750 reg = <0 0xe6ce0000 0 0x100>;
751 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&cpg CPG_MOD 216>;
753 clock-names = "fck";
754 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
755 <&dmac1 0x1d>, <&dmac1 0x1e>;
756 dma-names = "tx", "rx", "tx", "rx";
757 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
758 resets = <&cpg 216>;
759 status = "disabled";
760 };
761
762 scif0: serial@e6e60000 {
763 compatible = "renesas,scif-r8a7794",
764 "renesas,rcar-gen2-scif",
765 "renesas,scif";
766 reg = <0 0xe6e60000 0 64>;
767 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
769 <&scif_clk>;
770 clock-names = "fck", "brg_int", "scif_clk";
771 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
772 <&dmac1 0x29>, <&dmac1 0x2a>;
773 dma-names = "tx", "rx", "tx", "rx";
774 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
775 resets = <&cpg 721>;
776 status = "disabled";
777 };
778
779 scif1: serial@e6e68000 {
780 compatible = "renesas,scif-r8a7794",
781 "renesas,rcar-gen2-scif",
782 "renesas,scif";
783 reg = <0 0xe6e68000 0 64>;
784 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
786 <&scif_clk>;
787 clock-names = "fck", "brg_int", "scif_clk";
788 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
789 <&dmac1 0x2d>, <&dmac1 0x2e>;
790 dma-names = "tx", "rx", "tx", "rx";
791 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
792 resets = <&cpg 720>;
793 status = "disabled";
794 };
795
796 scif2: serial@e6e58000 {
797 compatible = "renesas,scif-r8a7794",
798 "renesas,rcar-gen2-scif", "renesas,scif";
799 reg = <0 0xe6e58000 0 64>;
800 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
802 <&scif_clk>;
803 clock-names = "fck", "brg_int", "scif_clk";
804 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
805 <&dmac1 0x2b>, <&dmac1 0x2c>;
806 dma-names = "tx", "rx", "tx", "rx";
807 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
808 resets = <&cpg 719>;
809 status = "disabled";
810 };
811
812 scif3: serial@e6ea8000 {
813 compatible = "renesas,scif-r8a7794",
814 "renesas,rcar-gen2-scif", "renesas,scif";
815 reg = <0 0xe6ea8000 0 64>;
816 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
818 <&scif_clk>;
819 clock-names = "fck", "brg_int", "scif_clk";
820 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
821 <&dmac1 0x2f>, <&dmac1 0x30>;
822 dma-names = "tx", "rx", "tx", "rx";
823 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
824 resets = <&cpg 718>;
825 status = "disabled";
826 };
827
828 scif4: serial@e6ee0000 {
829 compatible = "renesas,scif-r8a7794",
830 "renesas,rcar-gen2-scif", "renesas,scif";
831 reg = <0 0xe6ee0000 0 64>;
832 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
834 <&scif_clk>;
835 clock-names = "fck", "brg_int", "scif_clk";
836 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
837 <&dmac1 0xfb>, <&dmac1 0xfc>;
838 dma-names = "tx", "rx", "tx", "rx";
839 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
840 resets = <&cpg 715>;
841 status = "disabled";
842 };
843
844 scif5: serial@e6ee8000 {
845 compatible = "renesas,scif-r8a7794",
846 "renesas,rcar-gen2-scif", "renesas,scif";
847 reg = <0 0xe6ee8000 0 64>;
848 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
850 <&scif_clk>;
851 clock-names = "fck", "brg_int", "scif_clk";
852 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
853 <&dmac1 0xfd>, <&dmac1 0xfe>;
854 dma-names = "tx", "rx", "tx", "rx";
855 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
856 resets = <&cpg 714>;
857 status = "disabled";
858 };
859
860 hscif0: serial@e62c0000 {
861 compatible = "renesas,hscif-r8a7794",
862 "renesas,rcar-gen2-hscif", "renesas,hscif";
863 reg = <0 0xe62c0000 0 96>;
864 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&cpg CPG_MOD 717>,
866 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
867 clock-names = "fck", "brg_int", "scif_clk";
868 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
869 <&dmac1 0x39>, <&dmac1 0x3a>;
870 dma-names = "tx", "rx", "tx", "rx";
871 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
872 resets = <&cpg 717>;
873 status = "disabled";
874 };
875
876 hscif1: serial@e62c8000 {
877 compatible = "renesas,hscif-r8a7794",
878 "renesas,rcar-gen2-hscif", "renesas,hscif";
879 reg = <0 0xe62c8000 0 96>;
880 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&cpg CPG_MOD 716>,
882 <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>;
883 clock-names = "fck", "brg_int", "scif_clk";
884 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
885 <&dmac1 0x4d>, <&dmac1 0x4e>;
886 dma-names = "tx", "rx", "tx", "rx";
887 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
888 resets = <&cpg 716>;
889 status = "disabled";
890 };
891
892 hscif2: serial@e62d0000 {
893 compatible = "renesas,hscif-r8a7794",
894 "renesas,rcar-gen2-hscif", "renesas,hscif";
895 reg = <0 0xe62d0000 0 96>;
896 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>,
898 <&scif_clk>;
899 clock-names = "fck", "brg_int", "scif_clk";
900 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
901 <&dmac1 0x3b>, <&dmac1 0x3c>;
902 dma-names = "tx", "rx", "tx", "rx";
903 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
904 resets = <&cpg 713>;
905 status = "disabled";
906 };
907
908 can0: can@e6e80000 {
909 compatible = "renesas,can-r8a7794",
910 "renesas,rcar-gen2-can";
911 reg = <0 0xe6e80000 0 0x1000>;
912 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
914 <&can_clk>;
915 clock-names = "clkp1", "clkp2", "can_clk";
916 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
917 resets = <&cpg 916>;
918 status = "disabled";
919 };
920
921 can1: can@e6e88000 {
922 compatible = "renesas,can-r8a7794",
923 "renesas,rcar-gen2-can";
924 reg = <0 0xe6e88000 0 0x1000>;
925 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>,
927 <&can_clk>;
928 clock-names = "clkp1", "clkp2", "can_clk";
929 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
930 resets = <&cpg 915>;
931 status = "disabled";
932 };
933
934 vin0: video@e6ef0000 {
935 compatible = "renesas,vin-r8a7794",
936 "renesas,rcar-gen2-vin";
937 reg = <0 0xe6ef0000 0 0x1000>;
938 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&cpg CPG_MOD 811>;
940 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
941 resets = <&cpg 811>;
942 status = "disabled";
943 };
944
945 vin1: video@e6ef1000 {
946 compatible = "renesas,vin-r8a7794",
947 "renesas,rcar-gen2-vin";
948 reg = <0 0xe6ef1000 0 0x1000>;
949 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&cpg CPG_MOD 810>;
951 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
952 resets = <&cpg 810>;
953 status = "disabled";
954 };
955
956 rcar_sound: sound@ec500000 {
957 /*
958 * #sound-dai-cells is required
959 *
960 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
961 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
962 */
963 compatible = "renesas,rcar_sound-r8a7794",
964 "renesas,rcar_sound-gen2";
965 reg = <0 0xec500000 0 0x1000>, /* SCU */
966 <0 0xec5a0000 0 0x100>, /* ADG */
967 <0 0xec540000 0 0x1000>, /* SSIU */
968 <0 0xec541000 0 0x280>, /* SSI */
969 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
970 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
971
972 clocks = <&cpg CPG_MOD 1005>,
973 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
974 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
975 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
976 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
977 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
978 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
979 <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
980 <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
981 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
982 <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
983 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
984 <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
985 <&cpg CPG_CORE R8A7794_CLK_M2>;
986 clock-names = "ssi-all",
987 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
988 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
989 "ssi.1", "ssi.0",
990 "src.6", "src.5", "src.4", "src.3",
991 "src.2", "src.1",
992 "ctu.0", "ctu.1",
993 "mix.0", "mix.1",
994 "dvc.0", "dvc.1",
995 "clk_a", "clk_b", "clk_c", "clk_i";
996 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
997 resets = <&cpg 1005>,
998 <&cpg 1006>, <&cpg 1007>,
999 <&cpg 1008>, <&cpg 1009>,
1000 <&cpg 1010>, <&cpg 1011>,
1001 <&cpg 1012>, <&cpg 1013>,
1002 <&cpg 1014>, <&cpg 1015>;
1003 reset-names = "ssi-all",
1004 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1005 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1006 "ssi.1", "ssi.0";
1007
1008 status = "disabled";
1009
1010 rcar_sound,dvc {
1011 dvc0: dvc-0 {
1012 dmas = <&audma0 0xbc>;
1013 dma-names = "tx";
1014 };
1015 dvc1: dvc-1 {
1016 dmas = <&audma0 0xbe>;
1017 dma-names = "tx";
1018 };
1019 };
1020
1021 rcar_sound,mix {
1022 mix0: mix-0 { };
1023 mix1: mix-1 { };
1024 };
1025
1026 rcar_sound,ctu {
1027 ctu00: ctu-0 { };
1028 ctu01: ctu-1 { };
1029 ctu02: ctu-2 { };
1030 ctu03: ctu-3 { };
1031 ctu10: ctu-4 { };
1032 ctu11: ctu-5 { };
1033 ctu12: ctu-6 { };
1034 ctu13: ctu-7 { };
1035 };
1036
1037 rcar_sound,src {
1038 src-0 {
1039 status = "disabled";
1040 };
1041 src1: src-1 {
1042 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1043 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1044 dma-names = "rx", "tx";
1045 };
1046 src2: src-2 {
1047 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1048 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1049 dma-names = "rx", "tx";
1050 };
1051 src3: src-3 {
1052 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1053 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1054 dma-names = "rx", "tx";
1055 };
1056 src4: src-4 {
1057 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1058 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1059 dma-names = "rx", "tx";
1060 };
1061 src5: src-5 {
1062 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1063 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1064 dma-names = "rx", "tx";
1065 };
1066 src6: src-6 {
1067 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1068 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1069 dma-names = "rx", "tx";
1070 };
1071 };
1072
1073 rcar_sound,ssi {
1074 ssi0: ssi-0 {
1075 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1076 dmas = <&audma0 0x01>, <&audma0 0x02>,
1077 <&audma0 0x15>, <&audma0 0x16>;
1078 dma-names = "rx", "tx", "rxu", "txu";
1079 };
1080 ssi1: ssi-1 {
1081 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1082 dmas = <&audma0 0x03>, <&audma0 0x04>,
1083 <&audma0 0x49>, <&audma0 0x4a>;
1084 dma-names = "rx", "tx", "rxu", "txu";
1085 };
1086 ssi2: ssi-2 {
1087 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1088 dmas = <&audma0 0x05>, <&audma0 0x06>,
1089 <&audma0 0x63>, <&audma0 0x64>;
1090 dma-names = "rx", "tx", "rxu", "txu";
1091 };
1092 ssi3: ssi-3 {
1093 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1094 dmas = <&audma0 0x07>, <&audma0 0x08>,
1095 <&audma0 0x6f>, <&audma0 0x70>;
1096 dma-names = "rx", "tx", "rxu", "txu";
1097 };
1098 ssi4: ssi-4 {
1099 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1100 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1101 <&audma0 0x71>, <&audma0 0x72>;
1102 dma-names = "rx", "tx", "rxu", "txu";
1103 };
1104 ssi5: ssi-5 {
1105 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1106 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1107 <&audma0 0x73>, <&audma0 0x74>;
1108 dma-names = "rx", "tx", "rxu", "txu";
1109 };
1110 ssi6: ssi-6 {
1111 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1112 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1113 <&audma0 0x75>, <&audma0 0x76>;
1114 dma-names = "rx", "tx", "rxu", "txu";
1115 };
1116 ssi7: ssi-7 {
1117 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1118 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1119 <&audma0 0x79>, <&audma0 0x7a>;
1120 dma-names = "rx", "tx", "rxu", "txu";
1121 };
1122 ssi8: ssi-8 {
1123 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1124 dmas = <&audma0 0x11>, <&audma0 0x12>,
1125 <&audma0 0x7b>, <&audma0 0x7c>;
1126 dma-names = "rx", "tx", "rxu", "txu";
1127 };
1128 ssi9: ssi-9 {
1129 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1130 dmas = <&audma0 0x13>, <&audma0 0x14>,
1131 <&audma0 0x7d>, <&audma0 0x7e>;
1132 dma-names = "rx", "tx", "rxu", "txu";
1133 };
1134 };
1135 };
1136
1137 audma0: dma-controller@ec700000 {
1138 compatible = "renesas,dmac-r8a7794",
1139 "renesas,rcar-dmac";
1140 reg = <0 0xec700000 0 0x10000>;
1141 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
1142 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1143 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1150 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1151 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1152 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1155 interrupt-names = "error",
1156 "ch0", "ch1", "ch2", "ch3", "ch4",
1157 "ch5", "ch6", "ch7", "ch8", "ch9",
1158 "ch10", "ch11",
1159 "ch12";
1160 clocks = <&cpg CPG_MOD 502>;
1161 clock-names = "fck";
1162 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1163 resets = <&cpg 502>;
1164 #dma-cells = <1>;
1165 dma-channels = <13>;
1166 };
1167
1168 pci0: pci@ee090000 {
1169 compatible = "renesas,pci-r8a7794",
1170 "renesas,pci-rcar-gen2";
1171 device_type = "pci";
1172 reg = <0 0xee090000 0 0xc00>,
1173 <0 0xee080000 0 0x1100>;
1174 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1175 clocks = <&cpg CPG_MOD 703>;
1176 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1177 resets = <&cpg 703>;
1178 status = "disabled";
1179
1180 bus-range = <0 0>;
1181 #address-cells = <3>;
1182 #size-cells = <2>;
1183 #interrupt-cells = <1>;
1184 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1185 interrupt-map-mask = <0xf800 0 0 0x7>;
1186 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1187 <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1188 <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1189
1190 usb@1,0 {
1191 reg = <0x800 0 0 0 0>;
1192 phys = <&usb0 0>;
1193 phy-names = "usb";
1194 };
1195
1196 usb@2,0 {
1197 reg = <0x1000 0 0 0 0>;
1198 phys = <&usb0 0>;
1199 phy-names = "usb";
1200 };
1201 };
1202
1203 pci1: pci@ee0d0000 {
1204 compatible = "renesas,pci-r8a7794",
1205 "renesas,pci-rcar-gen2";
1206 device_type = "pci";
1207 reg = <0 0xee0d0000 0 0xc00>,
1208 <0 0xee0c0000 0 0x1100>;
1209 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MOD 703>;
1211 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1212 resets = <&cpg 703>;
1213 status = "disabled";
1214
1215 bus-range = <1 1>;
1216 #address-cells = <3>;
1217 #size-cells = <2>;
1218 #interrupt-cells = <1>;
1219 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1220 interrupt-map-mask = <0xf800 0 0 0x7>;
1221 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1222 <0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1223 <0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1224
1225 usb@1,0 {
1226 reg = <0x10800 0 0 0 0>;
1227 phys = <&usb2 0>;
1228 phy-names = "usb";
1229 };
1230
1231 usb@2,0 {
1232 reg = <0x11000 0 0 0 0>;
1233 phys = <&usb2 0>;
1234 phy-names = "usb";
1235 };
1236 };
1237
1238 sdhi0: mmc@ee100000 {
1239 compatible = "renesas,sdhi-r8a7794",
1240 "renesas,rcar-gen2-sdhi";
1241 reg = <0 0xee100000 0 0x328>;
1242 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1243 clocks = <&cpg CPG_MOD 314>;
1244 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
1245 <&dmac1 0xcd>, <&dmac1 0xce>;
1246 dma-names = "tx", "rx", "tx", "rx";
1247 max-frequency = <195000000>;
1248 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1249 resets = <&cpg 314>;
1250 status = "disabled";
1251 };
1252
1253 sdhi1: mmc@ee140000 {
1254 compatible = "renesas,sdhi-r8a7794",
1255 "renesas,rcar-gen2-sdhi";
1256 reg = <0 0xee140000 0 0x100>;
1257 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&cpg CPG_MOD 312>;
1259 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
1260 <&dmac1 0xc1>, <&dmac1 0xc2>;
1261 dma-names = "tx", "rx", "tx", "rx";
1262 max-frequency = <97500000>;
1263 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1264 resets = <&cpg 312>;
1265 status = "disabled";
1266 };
1267
1268 sdhi2: mmc@ee160000 {
1269 compatible = "renesas,sdhi-r8a7794",
1270 "renesas,rcar-gen2-sdhi";
1271 reg = <0 0xee160000 0 0x100>;
1272 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&cpg CPG_MOD 311>;
1274 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
1275 <&dmac1 0xd3>, <&dmac1 0xd4>;
1276 dma-names = "tx", "rx", "tx", "rx";
1277 max-frequency = <97500000>;
1278 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1279 resets = <&cpg 311>;
1280 status = "disabled";
1281 };
1282
1283 mmcif0: mmc@ee200000 {
1284 compatible = "renesas,mmcif-r8a7794",
1285 "renesas,sh-mmcif";
1286 reg = <0 0xee200000 0 0x80>;
1287 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&cpg CPG_MOD 315>;
1289 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
1290 <&dmac1 0xd1>, <&dmac1 0xd2>;
1291 dma-names = "tx", "rx", "tx", "rx";
1292 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1293 resets = <&cpg 315>;
1294 reg-io-width = <4>;
1295 status = "disabled";
1296 };
1297
1298 ether: ethernet@ee700000 {
1299 compatible = "renesas,ether-r8a7794",
1300 "renesas,rcar-gen2-ether";
1301 reg = <0 0xee700000 0 0x400>;
1302 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1303 clocks = <&cpg CPG_MOD 813>;
1304 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1305 resets = <&cpg 813>;
1306 phy-mode = "rmii";
1307 #address-cells = <1>;
1308 #size-cells = <0>;
1309 status = "disabled";
1310 };
1311
1312 gic: interrupt-controller@f1001000 {
1313 compatible = "arm,gic-400";
1314 #interrupt-cells = <3>;
1315 #address-cells = <0>;
1316 interrupt-controller;
1317 reg = <0 0xf1001000 0 0x1000>,
1318 <0 0xf1002000 0 0x2000>,
1319 <0 0xf1004000 0 0x2000>,
1320 <0 0xf1006000 0 0x2000>;
1321 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1322 clocks = <&cpg CPG_MOD 408>;
1323 clock-names = "clk";
1324 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1325 resets = <&cpg 408>;
1326 };
1327
1328 vsp@fe928000 {
1329 compatible = "renesas,vsp1";
1330 reg = <0 0xfe928000 0 0x8000>;
1331 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
1332 clocks = <&cpg CPG_MOD 131>;
1333 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1334 resets = <&cpg 131>;
1335 };
1336
1337 vsp@fe930000 {
1338 compatible = "renesas,vsp1";
1339 reg = <0 0xfe930000 0 0x8000>;
1340 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1341 clocks = <&cpg CPG_MOD 128>;
1342 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1343 resets = <&cpg 128>;
1344 };
1345
1346 fdp1@fe940000 {
1347 compatible = "renesas,fdp1";
1348 reg = <0 0xfe940000 0 0x2400>;
1349 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
1350 clocks = <&cpg CPG_MOD 119>;
1351 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1352 resets = <&cpg 119>;
1353 };
1354
1355 du: display@feb00000 {
1356 compatible = "renesas,du-r8a7794";
1357 reg = <0 0xfeb00000 0 0x40000>;
1358 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1360 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
1361 clock-names = "du.0", "du.1";
1362 resets = <&cpg 724>;
1363 reset-names = "du.0";
1364 status = "disabled";
1365
1366 ports {
1367 #address-cells = <1>;
1368 #size-cells = <0>;
1369
1370 port@0 {
1371 reg = <0>;
1372 du_out_rgb0: endpoint {
1373 };
1374 };
1375 port@1 {
1376 reg = <1>;
1377 du_out_rgb1: endpoint {
1378 };
1379 };
1380 };
1381 };
1382
1383 prr: chipid@ff000044 {
1384 compatible = "renesas,prr";
1385 reg = <0 0xff000044 0 4>;
1386 };
1387
1388 cmt0: timer@ffca0000 {
1389 compatible = "renesas,r8a7794-cmt0",
1390 "renesas,rcar-gen2-cmt0";
1391 reg = <0 0xffca0000 0 0x1004>;
1392 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1394 clocks = <&cpg CPG_MOD 124>;
1395 clock-names = "fck";
1396 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1397 resets = <&cpg 124>;
1398
1399 status = "disabled";
1400 };
1401
1402 cmt1: timer@e6130000 {
1403 compatible = "renesas,r8a7794-cmt1",
1404 "renesas,rcar-gen2-cmt1";
1405 reg = <0 0xe6130000 0 0x1004>;
1406 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1410 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1414 clocks = <&cpg CPG_MOD 329>;
1415 clock-names = "fck";
1416 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
1417 resets = <&cpg 329>;
1418
1419 status = "disabled";
1420 };
1421 };
1422
1423 timer {
1424 compatible = "arm,armv7-timer";
1425 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1426 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1427 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1428 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1429 };
1430
1431 /* External USB clock - can be overridden by the board */
1432 usb_extal_clk: usb_extal {
1433 compatible = "fixed-clock";
1434 #clock-cells = <0>;
1435 clock-frequency = <48000000>;
1436 };
1437};
1/*
2 * Device Tree Source for the r8a7794 SoC
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2014 Ulrich Hecht
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r8a7794-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
16/ {
17 compatible = "renesas,r8a7794";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 i2c5 = &i2c5;
29 spi0 = &qspi;
30 vin0 = &vin0;
31 vin1 = &vin1;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu0: cpu@0 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a7";
41 reg = <0>;
42 clock-frequency = <1000000000>;
43 next-level-cache = <&L2_CA7>;
44 };
45
46 cpu1: cpu@1 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a7";
49 reg = <1>;
50 clock-frequency = <1000000000>;
51 next-level-cache = <&L2_CA7>;
52 };
53 };
54
55 L2_CA7: cache-controller@1 {
56 compatible = "cache";
57 cache-unified;
58 cache-level = <2>;
59 };
60
61 gic: interrupt-controller@f1001000 {
62 compatible = "arm,gic-400";
63 #interrupt-cells = <3>;
64 #address-cells = <0>;
65 interrupt-controller;
66 reg = <0 0xf1001000 0 0x1000>,
67 <0 0xf1002000 0 0x1000>,
68 <0 0xf1004000 0 0x2000>,
69 <0 0xf1006000 0 0x2000>;
70 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
71 };
72
73 gpio0: gpio@e6050000 {
74 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
75 reg = <0 0xe6050000 0 0x50>;
76 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
77 #gpio-cells = <2>;
78 gpio-controller;
79 gpio-ranges = <&pfc 0 0 32>;
80 #interrupt-cells = <2>;
81 interrupt-controller;
82 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
83 power-domains = <&cpg_clocks>;
84 };
85
86 gpio1: gpio@e6051000 {
87 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
88 reg = <0 0xe6051000 0 0x50>;
89 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
90 #gpio-cells = <2>;
91 gpio-controller;
92 gpio-ranges = <&pfc 0 32 26>;
93 #interrupt-cells = <2>;
94 interrupt-controller;
95 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
96 power-domains = <&cpg_clocks>;
97 };
98
99 gpio2: gpio@e6052000 {
100 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
101 reg = <0 0xe6052000 0 0x50>;
102 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
103 #gpio-cells = <2>;
104 gpio-controller;
105 gpio-ranges = <&pfc 0 64 32>;
106 #interrupt-cells = <2>;
107 interrupt-controller;
108 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
109 power-domains = <&cpg_clocks>;
110 };
111
112 gpio3: gpio@e6053000 {
113 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
114 reg = <0 0xe6053000 0 0x50>;
115 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
116 #gpio-cells = <2>;
117 gpio-controller;
118 gpio-ranges = <&pfc 0 96 32>;
119 #interrupt-cells = <2>;
120 interrupt-controller;
121 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
122 power-domains = <&cpg_clocks>;
123 };
124
125 gpio4: gpio@e6054000 {
126 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
127 reg = <0 0xe6054000 0 0x50>;
128 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
129 #gpio-cells = <2>;
130 gpio-controller;
131 gpio-ranges = <&pfc 0 128 32>;
132 #interrupt-cells = <2>;
133 interrupt-controller;
134 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
135 power-domains = <&cpg_clocks>;
136 };
137
138 gpio5: gpio@e6055000 {
139 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
140 reg = <0 0xe6055000 0 0x50>;
141 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
142 #gpio-cells = <2>;
143 gpio-controller;
144 gpio-ranges = <&pfc 0 160 28>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
147 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
148 power-domains = <&cpg_clocks>;
149 };
150
151 gpio6: gpio@e6055400 {
152 compatible = "renesas,gpio-r8a7794", "renesas,gpio-rcar";
153 reg = <0 0xe6055400 0 0x50>;
154 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
155 #gpio-cells = <2>;
156 gpio-controller;
157 gpio-ranges = <&pfc 0 192 26>;
158 #interrupt-cells = <2>;
159 interrupt-controller;
160 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
161 power-domains = <&cpg_clocks>;
162 };
163
164 cmt0: timer@ffca0000 {
165 compatible = "renesas,cmt-48-gen2";
166 reg = <0 0xffca0000 0 0x1004>;
167 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
170 clock-names = "fck";
171 power-domains = <&cpg_clocks>;
172
173 renesas,channels-mask = <0x60>;
174
175 status = "disabled";
176 };
177
178 cmt1: timer@e6130000 {
179 compatible = "renesas,cmt-48-gen2";
180 reg = <0 0xe6130000 0 0x1004>;
181 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
190 clock-names = "fck";
191 power-domains = <&cpg_clocks>;
192
193 renesas,channels-mask = <0xff>;
194
195 status = "disabled";
196 };
197
198 timer {
199 compatible = "arm,armv7-timer";
200 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
201 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
202 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
203 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
204 };
205
206 irqc0: interrupt-controller@e61c0000 {
207 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
208 #interrupt-cells = <2>;
209 interrupt-controller;
210 reg = <0 0xe61c0000 0 0x200>;
211 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
222 power-domains = <&cpg_clocks>;
223 };
224
225 pfc: pin-controller@e6060000 {
226 compatible = "renesas,pfc-r8a7794";
227 reg = <0 0xe6060000 0 0x11c>;
228 };
229
230 dmac0: dma-controller@e6700000 {
231 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
232 reg = <0 0xe6700000 0 0x20000>;
233 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
234 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
235 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
236 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
237 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
238 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
239 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
240 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
241 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
242 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
243 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
245 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
246 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
247 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
248 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
249 interrupt-names = "error",
250 "ch0", "ch1", "ch2", "ch3",
251 "ch4", "ch5", "ch6", "ch7",
252 "ch8", "ch9", "ch10", "ch11",
253 "ch12", "ch13", "ch14";
254 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
255 clock-names = "fck";
256 power-domains = <&cpg_clocks>;
257 #dma-cells = <1>;
258 dma-channels = <15>;
259 };
260
261 dmac1: dma-controller@e6720000 {
262 compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac";
263 reg = <0 0xe6720000 0 0x20000>;
264 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
265 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
266 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
267 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
268 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
269 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
270 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
271 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
272 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
273 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
274 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
275 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
276 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
277 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
278 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
279 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-names = "error",
281 "ch0", "ch1", "ch2", "ch3",
282 "ch4", "ch5", "ch6", "ch7",
283 "ch8", "ch9", "ch10", "ch11",
284 "ch12", "ch13", "ch14";
285 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
286 clock-names = "fck";
287 power-domains = <&cpg_clocks>;
288 #dma-cells = <1>;
289 dma-channels = <15>;
290 };
291
292 scifa0: serial@e6c40000 {
293 compatible = "renesas,scifa-r8a7794",
294 "renesas,rcar-gen2-scifa", "renesas,scifa";
295 reg = <0 0xe6c40000 0 64>;
296 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
298 clock-names = "fck";
299 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
300 dma-names = "tx", "rx";
301 power-domains = <&cpg_clocks>;
302 status = "disabled";
303 };
304
305 scifa1: serial@e6c50000 {
306 compatible = "renesas,scifa-r8a7794",
307 "renesas,rcar-gen2-scifa", "renesas,scifa";
308 reg = <0 0xe6c50000 0 64>;
309 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
311 clock-names = "fck";
312 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
313 dma-names = "tx", "rx";
314 power-domains = <&cpg_clocks>;
315 status = "disabled";
316 };
317
318 scifa2: serial@e6c60000 {
319 compatible = "renesas,scifa-r8a7794",
320 "renesas,rcar-gen2-scifa", "renesas,scifa";
321 reg = <0 0xe6c60000 0 64>;
322 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
324 clock-names = "fck";
325 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
326 dma-names = "tx", "rx";
327 power-domains = <&cpg_clocks>;
328 status = "disabled";
329 };
330
331 scifa3: serial@e6c70000 {
332 compatible = "renesas,scifa-r8a7794",
333 "renesas,rcar-gen2-scifa", "renesas,scifa";
334 reg = <0 0xe6c70000 0 64>;
335 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
337 clock-names = "fck";
338 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
339 dma-names = "tx", "rx";
340 power-domains = <&cpg_clocks>;
341 status = "disabled";
342 };
343
344 scifa4: serial@e6c78000 {
345 compatible = "renesas,scifa-r8a7794",
346 "renesas,rcar-gen2-scifa", "renesas,scifa";
347 reg = <0 0xe6c78000 0 64>;
348 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
350 clock-names = "fck";
351 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
352 dma-names = "tx", "rx";
353 power-domains = <&cpg_clocks>;
354 status = "disabled";
355 };
356
357 scifa5: serial@e6c80000 {
358 compatible = "renesas,scifa-r8a7794",
359 "renesas,rcar-gen2-scifa", "renesas,scifa";
360 reg = <0 0xe6c80000 0 64>;
361 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
363 clock-names = "fck";
364 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
365 dma-names = "tx", "rx";
366 power-domains = <&cpg_clocks>;
367 status = "disabled";
368 };
369
370 scifb0: serial@e6c20000 {
371 compatible = "renesas,scifb-r8a7794",
372 "renesas,rcar-gen2-scifb", "renesas,scifb";
373 reg = <0 0xe6c20000 0 64>;
374 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
376 clock-names = "fck";
377 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
378 dma-names = "tx", "rx";
379 power-domains = <&cpg_clocks>;
380 status = "disabled";
381 };
382
383 scifb1: serial@e6c30000 {
384 compatible = "renesas,scifb-r8a7794",
385 "renesas,rcar-gen2-scifb", "renesas,scifb";
386 reg = <0 0xe6c30000 0 64>;
387 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
389 clock-names = "fck";
390 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
391 dma-names = "tx", "rx";
392 power-domains = <&cpg_clocks>;
393 status = "disabled";
394 };
395
396 scifb2: serial@e6ce0000 {
397 compatible = "renesas,scifb-r8a7794",
398 "renesas,rcar-gen2-scifb", "renesas,scifb";
399 reg = <0 0xe6ce0000 0 64>;
400 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
402 clock-names = "fck";
403 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
404 dma-names = "tx", "rx";
405 power-domains = <&cpg_clocks>;
406 status = "disabled";
407 };
408
409 scif0: serial@e6e60000 {
410 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
411 "renesas,scif";
412 reg = <0 0xe6e60000 0 64>;
413 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
415 <&scif_clk>;
416 clock-names = "fck", "brg_int", "scif_clk";
417 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
418 dma-names = "tx", "rx";
419 power-domains = <&cpg_clocks>;
420 status = "disabled";
421 };
422
423 scif1: serial@e6e68000 {
424 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
425 "renesas,scif";
426 reg = <0 0xe6e68000 0 64>;
427 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
429 <&scif_clk>;
430 clock-names = "fck", "brg_int", "scif_clk";
431 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
432 dma-names = "tx", "rx";
433 power-domains = <&cpg_clocks>;
434 status = "disabled";
435 };
436
437 scif2: serial@e6e58000 {
438 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
439 "renesas,scif";
440 reg = <0 0xe6e58000 0 64>;
441 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
443 <&scif_clk>;
444 clock-names = "fck", "brg_int", "scif_clk";
445 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
446 dma-names = "tx", "rx";
447 power-domains = <&cpg_clocks>;
448 status = "disabled";
449 };
450
451 scif3: serial@e6ea8000 {
452 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
453 "renesas,scif";
454 reg = <0 0xe6ea8000 0 64>;
455 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
457 <&scif_clk>;
458 clock-names = "fck", "brg_int", "scif_clk";
459 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
460 dma-names = "tx", "rx";
461 power-domains = <&cpg_clocks>;
462 status = "disabled";
463 };
464
465 scif4: serial@e6ee0000 {
466 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
467 "renesas,scif";
468 reg = <0 0xe6ee0000 0 64>;
469 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
471 <&scif_clk>;
472 clock-names = "fck", "brg_int", "scif_clk";
473 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
474 dma-names = "tx", "rx";
475 power-domains = <&cpg_clocks>;
476 status = "disabled";
477 };
478
479 scif5: serial@e6ee8000 {
480 compatible = "renesas,scif-r8a7794", "renesas,rcar-gen2-scif",
481 "renesas,scif";
482 reg = <0 0xe6ee8000 0 64>;
483 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
485 <&scif_clk>;
486 clock-names = "fck", "brg_int", "scif_clk";
487 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
488 dma-names = "tx", "rx";
489 power-domains = <&cpg_clocks>;
490 status = "disabled";
491 };
492
493 hscif0: serial@e62c0000 {
494 compatible = "renesas,hscif-r8a7794",
495 "renesas,rcar-gen2-hscif", "renesas,hscif";
496 reg = <0 0xe62c0000 0 96>;
497 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
499 <&scif_clk>;
500 clock-names = "fck", "brg_int", "scif_clk";
501 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
502 dma-names = "tx", "rx";
503 power-domains = <&cpg_clocks>;
504 status = "disabled";
505 };
506
507 hscif1: serial@e62c8000 {
508 compatible = "renesas,hscif-r8a7794",
509 "renesas,rcar-gen2-hscif", "renesas,hscif";
510 reg = <0 0xe62c8000 0 96>;
511 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
513 <&scif_clk>;
514 clock-names = "fck", "brg_int", "scif_clk";
515 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
516 dma-names = "tx", "rx";
517 power-domains = <&cpg_clocks>;
518 status = "disabled";
519 };
520
521 hscif2: serial@e62d0000 {
522 compatible = "renesas,hscif-r8a7794",
523 "renesas,rcar-gen2-hscif", "renesas,hscif";
524 reg = <0 0xe62d0000 0 96>;
525 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
527 <&scif_clk>;
528 clock-names = "fck", "brg_int", "scif_clk";
529 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
530 dma-names = "tx", "rx";
531 power-domains = <&cpg_clocks>;
532 status = "disabled";
533 };
534
535 ether: ethernet@ee700000 {
536 compatible = "renesas,ether-r8a7794";
537 reg = <0 0xee700000 0 0x400>;
538 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
540 power-domains = <&cpg_clocks>;
541 phy-mode = "rmii";
542 #address-cells = <1>;
543 #size-cells = <0>;
544 status = "disabled";
545 };
546
547 avb: ethernet@e6800000 {
548 compatible = "renesas,etheravb-r8a7794",
549 "renesas,etheravb-rcar-gen2";
550 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
551 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
553 power-domains = <&cpg_clocks>;
554 #address-cells = <1>;
555 #size-cells = <0>;
556 status = "disabled";
557 };
558
559 /* The memory map in the User's Manual maps the cores to bus numbers */
560 i2c0: i2c@e6508000 {
561 compatible = "renesas,i2c-r8a7794";
562 reg = <0 0xe6508000 0 0x40>;
563 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
565 power-domains = <&cpg_clocks>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 i2c-scl-internal-delay-ns = <6>;
569 status = "disabled";
570 };
571
572 i2c1: i2c@e6518000 {
573 compatible = "renesas,i2c-r8a7794";
574 reg = <0 0xe6518000 0 0x40>;
575 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
577 power-domains = <&cpg_clocks>;
578 #address-cells = <1>;
579 #size-cells = <0>;
580 i2c-scl-internal-delay-ns = <6>;
581 status = "disabled";
582 };
583
584 i2c2: i2c@e6530000 {
585 compatible = "renesas,i2c-r8a7794";
586 reg = <0 0xe6530000 0 0x40>;
587 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
589 power-domains = <&cpg_clocks>;
590 #address-cells = <1>;
591 #size-cells = <0>;
592 i2c-scl-internal-delay-ns = <6>;
593 status = "disabled";
594 };
595
596 i2c3: i2c@e6540000 {
597 compatible = "renesas,i2c-r8a7794";
598 reg = <0 0xe6540000 0 0x40>;
599 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
601 power-domains = <&cpg_clocks>;
602 #address-cells = <1>;
603 #size-cells = <0>;
604 i2c-scl-internal-delay-ns = <6>;
605 status = "disabled";
606 };
607
608 i2c4: i2c@e6520000 {
609 compatible = "renesas,i2c-r8a7794";
610 reg = <0 0xe6520000 0 0x40>;
611 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
613 power-domains = <&cpg_clocks>;
614 #address-cells = <1>;
615 #size-cells = <0>;
616 i2c-scl-internal-delay-ns = <6>;
617 status = "disabled";
618 };
619
620 i2c5: i2c@e6528000 {
621 compatible = "renesas,i2c-r8a7794";
622 reg = <0 0xe6528000 0 0x40>;
623 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
625 power-domains = <&cpg_clocks>;
626 #address-cells = <1>;
627 #size-cells = <0>;
628 i2c-scl-internal-delay-ns = <6>;
629 status = "disabled";
630 };
631
632 mmcif0: mmc@ee200000 {
633 compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
634 reg = <0 0xee200000 0 0x80>;
635 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
637 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
638 dma-names = "tx", "rx";
639 power-domains = <&cpg_clocks>;
640 reg-io-width = <4>;
641 status = "disabled";
642 };
643
644 sdhi0: sd@ee100000 {
645 compatible = "renesas,sdhi-r8a7794";
646 reg = <0 0xee100000 0 0x200>;
647 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
649 power-domains = <&cpg_clocks>;
650 status = "disabled";
651 };
652
653 sdhi1: sd@ee140000 {
654 compatible = "renesas,sdhi-r8a7794";
655 reg = <0 0xee140000 0 0x100>;
656 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
658 power-domains = <&cpg_clocks>;
659 status = "disabled";
660 };
661
662 sdhi2: sd@ee160000 {
663 compatible = "renesas,sdhi-r8a7794";
664 reg = <0 0xee160000 0 0x100>;
665 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
667 power-domains = <&cpg_clocks>;
668 status = "disabled";
669 };
670
671 qspi: spi@e6b10000 {
672 compatible = "renesas,qspi-r8a7794", "renesas,qspi";
673 reg = <0 0xe6b10000 0 0x2c>;
674 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
676 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
677 dma-names = "tx", "rx";
678 power-domains = <&cpg_clocks>;
679 num-cs = <1>;
680 #address-cells = <1>;
681 #size-cells = <0>;
682 status = "disabled";
683 };
684
685 vin0: video@e6ef0000 {
686 compatible = "renesas,vin-r8a7794";
687 reg = <0 0xe6ef0000 0 0x1000>;
688 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
690 power-domains = <&cpg_clocks>;
691 status = "disabled";
692 };
693
694 vin1: video@e6ef1000 {
695 compatible = "renesas,vin-r8a7794";
696 reg = <0 0xe6ef1000 0 0x1000>;
697 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
699 power-domains = <&cpg_clocks>;
700 status = "disabled";
701 };
702
703 pci0: pci@ee090000 {
704 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
705 device_type = "pci";
706 reg = <0 0xee090000 0 0xc00>,
707 <0 0xee080000 0 0x1100>;
708 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
710 power-domains = <&cpg_clocks>;
711 status = "disabled";
712
713 bus-range = <0 0>;
714 #address-cells = <3>;
715 #size-cells = <2>;
716 #interrupt-cells = <1>;
717 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
718 interrupt-map-mask = <0xff00 0 0 0x7>;
719 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
720 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
721 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
722
723 usb@0,1 {
724 reg = <0x800 0 0 0 0>;
725 device_type = "pci";
726 phys = <&usb0 0>;
727 phy-names = "usb";
728 };
729
730 usb@0,2 {
731 reg = <0x1000 0 0 0 0>;
732 device_type = "pci";
733 phys = <&usb0 0>;
734 phy-names = "usb";
735 };
736 };
737
738 pci1: pci@ee0d0000 {
739 compatible = "renesas,pci-r8a7794", "renesas,pci-rcar-gen2";
740 device_type = "pci";
741 reg = <0 0xee0d0000 0 0xc00>,
742 <0 0xee0c0000 0 0x1100>;
743 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
745 power-domains = <&cpg_clocks>;
746 status = "disabled";
747
748 bus-range = <1 1>;
749 #address-cells = <3>;
750 #size-cells = <2>;
751 #interrupt-cells = <1>;
752 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
753 interrupt-map-mask = <0xff00 0 0 0x7>;
754 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
755 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
756 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
757
758 usb@0,1 {
759 reg = <0x800 0 0 0 0>;
760 device_type = "pci";
761 phys = <&usb2 0>;
762 phy-names = "usb";
763 };
764
765 usb@0,2 {
766 reg = <0x1000 0 0 0 0>;
767 device_type = "pci";
768 phys = <&usb2 0>;
769 phy-names = "usb";
770 };
771 };
772
773 hsusb: usb@e6590000 {
774 compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs";
775 reg = <0 0xe6590000 0 0x100>;
776 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
778 power-domains = <&cpg_clocks>;
779 renesas,buswait = <4>;
780 phys = <&usb0 1>;
781 phy-names = "usb";
782 status = "disabled";
783 };
784
785 usbphy: usb-phy@e6590100 {
786 compatible = "renesas,usb-phy-r8a7794";
787 reg = <0 0xe6590100 0 0x100>;
788 #address-cells = <1>;
789 #size-cells = <0>;
790 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
791 clock-names = "usbhs";
792 power-domains = <&cpg_clocks>;
793 status = "disabled";
794
795 usb0: usb-channel@0 {
796 reg = <0>;
797 #phy-cells = <1>;
798 };
799 usb2: usb-channel@2 {
800 reg = <2>;
801 #phy-cells = <1>;
802 };
803 };
804
805 du: display@feb00000 {
806 compatible = "renesas,du-r8a7794";
807 reg = <0 0xfeb00000 0 0x40000>;
808 reg-names = "du";
809 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&mstp7_clks R8A7794_CLK_DU0>,
812 <&mstp7_clks R8A7794_CLK_DU0>;
813 clock-names = "du.0", "du.1";
814 status = "disabled";
815
816 ports {
817 #address-cells = <1>;
818 #size-cells = <0>;
819
820 port@0 {
821 reg = <0>;
822 du_out_rgb0: endpoint {
823 };
824 };
825 port@1 {
826 reg = <1>;
827 du_out_rgb1: endpoint {
828 };
829 };
830 };
831 };
832
833 clocks {
834 #address-cells = <2>;
835 #size-cells = <2>;
836 ranges;
837
838 /* External root clock */
839 extal_clk: extal_clk {
840 compatible = "fixed-clock";
841 #clock-cells = <0>;
842 /* This value must be overriden by the board. */
843 clock-frequency = <0>;
844 clock-output-names = "extal";
845 };
846
847 /* External SCIF clock */
848 scif_clk: scif {
849 compatible = "fixed-clock";
850 #clock-cells = <0>;
851 /* This value must be overridden by the board. */
852 clock-frequency = <0>;
853 status = "disabled";
854 };
855
856 /* Special CPG clocks */
857 cpg_clocks: cpg_clocks@e6150000 {
858 compatible = "renesas,r8a7794-cpg-clocks",
859 "renesas,rcar-gen2-cpg-clocks";
860 reg = <0 0xe6150000 0 0x1000>;
861 clocks = <&extal_clk>;
862 #clock-cells = <1>;
863 clock-output-names = "main", "pll0", "pll1", "pll3",
864 "lb", "qspi", "sdh", "sd0", "z";
865 #power-domain-cells = <0>;
866 };
867 /* Variable factor clocks */
868 sd2_clk: sd2_clk@e6150078 {
869 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
870 reg = <0 0xe6150078 0 4>;
871 clocks = <&pll1_div2_clk>;
872 #clock-cells = <0>;
873 clock-output-names = "sd2";
874 };
875 sd3_clk: sd3_clk@e615026c {
876 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
877 reg = <0 0xe615026c 0 4>;
878 clocks = <&pll1_div2_clk>;
879 #clock-cells = <0>;
880 clock-output-names = "sd3";
881 };
882 mmc0_clk: mmc0_clk@e6150240 {
883 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
884 reg = <0 0xe6150240 0 4>;
885 clocks = <&pll1_div2_clk>;
886 #clock-cells = <0>;
887 clock-output-names = "mmc0";
888 };
889
890 /* Fixed factor clocks */
891 pll1_div2_clk: pll1_div2_clk {
892 compatible = "fixed-factor-clock";
893 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
894 #clock-cells = <0>;
895 clock-div = <2>;
896 clock-mult = <1>;
897 clock-output-names = "pll1_div2";
898 };
899 zg_clk: zg_clk {
900 compatible = "fixed-factor-clock";
901 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
902 #clock-cells = <0>;
903 clock-div = <6>;
904 clock-mult = <1>;
905 clock-output-names = "zg";
906 };
907 zx_clk: zx_clk {
908 compatible = "fixed-factor-clock";
909 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
910 #clock-cells = <0>;
911 clock-div = <3>;
912 clock-mult = <1>;
913 clock-output-names = "zx";
914 };
915 zs_clk: zs_clk {
916 compatible = "fixed-factor-clock";
917 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
918 #clock-cells = <0>;
919 clock-div = <6>;
920 clock-mult = <1>;
921 clock-output-names = "zs";
922 };
923 hp_clk: hp_clk {
924 compatible = "fixed-factor-clock";
925 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
926 #clock-cells = <0>;
927 clock-div = <12>;
928 clock-mult = <1>;
929 clock-output-names = "hp";
930 };
931 i_clk: i_clk {
932 compatible = "fixed-factor-clock";
933 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
934 #clock-cells = <0>;
935 clock-div = <2>;
936 clock-mult = <1>;
937 clock-output-names = "i";
938 };
939 b_clk: b_clk {
940 compatible = "fixed-factor-clock";
941 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
942 #clock-cells = <0>;
943 clock-div = <12>;
944 clock-mult = <1>;
945 clock-output-names = "b";
946 };
947 p_clk: p_clk {
948 compatible = "fixed-factor-clock";
949 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
950 #clock-cells = <0>;
951 clock-div = <24>;
952 clock-mult = <1>;
953 clock-output-names = "p";
954 };
955 cl_clk: cl_clk {
956 compatible = "fixed-factor-clock";
957 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
958 #clock-cells = <0>;
959 clock-div = <48>;
960 clock-mult = <1>;
961 clock-output-names = "cl";
962 };
963 m2_clk: m2_clk {
964 compatible = "fixed-factor-clock";
965 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
966 #clock-cells = <0>;
967 clock-div = <8>;
968 clock-mult = <1>;
969 clock-output-names = "m2";
970 };
971 rclk_clk: rclk_clk {
972 compatible = "fixed-factor-clock";
973 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
974 #clock-cells = <0>;
975 clock-div = <(48 * 1024)>;
976 clock-mult = <1>;
977 clock-output-names = "rclk";
978 };
979 oscclk_clk: oscclk_clk {
980 compatible = "fixed-factor-clock";
981 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
982 #clock-cells = <0>;
983 clock-div = <(12 * 1024)>;
984 clock-mult = <1>;
985 clock-output-names = "oscclk";
986 };
987 zb3_clk: zb3_clk {
988 compatible = "fixed-factor-clock";
989 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
990 #clock-cells = <0>;
991 clock-div = <4>;
992 clock-mult = <1>;
993 clock-output-names = "zb3";
994 };
995 zb3d2_clk: zb3d2_clk {
996 compatible = "fixed-factor-clock";
997 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
998 #clock-cells = <0>;
999 clock-div = <8>;
1000 clock-mult = <1>;
1001 clock-output-names = "zb3d2";
1002 };
1003 ddr_clk: ddr_clk {
1004 compatible = "fixed-factor-clock";
1005 clocks = <&cpg_clocks R8A7794_CLK_PLL3>;
1006 #clock-cells = <0>;
1007 clock-div = <8>;
1008 clock-mult = <1>;
1009 clock-output-names = "ddr";
1010 };
1011 mp_clk: mp_clk {
1012 compatible = "fixed-factor-clock";
1013 clocks = <&pll1_div2_clk>;
1014 #clock-cells = <0>;
1015 clock-div = <15>;
1016 clock-mult = <1>;
1017 clock-output-names = "mp";
1018 };
1019 cp_clk: cp_clk {
1020 compatible = "fixed-factor-clock";
1021 clocks = <&cpg_clocks R8A7794_CLK_PLL1>;
1022 #clock-cells = <0>;
1023 clock-div = <48>;
1024 clock-mult = <1>;
1025 clock-output-names = "cp";
1026 };
1027
1028 acp_clk: acp_clk {
1029 compatible = "fixed-factor-clock";
1030 clocks = <&extal_clk>;
1031 #clock-cells = <0>;
1032 clock-div = <2>;
1033 clock-mult = <1>;
1034 clock-output-names = "acp";
1035 };
1036
1037 /* Gate clocks */
1038 mstp0_clks: mstp0_clks@e6150130 {
1039 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1040 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1041 clocks = <&mp_clk>;
1042 #clock-cells = <1>;
1043 clock-indices = <R8A7794_CLK_MSIOF0>;
1044 clock-output-names = "msiof0";
1045 };
1046 mstp1_clks: mstp1_clks@e6150134 {
1047 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1048 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1049 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
1050 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
1051 <&zs_clk>, <&zs_clk>;
1052 #clock-cells = <1>;
1053 clock-indices = <
1054 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
1055 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
1056 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
1057 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
1058 >;
1059 clock-output-names =
1060 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
1061 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
1062 };
1063 mstp2_clks: mstp2_clks@e6150138 {
1064 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1065 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1066 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1067 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1068 <&zs_clk>, <&zs_clk>;
1069 #clock-cells = <1>;
1070 clock-indices = <
1071 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
1072 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
1073 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
1074 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0
1075 >;
1076 clock-output-names =
1077 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1078 "scifb1", "msiof1", "scifb2",
1079 "sys-dmac1", "sys-dmac0";
1080 };
1081 mstp3_clks: mstp3_clks@e615013c {
1082 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1083 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1084 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
1085 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1086 #clock-cells = <1>;
1087 clock-indices = <
1088 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
1089 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
1090 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
1091 >;
1092 clock-output-names =
1093 "sdhi2", "sdhi1", "sdhi0",
1094 "mmcif0", "cmt1", "usbdmac0", "usbdmac1";
1095 };
1096 mstp4_clks: mstp4_clks@e6150140 {
1097 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1098 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1099 clocks = <&cp_clk>;
1100 #clock-cells = <1>;
1101 clock-indices = <R8A7794_CLK_IRQC>;
1102 clock-output-names = "irqc";
1103 };
1104 mstp7_clks: mstp7_clks@e615014c {
1105 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1106 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1107 clocks = <&mp_clk>, <&mp_clk>,
1108 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1109 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1110 <&zx_clk>;
1111 #clock-cells = <1>;
1112 clock-indices = <
1113 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB
1114 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
1115 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
1116 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
1117 R8A7794_CLK_SCIF0 R8A7794_CLK_DU0
1118 >;
1119 clock-output-names =
1120 "ehci", "hsusb",
1121 "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1122 "scif3", "scif2", "scif1", "scif0", "du0";
1123 };
1124 mstp8_clks: mstp8_clks@e6150990 {
1125 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1126 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1127 clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>;
1128 #clock-cells = <1>;
1129 clock-indices = <
1130 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0
1131 R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER
1132 >;
1133 clock-output-names =
1134 "vin1", "vin0", "etheravb", "ether";
1135 };
1136 mstp9_clks: mstp9_clks@e6150994 {
1137 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1138 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1139 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1140 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1141 <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
1142 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
1143 #clock-cells = <1>;
1144 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
1145 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
1146 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
1147 R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD
1148 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
1149 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
1150 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
1151 clock-output-names =
1152 "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
1153 "gpio1", "gpio0", "qspi_mod",
1154 "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
1155 };
1156 mstp11_clks: mstp11_clks@e615099c {
1157 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
1158 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1159 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1160 #clock-cells = <1>;
1161 clock-indices = <
1162 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
1163 >;
1164 clock-output-names = "scifa3", "scifa4", "scifa5";
1165 };
1166 };
1167
1168 ipmmu_sy0: mmu@e6280000 {
1169 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1170 reg = <0 0xe6280000 0 0x1000>;
1171 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1173 #iommu-cells = <1>;
1174 status = "disabled";
1175 };
1176
1177 ipmmu_sy1: mmu@e6290000 {
1178 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1179 reg = <0 0xe6290000 0 0x1000>;
1180 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1181 #iommu-cells = <1>;
1182 status = "disabled";
1183 };
1184
1185 ipmmu_ds: mmu@e6740000 {
1186 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1187 reg = <0 0xe6740000 0 0x1000>;
1188 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1190 #iommu-cells = <1>;
1191 status = "disabled";
1192 };
1193
1194 ipmmu_mp: mmu@ec680000 {
1195 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1196 reg = <0 0xec680000 0 0x1000>;
1197 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1198 #iommu-cells = <1>;
1199 status = "disabled";
1200 };
1201
1202 ipmmu_mx: mmu@fe951000 {
1203 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1204 reg = <0 0xfe951000 0 0x1000>;
1205 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1207 #iommu-cells = <1>;
1208 status = "disabled";
1209 };
1210
1211 ipmmu_gp: mmu@e62a0000 {
1212 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1213 reg = <0 0xe62a0000 0 0x1000>;
1214 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1216 #iommu-cells = <1>;
1217 status = "disabled";
1218 };
1219};