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1// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * SDX55 SoC device tree source
4 *
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2020, Linaro Ltd.
7 */
8
9#include <dt-bindings/clock/qcom,gcc-sdx55.h>
10#include <dt-bindings/clock/qcom,rpmh.h>
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interconnect/qcom,sdx55.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/power/qcom-rpmpd.h>
15#include <dt-bindings/soc/qcom,rpmh-rsc.h>
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
21 interrupt-parent = <&intc>;
22
23 memory {
24 device_type = "memory";
25 reg = <0 0>;
26 };
27
28 clocks {
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <38400000>;
33 clock-output-names = "xo_board";
34 };
35
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <32000>;
40 };
41
42 nand_clk_dummy: nand-clk-dummy {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <32000>;
46 };
47 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
53 cpu0: cpu@0 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a7";
56 reg = <0x0>;
57 enable-method = "psci";
58 clocks = <&apcs>;
59 power-domains = <&rpmhpd SDX55_CX>;
60 power-domain-names = "rpmhpd";
61 operating-points-v2 = <&cpu_opp_table>;
62 };
63 };
64
65 cpu_opp_table: cpu-opp-table {
66 compatible = "operating-points-v2";
67 opp-shared;
68
69 opp-345600000 {
70 opp-hz = /bits/ 64 <345600000>;
71 required-opps = <&rpmhpd_opp_low_svs>;
72 };
73
74 opp-576000000 {
75 opp-hz = /bits/ 64 <576000000>;
76 required-opps = <&rpmhpd_opp_svs>;
77 };
78
79 opp-1094400000 {
80 opp-hz = /bits/ 64 <1094400000>;
81 required-opps = <&rpmhpd_opp_nom>;
82 };
83
84 opp-1555200000 {
85 opp-hz = /bits/ 64 <1555200000>;
86 required-opps = <&rpmhpd_opp_turbo>;
87 };
88 };
89
90 firmware {
91 scm {
92 compatible = "qcom,scm-sdx55", "qcom,scm";
93 };
94 };
95
96 psci {
97 compatible = "arm,psci-1.0";
98 method = "smc";
99 };
100
101 reserved-memory {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges;
105
106 hyp_mem: memory@8fc00000 {
107 no-map;
108 reg = <0x8fc00000 0x80000>;
109 };
110
111 ac_db_mem: memory@8fc80000 {
112 no-map;
113 reg = <0x8fc80000 0x40000>;
114 };
115
116 secdata_mem: memory@8fcfd000 {
117 no-map;
118 reg = <0x8fcfd000 0x1000>;
119 };
120
121 sbl_mem: memory@8fd00000 {
122 no-map;
123 reg = <0x8fd00000 0x100000>;
124 };
125
126 aop_image: memory@8fe00000 {
127 no-map;
128 reg = <0x8fe00000 0x20000>;
129 };
130
131 aop_cmd_db: memory@8fe20000 {
132 compatible = "qcom,cmd-db";
133 reg = <0x8fe20000 0x20000>;
134 no-map;
135 };
136
137 smem_mem: memory@8fe40000 {
138 no-map;
139 reg = <0x8fe40000 0xc0000>;
140 };
141
142 tz_mem: memory@8ff00000 {
143 no-map;
144 reg = <0x8ff00000 0x100000>;
145 };
146
147 tz_apps_mem: memory@90000000 {
148 no-map;
149 reg = <0x90000000 0x500000>;
150 };
151 };
152
153 smem {
154 compatible = "qcom,smem";
155 memory-region = <&smem_mem>;
156 hwlocks = <&tcsr_mutex 3>;
157 };
158
159 smp2p-mpss {
160 compatible = "qcom,smp2p";
161 qcom,smem = <435>, <428>;
162 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
163 mboxes = <&apcs 14>;
164 qcom,local-pid = <0>;
165 qcom,remote-pid = <1>;
166
167 modem_smp2p_out: master-kernel {
168 qcom,entry-name = "master-kernel";
169 #qcom,smem-state-cells = <1>;
170 };
171
172 modem_smp2p_in: slave-kernel {
173 qcom,entry-name = "slave-kernel";
174 interrupt-controller;
175 #interrupt-cells = <2>;
176 };
177
178 ipa_smp2p_out: ipa-ap-to-modem {
179 qcom,entry-name = "ipa";
180 #qcom,smem-state-cells = <1>;
181 };
182
183 ipa_smp2p_in: ipa-modem-to-ap {
184 qcom,entry-name = "ipa";
185 interrupt-controller;
186 #interrupt-cells = <2>;
187 };
188 };
189
190 soc: soc {
191 #address-cells = <1>;
192 #size-cells = <1>;
193 ranges;
194 compatible = "simple-bus";
195
196 gcc: clock-controller@100000 {
197 compatible = "qcom,gcc-sdx55";
198 reg = <0x100000 0x1f0000>;
199 #clock-cells = <1>;
200 #reset-cells = <1>;
201 #power-domain-cells = <1>;
202 clock-names = "bi_tcxo", "sleep_clk";
203 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
204 };
205
206 blsp1_uart3: serial@831000 {
207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
208 reg = <0x00831000 0x200>;
209 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&gcc 30>,
211 <&gcc 9>;
212 clock-names = "core", "iface";
213 status = "disabled";
214 };
215
216 usb_hsphy: phy@ff4000 {
217 compatible = "qcom,usb-snps-hs-7nm-phy";
218 reg = <0x00ff4000 0x114>;
219 status = "disabled";
220 #phy-cells = <0>;
221
222 clocks = <&rpmhcc RPMH_CXO_CLK>;
223 clock-names = "ref";
224
225 resets = <&gcc GCC_QUSB2PHY_BCR>;
226 };
227
228 usb_qmpphy: phy@ff6000 {
229 compatible = "qcom,sdx55-qmp-usb3-uni-phy";
230 reg = <0x00ff6000 0x1c0>;
231 status = "disabled";
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges;
235
236 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
237 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
238 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
239 clock-names = "aux", "cfg_ahb", "ref";
240
241 resets = <&gcc GCC_USB3PHY_PHY_BCR>,
242 <&gcc GCC_USB3_PHY_BCR>;
243 reset-names = "phy", "common";
244
245 usb_ssphy: phy@ff6200 {
246 reg = <0x00ff6200 0x170>,
247 <0x00ff6400 0x200>,
248 <0x00ff6800 0x800>;
249 #phy-cells = <0>;
250 #clock-cells = <0>;
251 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
252 clock-names = "pipe0";
253 clock-output-names = "usb3_uni_phy_pipe_clk_src";
254 };
255 };
256
257 mc_virt: interconnect@1100000 {
258 compatible = "qcom,sdx55-mc-virt";
259 reg = <0x01100000 0x400000>;
260 #interconnect-cells = <1>;
261 qcom,bcm-voters = <&apps_bcm_voter>;
262 };
263
264 mem_noc: interconnect@9680000 {
265 compatible = "qcom,sdx55-mem-noc";
266 reg = <0x09680000 0x40000>;
267 #interconnect-cells = <1>;
268 qcom,bcm-voters = <&apps_bcm_voter>;
269 };
270
271 system_noc: interconnect@162c000 {
272 compatible = "qcom,sdx55-system-noc";
273 reg = <0x0162c000 0x31200>;
274 #interconnect-cells = <1>;
275 qcom,bcm-voters = <&apps_bcm_voter>;
276 };
277
278 qpic_bam: dma-controller@1b04000 {
279 compatible = "qcom,bam-v1.7.0";
280 reg = <0x01b04000 0x1c000>;
281 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&rpmhcc RPMH_QPIC_CLK>;
283 clock-names = "bam_clk";
284 #dma-cells = <1>;
285 qcom,ee = <0>;
286 qcom,controlled-remotely;
287 status = "disabled";
288 };
289
290 qpic_nand: nand-controller@1b30000 {
291 compatible = "qcom,sdx55-nand";
292 reg = <0x01b30000 0x10000>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 clocks = <&rpmhcc RPMH_QPIC_CLK>,
296 <&nand_clk_dummy>;
297 clock-names = "core", "aon";
298
299 dmas = <&qpic_bam 0>,
300 <&qpic_bam 1>,
301 <&qpic_bam 2>;
302 dma-names = "tx", "rx", "cmd";
303 status = "disabled";
304 };
305
306 pcie0_phy: phy@1c07000 {
307 compatible = "qcom,sdx55-qmp-pcie-phy";
308 reg = <0x01c07000 0x1c4>;
309 #address-cells = <1>;
310 #size-cells = <1>;
311 ranges;
312 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
313 <&gcc GCC_PCIE_CFG_AHB_CLK>,
314 <&gcc GCC_PCIE_0_CLKREF_CLK>,
315 <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
316 clock-names = "aux", "cfg_ahb", "ref", "refgen";
317
318 resets = <&gcc GCC_PCIE_PHY_BCR>;
319 reset-names = "phy";
320
321 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
322 assigned-clock-rates = <100000000>;
323
324 status = "disabled";
325
326 pcie0_lane: lanes@1c06000 {
327 reg = <0x01c06000 0x104>, /* tx0 */
328 <0x01c06200 0x328>, /* rx0 */
329 <0x01c07200 0x1e8>, /* pcs */
330 <0x01c06800 0x104>, /* tx1 */
331 <0x01c06a00 0x328>, /* rx1 */
332 <0x01c07600 0x800>; /* pcs_misc */
333 clocks = <&gcc GCC_PCIE_PIPE_CLK>;
334 clock-names = "pipe0";
335
336 #phy-cells = <0>;
337 clock-output-names = "pcie_pipe_clk";
338 };
339 };
340
341 ipa: ipa@1e40000 {
342 compatible = "qcom,sdx55-ipa";
343
344 iommus = <&apps_smmu 0x5e0 0x0>,
345 <&apps_smmu 0x5e2 0x0>;
346 reg = <0x1e40000 0x7000>,
347 <0x1e50000 0x4b20>,
348 <0x1e04000 0x2c000>;
349 reg-names = "ipa-reg",
350 "ipa-shared",
351 "gsi";
352
353 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
354 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
355 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
356 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
357 interrupt-names = "ipa",
358 "gsi",
359 "ipa-clock-query",
360 "ipa-setup-ready";
361
362 clocks = <&rpmhcc RPMH_IPA_CLK>;
363 clock-names = "core";
364
365 interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI_CH0>,
366 <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
367 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>;
368 interconnect-names = "memory",
369 "imem",
370 "config";
371
372 qcom,smem-states = <&ipa_smp2p_out 0>,
373 <&ipa_smp2p_out 1>;
374 qcom,smem-state-names = "ipa-clock-enabled-valid",
375 "ipa-clock-enabled";
376
377 status = "disabled";
378 };
379
380 tcsr_mutex: hwlock@1f40000 {
381 compatible = "qcom,tcsr-mutex";
382 reg = <0x01f40000 0x40000>;
383 #hwlock-cells = <1>;
384 };
385
386 tcsr: syscon@1fcb000 {
387 compatible = "syscon";
388 reg = <0x01fc0000 0x1000>;
389 };
390
391 sdhc_1: mmc@8804000 {
392 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
393 reg = <0x08804000 0x1000>;
394 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
396 interrupt-names = "hc_irq", "pwr_irq";
397 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
398 <&gcc GCC_SDCC1_APPS_CLK>;
399 clock-names = "iface", "core";
400 status = "disabled";
401 };
402
403 pcie_ep: pcie-ep@40000000 {
404 compatible = "qcom,sdx55-pcie-ep";
405 reg = <0x01c00000 0x3000>,
406 <0x40000000 0xf1d>,
407 <0x40000f20 0xc8>,
408 <0x40001000 0x1000>,
409 <0x40200000 0x100000>,
410 <0x01c03000 0x3000>;
411 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
412 "mmio";
413
414 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
415
416 clocks = <&gcc GCC_PCIE_AUX_CLK>,
417 <&gcc GCC_PCIE_CFG_AHB_CLK>,
418 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
419 <&gcc GCC_PCIE_SLV_AXI_CLK>,
420 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
421 <&gcc GCC_PCIE_SLEEP_CLK>,
422 <&gcc GCC_PCIE_0_CLKREF_CLK>;
423 clock-names = "aux", "cfg", "bus_master", "bus_slave",
424 "slave_q2a", "sleep", "ref";
425
426 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
428 interrupt-names = "global", "doorbell";
429 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
430 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
431 resets = <&gcc GCC_PCIE_BCR>;
432 reset-names = "core";
433 power-domains = <&gcc PCIE_GDSC>;
434 phys = <&pcie0_lane>;
435 phy-names = "pciephy";
436 max-link-speed = <3>;
437 num-lanes = <2>;
438
439 status = "disabled";
440 };
441
442 remoteproc_mpss: remoteproc@4080000 {
443 compatible = "qcom,sdx55-mpss-pas";
444 reg = <0x04080000 0x4040>;
445
446 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
447 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
448 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
449 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
450 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
451 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
452 interrupt-names = "wdog", "fatal", "ready", "handover",
453 "stop-ack", "shutdown-ack";
454
455 clocks = <&rpmhcc RPMH_CXO_CLK>;
456 clock-names = "xo";
457
458 power-domains = <&rpmhpd SDX55_CX>,
459 <&rpmhpd SDX55_MSS>;
460 power-domain-names = "cx", "mss";
461
462 qcom,smem-states = <&modem_smp2p_out 0>;
463 qcom,smem-state-names = "stop";
464
465 status = "disabled";
466
467 glink-edge {
468 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
469 label = "mpss";
470 qcom,remote-pid = <1>;
471 mboxes = <&apcs 15>;
472 };
473 };
474
475 usb: usb@a6f8800 {
476 compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
477 reg = <0x0a6f8800 0x400>;
478 status = "disabled";
479 #address-cells = <1>;
480 #size-cells = <1>;
481 ranges;
482
483 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
484 <&gcc GCC_USB30_MASTER_CLK>,
485 <&gcc GCC_USB30_MSTR_AXI_CLK>,
486 <&gcc GCC_USB30_SLEEP_CLK>,
487 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
488 clock-names = "cfg_noc",
489 "core",
490 "iface",
491 "sleep",
492 "mock_utmi";
493
494 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
495 <&gcc GCC_USB30_MASTER_CLK>;
496 assigned-clock-rates = <19200000>, <200000000>;
497
498 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
502 interrupt-names = "hs_phy_irq", "ss_phy_irq",
503 "dm_hs_phy_irq", "dp_hs_phy_irq";
504
505 power-domains = <&gcc USB30_GDSC>;
506
507 resets = <&gcc GCC_USB30_BCR>;
508
509 usb_dwc3: dwc3@a600000 {
510 compatible = "snps,dwc3";
511 reg = <0x0a600000 0xcd00>;
512 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
513 iommus = <&apps_smmu 0x1a0 0x0>;
514 snps,dis_u2_susphy_quirk;
515 snps,dis_enblslpm_quirk;
516 phys = <&usb_hsphy>, <&usb_ssphy>;
517 phy-names = "usb2-phy", "usb3-phy";
518 };
519 };
520
521 pdc: interrupt-controller@b210000 {
522 compatible = "qcom,sdx55-pdc", "qcom,pdc";
523 reg = <0x0b210000 0x30000>;
524 qcom,pdc-ranges = <0 179 52>;
525 #interrupt-cells = <3>;
526 interrupt-parent = <&intc>;
527 interrupt-controller;
528 };
529
530 restart@c264000 {
531 compatible = "qcom,pshold";
532 reg = <0x0c264000 0x1000>;
533 };
534
535 spmi_bus: spmi@c440000 {
536 compatible = "qcom,spmi-pmic-arb";
537 reg = <0x0c440000 0x0000d00>,
538 <0x0c600000 0x2000000>,
539 <0x0e600000 0x0100000>,
540 <0x0e700000 0x00a0000>,
541 <0x0c40a000 0x0000700>;
542 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
543 interrupt-names = "periph_irq";
544 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
545 qcom,ee = <0>;
546 qcom,channel = <0>;
547 #address-cells = <2>;
548 #size-cells = <0>;
549 interrupt-controller;
550 #interrupt-cells = <4>;
551 cell-index = <0>;
552 };
553
554 tlmm: pinctrl@f100000 {
555 compatible = "qcom,sdx55-pinctrl";
556 reg = <0xf100000 0x300000>;
557 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
558 gpio-controller;
559 #gpio-cells = <2>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
562 gpio-ranges = <&tlmm 0 0 109>;
563 };
564
565 sram@1468f000 {
566 compatible = "qcom,sdx55-imem", "syscon", "simple-mfd";
567 reg = <0x1468f000 0x1000>;
568
569 #address-cells = <1>;
570 #size-cells = <1>;
571
572 ranges = <0x0 0x1468f000 0x1000>;
573
574 pil-reloc@94c {
575 compatible = "qcom,pil-reloc-info";
576 reg = <0x94c 0x200>;
577 };
578 };
579
580 apps_smmu: iommu@15000000 {
581 compatible = "qcom,sdx55-smmu-500", "arm,mmu-500";
582 reg = <0x15000000 0x20000>;
583 #iommu-cells = <2>;
584 #global-interrupts = <1>;
585 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
602 };
603
604 intc: interrupt-controller@17800000 {
605 compatible = "qcom,msm-qgic2";
606 interrupt-controller;
607 interrupt-parent = <&intc>;
608 #interrupt-cells = <3>;
609 reg = <0x17800000 0x1000>,
610 <0x17802000 0x1000>;
611 };
612
613 a7pll: clock@17808000 {
614 compatible = "qcom,sdx55-a7pll";
615 reg = <0x17808000 0x1000>;
616 clocks = <&rpmhcc RPMH_CXO_CLK>;
617 clock-names = "bi_tcxo";
618 #clock-cells = <0>;
619 };
620
621 apcs: mailbox@17810000 {
622 compatible = "qcom,sdx55-apcs-gcc", "syscon";
623 reg = <0x17810000 0x2000>;
624 #mbox-cells = <1>;
625 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
626 clock-names = "ref", "pll", "aux";
627 #clock-cells = <0>;
628 };
629
630 watchdog@17817000 {
631 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
632 reg = <0x17817000 0x1000>;
633 clocks = <&sleep_clk>;
634 };
635
636 timer@17820000 {
637 #address-cells = <1>;
638 #size-cells = <1>;
639 ranges;
640 compatible = "arm,armv7-timer-mem";
641 reg = <0x17820000 0x1000>;
642 clock-frequency = <19200000>;
643
644 frame@17821000 {
645 frame-number = <0>;
646 interrupts = <GIC_SPI 7 0x4>,
647 <GIC_SPI 6 0x4>;
648 reg = <0x17821000 0x1000>,
649 <0x17822000 0x1000>;
650 };
651
652 frame@17823000 {
653 frame-number = <1>;
654 interrupts = <GIC_SPI 8 0x4>;
655 reg = <0x17823000 0x1000>;
656 status = "disabled";
657 };
658
659 frame@17824000 {
660 frame-number = <2>;
661 interrupts = <GIC_SPI 9 0x4>;
662 reg = <0x17824000 0x1000>;
663 status = "disabled";
664 };
665
666 frame@17825000 {
667 frame-number = <3>;
668 interrupts = <GIC_SPI 10 0x4>;
669 reg = <0x17825000 0x1000>;
670 status = "disabled";
671 };
672
673 frame@17826000 {
674 frame-number = <4>;
675 interrupts = <GIC_SPI 11 0x4>;
676 reg = <0x17826000 0x1000>;
677 status = "disabled";
678 };
679
680 frame@17827000 {
681 frame-number = <5>;
682 interrupts = <GIC_SPI 12 0x4>;
683 reg = <0x17827000 0x1000>;
684 status = "disabled";
685 };
686
687 frame@17828000 {
688 frame-number = <6>;
689 interrupts = <GIC_SPI 13 0x4>;
690 reg = <0x17828000 0x1000>;
691 status = "disabled";
692 };
693
694 frame@17829000 {
695 frame-number = <7>;
696 interrupts = <GIC_SPI 14 0x4>;
697 reg = <0x17829000 0x1000>;
698 status = "disabled";
699 };
700 };
701
702 apps_rsc: rsc@17840000 {
703 compatible = "qcom,rpmh-rsc";
704 reg = <0x17830000 0x10000>, <0x17840000 0x10000>;
705 reg-names = "drv-0", "drv-1";
706 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
708 qcom,tcs-offset = <0xd00>;
709 qcom,drv-id = <1>;
710 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
711 <WAKE_TCS 2>, <CONTROL_TCS 1>;
712
713 rpmhcc: clock-controller {
714 compatible = "qcom,sdx55-rpmh-clk";
715 #clock-cells = <1>;
716 clock-names = "xo";
717 clocks = <&xo_board>;
718 };
719
720 rpmhpd: power-controller {
721 compatible = "qcom,sdx55-rpmhpd";
722 #power-domain-cells = <1>;
723 operating-points-v2 = <&rpmhpd_opp_table>;
724
725 rpmhpd_opp_table: opp-table {
726 compatible = "operating-points-v2";
727
728 rpmhpd_opp_ret: opp1 {
729 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
730 };
731
732 rpmhpd_opp_min_svs: opp2 {
733 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
734 };
735
736 rpmhpd_opp_low_svs: opp3 {
737 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
738 };
739
740 rpmhpd_opp_svs: opp4 {
741 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
742 };
743
744 rpmhpd_opp_svs_l1: opp5 {
745 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
746 };
747
748 rpmhpd_opp_nom: opp6 {
749 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
750 };
751
752 rpmhpd_opp_nom_l1: opp7 {
753 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
754 };
755
756 rpmhpd_opp_nom_l2: opp8 {
757 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
758 };
759
760 rpmhpd_opp_turbo: opp9 {
761 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
762 };
763
764 rpmhpd_opp_turbo_l1: opp10 {
765 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
766 };
767 };
768 };
769
770 apps_bcm_voter: bcm-voter {
771 compatible = "qcom,bcm-voter";
772 };
773 };
774 };
775
776 timer {
777 compatible = "arm,armv7-timer";
778 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
779 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
780 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
781 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
782 clock-frequency = <19200000>;
783 };
784};