1/*
  2 * PHYTEC phyCORE-LPC3250 board
  3 *
  4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
  5 *
  6 * The code contained herein is licensed under the GNU General Public
  7 * License. You may obtain a copy of the GNU General Public License
  8 * Version 2 or later at the following locations:
  9 *
 10 * http://www.opensource.org/licenses/gpl-license.html
 11 * http://www.gnu.org/copyleft/gpl.html
 12 */
 13
 14/dts-v1/;
 15#include "lpc32xx.dtsi"
 16
 17/ {
 18	model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
 19	compatible = "phytec,phy3250", "nxp,lpc3250";
 20	#address-cells = <1>;
 21	#size-cells = <1>;
 22
 23	memory {
 24		device_type = "memory";
 25		reg = <0x80000000 0x4000000>;
 26	};
 27
 28	regulators {
 29		backlight_reg: regulator@0 {
 30			compatible = "regulator-fixed";
 31			regulator-name = "backlight_reg";
 32			regulator-min-microvolt = <1800000>;
 33			regulator-max-microvolt = <1800000>;
 34			gpio = <&gpio 5 4 0>;
 35			enable-active-high;
 36			regulator-boot-on;
 37		};
 38
 39		lcd_reg: regulator@1 {
 40			compatible = "regulator-fixed";
 41			regulator-name = "lcd_reg";
 42			regulator-min-microvolt = <1800000>;
 43			regulator-max-microvolt = <1800000>;
 44			gpio = <&gpio 5 0 0>;
 45			enable-active-high;
 46			regulator-boot-on;
 47		};
 48
 49		sd_reg: regulator@2 {
 50			compatible = "regulator-fixed";
 51			regulator-name = "sd_reg";
 52			regulator-min-microvolt = <1800000>;
 53			regulator-max-microvolt = <1800000>;
 54			gpio = <&gpio 5 5 0>;
 55			enable-active-high;
 56		};
 57	};
 58
 59	ahb {
 60		mac: ethernet@31060000 {
 61			phy-mode = "rmii";
 62			use-iram;
 63		};
 64
 65		clcd@31040000 {
 66			status = "okay";
 67		};
 68
 69		/* 64MB Flash via SLC NAND controller */
 70		slc: flash@20020000 {
 71			status = "okay";
 72			#address-cells = <1>;
 73			#size-cells = <1>;
 74
 75			nxp,wdr-clks = <14>;
 76			nxp,wwidth = <40000000>;
 77			nxp,whold = <100000000>;
 78			nxp,wsetup = <100000000>;
 79			nxp,rdr-clks = <14>;
 80			nxp,rwidth = <40000000>;
 81			nxp,rhold = <66666666>;
 82			nxp,rsetup = <100000000>;
 83			nand-on-flash-bbt;
 84			gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
 85
 86			mtd0@00000000 {
 87				label = "phy3250-boot";
 88				reg = <0x00000000 0x00064000>;
 89				read-only;
 90			};
 91
 92			mtd1@00064000 {
 93				label = "phy3250-uboot";
 94				reg = <0x00064000 0x00190000>;
 95				read-only;
 96			};
 97
 98			mtd2@001f4000 {
 99				label = "phy3250-ubt-prms";
100				reg = <0x001f4000 0x00010000>;
101			};
102
103			mtd3@00204000 {
104				label = "phy3250-kernel";
105				reg = <0x00204000 0x00400000>;
106			};
107
108			mtd4@00604000 {
109				label = "phy3250-rootfs";
110				reg = <0x00604000 0x039fc000>;
111			};
112		};
113
114		apb {
115			uart5: serial@40090000 {
116				status = "okay";
117			};
118
119			uart3: serial@40080000 {
120				status = "okay";
121			};
122
123			i2c1: i2c@400A0000 {
124				clock-frequency = <100000>;
125
126				pcf8563: rtc@51 {
127					compatible = "nxp,pcf8563";
128					reg = <0x51>;
129				};
130
131				uda1380: uda1380@18 {
132					compatible = "nxp,uda1380";
133					reg = <0x18>;
134					power-gpio = <&gpio 0x59 0>;
135					reset-gpio = <&gpio 0x51 0>;
136					dac-clk = "wspll";
137				};
138			};
139
140			i2c2: i2c@400A8000 {
141				clock-frequency = <100000>;
142			};
143
144			ssp0: ssp@20084000 {
145				#address-cells = <1>;
146				#size-cells = <0>;
147				num-cs = <1>;
148				cs-gpios = <&gpio 3 5 0>;
149
150				eeprom: at25@0 {
151					pl022,interface = <0>;
152					pl022,com-mode = <0>;
153					pl022,rx-level-trig = <1>;
154					pl022,tx-level-trig = <1>;
155					pl022,ctrl-len = <11>;
156					pl022,wait-state = <0>;
157					pl022,duplex = <0>;
158
159					at25,byte-len = <0x8000>;
160					at25,addr-mode = <2>;
161					at25,page-size = <64>;
162
163					compatible = "atmel,at25";
164					reg = <0>;
165					spi-max-frequency = <5000000>;
166				};
167			};
168
169			sd@20098000 {
170				wp-gpios = <&gpio 3 0 0>;
171				cd-gpios = <&gpio 3 1 0>;
172				cd-inverted;
173				bus-width = <4>;
174				vmmc-supply = <&sd_reg>;
175				status = "okay";
176			};
177		};
178
179		fab {
180			uart2: serial@40018000 {
181				status = "okay";
182			};
183
184			tsc@40048000 {
185				status = "okay";
186			};
187
188			key@40050000 {
189				status = "okay";
190				keypad,num-rows = <1>;
191				keypad,num-columns = <1>;
192				nxp,debounce-delay-ms = <3>;
193				nxp,scan-delay-ms = <34>;
194				linux,keymap = <0x00000002>;
195			};
196		};
197	};
198
199	leds {
200		compatible = "gpio-leds";
201
202		led0 { /* red */
203			gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
204			default-state = "off";
205		};
206
207		led1 { /* green */
208			gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
209			linux,default-trigger = "heartbeat";
210		};
211	};
212};
213
214/* Here, choose exactly one from: ohci, usbd */
215&ohci /* &usbd */ {
216	transceiver = <&isp1301>;
217	status = "okay";
218};
219
220&i2cusb {
221	clock-frequency = <100000>;
222
223	isp1301: usb-transceiver@2c {
224		compatible = "nxp,isp1301";
225		reg = <0x2c>;
226	};
227};