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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/thermal/thermal.h>
8
9/ {
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
13
14 aliases {
15 crypto = &crypto;
16 ethernet0 = &enet0;
17 ethernet1 = &enet1;
18 ethernet2 = &enet2;
19 rtc1 = &ftm_alarm0;
20 serial0 = &lpuart0;
21 serial1 = &lpuart1;
22 serial2 = &lpuart2;
23 serial3 = &lpuart3;
24 serial4 = &lpuart4;
25 serial5 = &lpuart5;
26 sysclk = &sysclk;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu0: cpu@f00 {
34 compatible = "arm,cortex-a7";
35 device_type = "cpu";
36 reg = <0xf00>;
37 clocks = <&clockgen 1 0>;
38 #cooling-cells = <2>;
39 };
40
41 cpu1: cpu@f01 {
42 compatible = "arm,cortex-a7";
43 device_type = "cpu";
44 reg = <0xf01>;
45 clocks = <&clockgen 1 0>;
46 #cooling-cells = <2>;
47 };
48 };
49
50 memory@0 {
51 device_type = "memory";
52 reg = <0x0 0x0 0x0 0x0>;
53 };
54
55 sysclk: sysclk {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <100000000>;
59 clock-output-names = "sysclk";
60 };
61
62 timer {
63 compatible = "arm,armv7-timer";
64 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
65 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
66 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
68 };
69
70 pmu {
71 compatible = "arm,cortex-a7-pmu";
72 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
74 interrupt-affinity = <&cpu0>, <&cpu1>;
75 };
76
77 reboot {
78 compatible = "syscon-reboot";
79 regmap = <&dcfg>;
80 offset = <0xb0>;
81 mask = <0x02>;
82 };
83
84 soc {
85 compatible = "simple-bus";
86 #address-cells = <2>;
87 #size-cells = <2>;
88 device_type = "soc";
89 interrupt-parent = <&gic>;
90 ranges;
91
92 ddr: memory-controller@1080000 {
93 compatible = "fsl,qoriq-memory-controller";
94 reg = <0x0 0x1080000 0x0 0x1000>;
95 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
96 big-endian;
97 };
98
99 gic: interrupt-controller@1400000 {
100 compatible = "arm,gic-400", "arm,cortex-a7-gic";
101 #interrupt-cells = <3>;
102 interrupt-controller;
103 reg = <0x0 0x1401000 0x0 0x1000>,
104 <0x0 0x1402000 0x0 0x2000>,
105 <0x0 0x1404000 0x0 0x2000>,
106 <0x0 0x1406000 0x0 0x2000>;
107 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
108
109 };
110
111 msi1: msi-controller@1570e00 {
112 compatible = "fsl,ls1021a-msi";
113 reg = <0x0 0x1570e00 0x0 0x8>;
114 msi-controller;
115 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
116 };
117
118 msi2: msi-controller@1570e08 {
119 compatible = "fsl,ls1021a-msi";
120 reg = <0x0 0x1570e08 0x0 0x8>;
121 msi-controller;
122 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
123 };
124
125 ifc: memory-controller@1530000 {
126 compatible = "fsl,ifc";
127 reg = <0x0 0x1530000 0x0 0x10000>;
128 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
129 status = "disabled";
130 };
131
132 sfp: efuse@1e80000 {
133 compatible = "fsl,ls1021a-sfp";
134 reg = <0x0 0x1e80000 0x0 0x10000>;
135 clocks = <&clockgen 4 3>;
136 clock-names = "sfp";
137 };
138
139 dcfg: dcfg@1ee0000 {
140 compatible = "fsl,ls1021a-dcfg", "syscon";
141 reg = <0x0 0x1ee0000 0x0 0x1000>;
142 big-endian;
143 };
144
145 qspi: spi@1550000 {
146 compatible = "fsl,ls1021a-qspi";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 reg = <0x0 0x1550000 0x0 0x10000>,
150 <0x0 0x40000000 0x0 0x20000000>;
151 reg-names = "QuadSPI", "QuadSPI-memory";
152 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
153 clock-names = "qspi_en", "qspi";
154 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
155 status = "disabled";
156 };
157
158 esdhc: esdhc@1560000 {
159 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
160 reg = <0x0 0x1560000 0x0 0x10000>;
161 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
162 clock-frequency = <0>;
163 voltage-ranges = <1800 1800 3300 3300>;
164 sdhci,auto-cmd12;
165 big-endian;
166 bus-width = <4>;
167 status = "disabled";
168 };
169
170 sata: sata@3200000 {
171 compatible = "fsl,ls1021a-ahci";
172 reg = <0x0 0x3200000 0x0 0x10000>,
173 <0x0 0x20220520 0x0 0x4>;
174 reg-names = "ahci", "sata-ecc";
175 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clockgen 4 1>;
177 dma-coherent;
178 status = "disabled";
179 };
180
181 scfg: scfg@1570000 {
182 compatible = "fsl,ls1021a-scfg", "syscon";
183 reg = <0x0 0x1570000 0x0 0x10000>;
184 big-endian;
185 #address-cells = <1>;
186 #size-cells = <1>;
187 ranges = <0x0 0x0 0x1570000 0x10000>;
188
189 extirq: interrupt-controller@1ac {
190 compatible = "fsl,ls1021a-extirq";
191 #interrupt-cells = <2>;
192 #address-cells = <0>;
193 interrupt-controller;
194 reg = <0x1ac 4>;
195 interrupt-map =
196 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
197 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
198 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
199 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
200 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
201 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-map-mask = <0x7 0x0>;
203 };
204 };
205
206 crypto: crypto@1700000 {
207 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
208 fsl,sec-era = <7>;
209 #address-cells = <1>;
210 #size-cells = <1>;
211 reg = <0x0 0x1700000 0x0 0x100000>;
212 ranges = <0x0 0x0 0x1700000 0x100000>;
213 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
214 dma-coherent;
215
216 sec_jr0: jr@10000 {
217 compatible = "fsl,sec-v5.0-job-ring",
218 "fsl,sec-v4.0-job-ring";
219 reg = <0x10000 0x10000>;
220 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
221 };
222
223 sec_jr1: jr@20000 {
224 compatible = "fsl,sec-v5.0-job-ring",
225 "fsl,sec-v4.0-job-ring";
226 reg = <0x20000 0x10000>;
227 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
228 };
229
230 sec_jr2: jr@30000 {
231 compatible = "fsl,sec-v5.0-job-ring",
232 "fsl,sec-v4.0-job-ring";
233 reg = <0x30000 0x10000>;
234 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
235 };
236
237 sec_jr3: jr@40000 {
238 compatible = "fsl,sec-v5.0-job-ring",
239 "fsl,sec-v4.0-job-ring";
240 reg = <0x40000 0x10000>;
241 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
242 };
243
244 };
245
246 clockgen: clocking@1ee1000 {
247 compatible = "fsl,ls1021a-clockgen";
248 reg = <0x0 0x1ee1000 0x0 0x1000>;
249 #clock-cells = <2>;
250 clocks = <&sysclk>;
251 };
252
253 tmu: tmu@1f00000 {
254 compatible = "fsl,qoriq-tmu";
255 reg = <0x0 0x1f00000 0x0 0x10000>;
256 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
257 fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
258 fsl,tmu-calibration = <0x00000000 0x00000020>,
259 <0x00000001 0x00000024>,
260 <0x00000002 0x0000002a>,
261 <0x00000003 0x00000032>,
262 <0x00000004 0x00000038>,
263 <0x00000005 0x0000003e>,
264 <0x00000006 0x00000043>,
265 <0x00000007 0x0000004a>,
266 <0x00000008 0x00000050>,
267 <0x00000009 0x00000059>,
268 <0x0000000a 0x0000005f>,
269 <0x0000000b 0x00000066>,
270
271 <0x00010000 0x00000023>,
272 <0x00010001 0x0000002b>,
273 <0x00010002 0x00000033>,
274 <0x00010003 0x0000003a>,
275 <0x00010004 0x00000042>,
276 <0x00010005 0x0000004a>,
277 <0x00010006 0x00000054>,
278 <0x00010007 0x0000005c>,
279 <0x00010008 0x00000065>,
280 <0x00010009 0x0000006f>,
281
282 <0x00020000 0x00000029>,
283 <0x00020001 0x00000033>,
284 <0x00020002 0x0000003d>,
285 <0x00020003 0x00000048>,
286 <0x00020004 0x00000054>,
287 <0x00020005 0x00000060>,
288 <0x00020006 0x0000006c>,
289
290 <0x00030000 0x00000025>,
291 <0x00030001 0x00000033>,
292 <0x00030002 0x00000043>,
293 <0x00030003 0x00000055>;
294 #thermal-sensor-cells = <1>;
295 };
296
297 dspi0: spi@2100000 {
298 compatible = "fsl,ls1021a-v1.0-dspi";
299 #address-cells = <1>;
300 #size-cells = <0>;
301 reg = <0x0 0x2100000 0x0 0x10000>;
302 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
303 clock-names = "dspi";
304 clocks = <&clockgen 4 1>;
305 spi-num-chipselects = <6>;
306 big-endian;
307 status = "disabled";
308 };
309
310 dspi1: spi@2110000 {
311 compatible = "fsl,ls1021a-v1.0-dspi";
312 #address-cells = <1>;
313 #size-cells = <0>;
314 reg = <0x0 0x2110000 0x0 0x10000>;
315 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
316 clock-names = "dspi";
317 clocks = <&clockgen 4 1>;
318 spi-num-chipselects = <6>;
319 big-endian;
320 status = "disabled";
321 };
322
323 i2c0: i2c@2180000 {
324 compatible = "fsl,vf610-i2c";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 reg = <0x0 0x2180000 0x0 0x10000>;
328 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clockgen 4 1>;
330 dma-names = "rx", "tx";
331 dmas = <&edma0 1 38>, <&edma0 1 39>;
332 status = "disabled";
333 };
334
335 i2c1: i2c@2190000 {
336 compatible = "fsl,vf610-i2c";
337 #address-cells = <1>;
338 #size-cells = <0>;
339 reg = <0x0 0x2190000 0x0 0x10000>;
340 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clockgen 4 1>;
342 dma-names = "rx", "tx";
343 dmas = <&edma0 1 36>, <&edma0 1 37>;
344 status = "disabled";
345 };
346
347 i2c2: i2c@21a0000 {
348 compatible = "fsl,vf610-i2c";
349 #address-cells = <1>;
350 #size-cells = <0>;
351 reg = <0x0 0x21a0000 0x0 0x10000>;
352 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&clockgen 4 1>;
354 dma-names = "rx", "tx";
355 dmas = <&edma0 1 34>, <&edma0 1 35>;
356 status = "disabled";
357 };
358
359 uart0: serial@21c0500 {
360 compatible = "fsl,16550-FIFO64", "ns16550a";
361 reg = <0x0 0x21c0500 0x0 0x100>;
362 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
363 clock-frequency = <0>;
364 fifo-size = <15>;
365 status = "disabled";
366 };
367
368 uart1: serial@21c0600 {
369 compatible = "fsl,16550-FIFO64", "ns16550a";
370 reg = <0x0 0x21c0600 0x0 0x100>;
371 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
372 clock-frequency = <0>;
373 fifo-size = <15>;
374 status = "disabled";
375 };
376
377 uart2: serial@21d0500 {
378 compatible = "fsl,16550-FIFO64", "ns16550a";
379 reg = <0x0 0x21d0500 0x0 0x100>;
380 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
381 clock-frequency = <0>;
382 fifo-size = <15>;
383 status = "disabled";
384 };
385
386 uart3: serial@21d0600 {
387 compatible = "fsl,16550-FIFO64", "ns16550a";
388 reg = <0x0 0x21d0600 0x0 0x100>;
389 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
390 clock-frequency = <0>;
391 fifo-size = <15>;
392 status = "disabled";
393 };
394
395 counter0: counter@29d0000 {
396 compatible = "fsl,ftm-quaddec";
397 reg = <0x0 0x29d0000 0x0 0x10000>;
398 big-endian;
399 status = "disabled";
400 };
401
402 counter1: counter@29e0000 {
403 compatible = "fsl,ftm-quaddec";
404 reg = <0x0 0x29e0000 0x0 0x10000>;
405 big-endian;
406 status = "disabled";
407 };
408
409 counter2: counter@29f0000 {
410 compatible = "fsl,ftm-quaddec";
411 reg = <0x0 0x29f0000 0x0 0x10000>;
412 big-endian;
413 status = "disabled";
414 };
415
416 counter3: counter@2a00000 {
417 compatible = "fsl,ftm-quaddec";
418 reg = <0x0 0x2a00000 0x0 0x10000>;
419 big-endian;
420 status = "disabled";
421 };
422
423 gpio0: gpio@2300000 {
424 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
425 reg = <0x0 0x2300000 0x0 0x10000>;
426 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
427 gpio-controller;
428 #gpio-cells = <2>;
429 interrupt-controller;
430 #interrupt-cells = <2>;
431 };
432
433 gpio1: gpio@2310000 {
434 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
435 reg = <0x0 0x2310000 0x0 0x10000>;
436 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
437 gpio-controller;
438 #gpio-cells = <2>;
439 interrupt-controller;
440 #interrupt-cells = <2>;
441 };
442
443 gpio2: gpio@2320000 {
444 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
445 reg = <0x0 0x2320000 0x0 0x10000>;
446 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
447 gpio-controller;
448 #gpio-cells = <2>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
451 };
452
453 gpio3: gpio@2330000 {
454 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
455 reg = <0x0 0x2330000 0x0 0x10000>;
456 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 };
462
463 lpuart0: serial@2950000 {
464 compatible = "fsl,ls1021a-lpuart";
465 reg = <0x0 0x2950000 0x0 0x1000>;
466 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&sysclk>;
468 clock-names = "ipg";
469 status = "disabled";
470 };
471
472 lpuart1: serial@2960000 {
473 compatible = "fsl,ls1021a-lpuart";
474 reg = <0x0 0x2960000 0x0 0x1000>;
475 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&clockgen 4 1>;
477 clock-names = "ipg";
478 status = "disabled";
479 };
480
481 lpuart2: serial@2970000 {
482 compatible = "fsl,ls1021a-lpuart";
483 reg = <0x0 0x2970000 0x0 0x1000>;
484 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clockgen 4 1>;
486 clock-names = "ipg";
487 status = "disabled";
488 };
489
490 lpuart3: serial@2980000 {
491 compatible = "fsl,ls1021a-lpuart";
492 reg = <0x0 0x2980000 0x0 0x1000>;
493 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&clockgen 4 1>;
495 clock-names = "ipg";
496 status = "disabled";
497 };
498
499 lpuart4: serial@2990000 {
500 compatible = "fsl,ls1021a-lpuart";
501 reg = <0x0 0x2990000 0x0 0x1000>;
502 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clockgen 4 1>;
504 clock-names = "ipg";
505 status = "disabled";
506 };
507
508 lpuart5: serial@29a0000 {
509 compatible = "fsl,ls1021a-lpuart";
510 reg = <0x0 0x29a0000 0x0 0x1000>;
511 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clockgen 4 1>;
513 clock-names = "ipg";
514 status = "disabled";
515 };
516
517 pwm0: pwm@29d0000 {
518 compatible = "fsl,vf610-ftm-pwm";
519 #pwm-cells = <3>;
520 reg = <0x0 0x29d0000 0x0 0x10000>;
521 clock-names = "ftm_sys", "ftm_ext",
522 "ftm_fix", "ftm_cnt_clk_en";
523 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
524 <&clockgen 4 1>, <&clockgen 4 1>;
525 big-endian;
526 status = "disabled";
527 };
528
529 pwm1: pwm@29e0000 {
530 compatible = "fsl,vf610-ftm-pwm";
531 #pwm-cells = <3>;
532 reg = <0x0 0x29e0000 0x0 0x10000>;
533 clock-names = "ftm_sys", "ftm_ext",
534 "ftm_fix", "ftm_cnt_clk_en";
535 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
536 <&clockgen 4 1>, <&clockgen 4 1>;
537 big-endian;
538 status = "disabled";
539 };
540
541 pwm2: pwm@29f0000 {
542 compatible = "fsl,vf610-ftm-pwm";
543 #pwm-cells = <3>;
544 reg = <0x0 0x29f0000 0x0 0x10000>;
545 clock-names = "ftm_sys", "ftm_ext",
546 "ftm_fix", "ftm_cnt_clk_en";
547 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
548 <&clockgen 4 1>, <&clockgen 4 1>;
549 big-endian;
550 status = "disabled";
551 };
552
553 pwm3: pwm@2a00000 {
554 compatible = "fsl,vf610-ftm-pwm";
555 #pwm-cells = <3>;
556 reg = <0x0 0x2a00000 0x0 0x10000>;
557 clock-names = "ftm_sys", "ftm_ext",
558 "ftm_fix", "ftm_cnt_clk_en";
559 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
560 <&clockgen 4 1>, <&clockgen 4 1>;
561 big-endian;
562 status = "disabled";
563 };
564
565 pwm4: pwm@2a10000 {
566 compatible = "fsl,vf610-ftm-pwm";
567 #pwm-cells = <3>;
568 reg = <0x0 0x2a10000 0x0 0x10000>;
569 clock-names = "ftm_sys", "ftm_ext",
570 "ftm_fix", "ftm_cnt_clk_en";
571 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
572 <&clockgen 4 1>, <&clockgen 4 1>;
573 big-endian;
574 status = "disabled";
575 };
576
577 pwm5: pwm@2a20000 {
578 compatible = "fsl,vf610-ftm-pwm";
579 #pwm-cells = <3>;
580 reg = <0x0 0x2a20000 0x0 0x10000>;
581 clock-names = "ftm_sys", "ftm_ext",
582 "ftm_fix", "ftm_cnt_clk_en";
583 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
584 <&clockgen 4 1>, <&clockgen 4 1>;
585 big-endian;
586 status = "disabled";
587 };
588
589 pwm6: pwm@2a30000 {
590 compatible = "fsl,vf610-ftm-pwm";
591 #pwm-cells = <3>;
592 reg = <0x0 0x2a30000 0x0 0x10000>;
593 clock-names = "ftm_sys", "ftm_ext",
594 "ftm_fix", "ftm_cnt_clk_en";
595 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
596 <&clockgen 4 1>, <&clockgen 4 1>;
597 big-endian;
598 status = "disabled";
599 };
600
601 pwm7: pwm@2a40000 {
602 compatible = "fsl,vf610-ftm-pwm";
603 #pwm-cells = <3>;
604 reg = <0x0 0x2a40000 0x0 0x10000>;
605 clock-names = "ftm_sys", "ftm_ext",
606 "ftm_fix", "ftm_cnt_clk_en";
607 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
608 <&clockgen 4 1>, <&clockgen 4 1>;
609 big-endian;
610 status = "disabled";
611 };
612
613 wdog0: watchdog@2ad0000 {
614 compatible = "fsl,imx21-wdt";
615 reg = <0x0 0x2ad0000 0x0 0x10000>;
616 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&clockgen 4 1>;
618 clock-names = "wdog-en";
619 big-endian;
620 };
621
622 sai1: sai@2b50000 {
623 #sound-dai-cells = <0>;
624 compatible = "fsl,vf610-sai";
625 reg = <0x0 0x2b50000 0x0 0x10000>;
626 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
628 <&clockgen 4 1>, <&clockgen 4 1>;
629 clock-names = "bus", "mclk1", "mclk2", "mclk3";
630 dma-names = "tx", "rx";
631 dmas = <&edma0 1 47>,
632 <&edma0 1 46>;
633 status = "disabled";
634 };
635
636 sai2: sai@2b60000 {
637 #sound-dai-cells = <0>;
638 compatible = "fsl,vf610-sai";
639 reg = <0x0 0x2b60000 0x0 0x10000>;
640 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
642 <&clockgen 4 1>, <&clockgen 4 1>;
643 clock-names = "bus", "mclk1", "mclk2", "mclk3";
644 dma-names = "tx", "rx";
645 dmas = <&edma0 1 45>,
646 <&edma0 1 44>;
647 status = "disabled";
648 };
649
650 edma0: dma-controller@2c00000 {
651 #dma-cells = <2>;
652 compatible = "fsl,vf610-edma";
653 reg = <0x0 0x2c00000 0x0 0x10000>,
654 <0x0 0x2c10000 0x0 0x10000>,
655 <0x0 0x2c20000 0x0 0x10000>;
656 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
658 interrupt-names = "edma-tx", "edma-err";
659 dma-channels = <32>;
660 big-endian;
661 clock-names = "dmamux0", "dmamux1";
662 clocks = <&clockgen 4 1>,
663 <&clockgen 4 1>;
664 };
665
666 dcu: dcu@2ce0000 {
667 compatible = "fsl,ls1021a-dcu";
668 reg = <0x0 0x2ce0000 0x0 0x10000>;
669 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clockgen 4 0>,
671 <&clockgen 4 0>;
672 clock-names = "dcu", "pix";
673 big-endian;
674 status = "disabled";
675 };
676
677 mdio0: mdio@2d24000 {
678 compatible = "gianfar";
679 device_type = "mdio";
680 #address-cells = <1>;
681 #size-cells = <0>;
682 reg = <0x0 0x2d24000 0x0 0x4000>,
683 <0x0 0x2d10030 0x0 0x4>;
684 };
685
686 mdio1: mdio@2d64000 {
687 compatible = "gianfar";
688 device_type = "mdio";
689 #address-cells = <1>;
690 #size-cells = <0>;
691 reg = <0x0 0x2d64000 0x0 0x4000>,
692 <0x0 0x2d50030 0x0 0x4>;
693 };
694
695 ptp_clock@2d10e00 {
696 compatible = "fsl,etsec-ptp";
697 reg = <0x0 0x2d10e00 0x0 0xb0>;
698 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
699 fsl,tclk-period = <5>;
700 fsl,tmr-prsc = <2>;
701 fsl,tmr-add = <0xaaaaaaab>;
702 fsl,tmr-fiper1 = <999999995>;
703 fsl,tmr-fiper2 = <999999995>;
704 fsl,max-adj = <499999999>;
705 fsl,extts-fifo;
706 };
707
708 enet0: ethernet@2d10000 {
709 compatible = "fsl,etsec2";
710 device_type = "network";
711 #address-cells = <2>;
712 #size-cells = <2>;
713 interrupt-parent = <&gic>;
714 model = "eTSEC";
715 fsl,magic-packet;
716 ranges;
717 dma-coherent;
718
719 queue-group@2d10000 {
720 #address-cells = <2>;
721 #size-cells = <2>;
722 reg = <0x0 0x2d10000 0x0 0x1000>;
723 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
726 };
727
728 queue-group@2d14000 {
729 #address-cells = <2>;
730 #size-cells = <2>;
731 reg = <0x0 0x2d14000 0x0 0x1000>;
732 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
735 };
736 };
737
738 enet1: ethernet@2d50000 {
739 compatible = "fsl,etsec2";
740 device_type = "network";
741 #address-cells = <2>;
742 #size-cells = <2>;
743 interrupt-parent = <&gic>;
744 model = "eTSEC";
745 ranges;
746 dma-coherent;
747
748 queue-group@2d50000 {
749 #address-cells = <2>;
750 #size-cells = <2>;
751 reg = <0x0 0x2d50000 0x0 0x1000>;
752 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
755 };
756
757 queue-group@2d54000 {
758 #address-cells = <2>;
759 #size-cells = <2>;
760 reg = <0x0 0x2d54000 0x0 0x1000>;
761 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
764 };
765 };
766
767 enet2: ethernet@2d90000 {
768 compatible = "fsl,etsec2";
769 device_type = "network";
770 #address-cells = <2>;
771 #size-cells = <2>;
772 interrupt-parent = <&gic>;
773 model = "eTSEC";
774 ranges;
775 dma-coherent;
776
777 queue-group@2d90000 {
778 #address-cells = <2>;
779 #size-cells = <2>;
780 reg = <0x0 0x2d90000 0x0 0x1000>;
781 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
784 };
785
786 queue-group@2d94000 {
787 #address-cells = <2>;
788 #size-cells = <2>;
789 reg = <0x0 0x2d94000 0x0 0x1000>;
790 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
793 };
794 };
795
796 usb2: usb@8600000 {
797 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
798 reg = <0x0 0x8600000 0x0 0x1000>;
799 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
800 dr_mode = "host";
801 phy_type = "ulpi";
802 };
803
804 usb3: usb@3100000 {
805 compatible = "snps,dwc3";
806 reg = <0x0 0x3100000 0x0 0x10000>;
807 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
808 dr_mode = "host";
809 snps,quirk-frame-length-adjustment = <0x20>;
810 snps,dis_rxdet_inp3_quirk;
811 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
812 };
813
814 pcie@3400000 {
815 compatible = "fsl,ls1021a-pcie";
816 reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */
817 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
818 reg-names = "regs", "config";
819 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
820 fsl,pcie-scfg = <&scfg 0>;
821 #address-cells = <3>;
822 #size-cells = <2>;
823 device_type = "pci";
824 num-viewport = <6>;
825 bus-range = <0x0 0xff>;
826 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */
827 <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
828 msi-parent = <&msi1>, <&msi2>;
829 #interrupt-cells = <1>;
830 interrupt-map-mask = <0 0 0 7>;
831 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
832 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
833 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
834 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
835 status = "disabled";
836 };
837
838 pcie@3500000 {
839 compatible = "fsl,ls1021a-pcie";
840 reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */
841 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
842 reg-names = "regs", "config";
843 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
844 fsl,pcie-scfg = <&scfg 1>;
845 #address-cells = <3>;
846 #size-cells = <2>;
847 device_type = "pci";
848 num-viewport = <6>;
849 bus-range = <0x0 0xff>;
850 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */
851 <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
852 msi-parent = <&msi1>, <&msi2>;
853 #interrupt-cells = <1>;
854 interrupt-map-mask = <0 0 0 7>;
855 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
856 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
857 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
858 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
859 status = "disabled";
860 };
861
862 can0: can@2a70000 {
863 compatible = "fsl,ls1021ar2-flexcan";
864 reg = <0x0 0x2a70000 0x0 0x1000>;
865 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
867 clock-names = "ipg", "per";
868 big-endian;
869 };
870
871 can1: can@2a80000 {
872 compatible = "fsl,ls1021ar2-flexcan";
873 reg = <0x0 0x2a80000 0x0 0x1000>;
874 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
876 clock-names = "ipg", "per";
877 big-endian;
878 };
879
880 can2: can@2a90000 {
881 compatible = "fsl,ls1021ar2-flexcan";
882 reg = <0x0 0x2a90000 0x0 0x1000>;
883 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
885 clock-names = "ipg", "per";
886 big-endian;
887 };
888
889 can3: can@2aa0000 {
890 compatible = "fsl,ls1021ar2-flexcan";
891 reg = <0x0 0x2aa0000 0x0 0x1000>;
892 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
894 clock-names = "ipg", "per";
895 big-endian;
896 };
897
898 ocram1: sram@10000000 {
899 compatible = "mmio-sram";
900 reg = <0x0 0x10000000 0x0 0x10000>;
901 #address-cells = <1>;
902 #size-cells = <1>;
903 ranges = <0x0 0x0 0x10000000 0x10000>;
904 };
905
906 ocram2: sram@10010000 {
907 compatible = "mmio-sram";
908 reg = <0x0 0x10010000 0x0 0x10000>;
909 #address-cells = <1>;
910 #size-cells = <1>;
911 ranges = <0x0 0x0 0x10010000 0x10000>;
912 };
913
914 qdma: dma-controller@8390000 {
915 compatible = "fsl,ls1021a-qdma";
916 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
917 <0x0 0x8389000 0x0 0x1000>, /* Status regs */
918 <0x0 0x838a000 0x0 0x2000>; /* Block regs */
919 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
922 interrupt-names = "qdma-error",
923 "qdma-queue0", "qdma-queue1";
924 #dma-cells = <2>;
925 dma-channels = <8>;
926 block-number = <1>;
927 block-offset = <0x1000>;
928 fsl,dma-queues = <2>;
929 status-sizes = <64>;
930 queue-sizes = <64 64>;
931 big-endian;
932 };
933
934 rcpm: power-controller@1ee2140 {
935 compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
936 reg = <0x0 0x1ee2140 0x0 0x8>;
937 #fsl,rcpm-wakeup-cells = <2>;
938 #power-domain-cells = <0>;
939 };
940
941 ftm_alarm0: timer0@29d0000 {
942 compatible = "fsl,ls1021a-ftm-alarm";
943 reg = <0x0 0x29d0000 0x0 0x10000>;
944 reg-names = "ftm";
945 fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
946 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
947 big-endian;
948 };
949 };
950
951 thermal-zones {
952 cpu_thermal: cpu-thermal {
953 polling-delay-passive = <1000>;
954 polling-delay = <5000>;
955
956 thermal-sensors = <&tmu 0>;
957
958 trips {
959 cpu_alert: cpu-alert {
960 temperature = <85000>;
961 hysteresis = <2000>;
962 type = "passive";
963 };
964 cpu_crit: cpu-crit {
965 temperature = <95000>;
966 hysteresis = <2000>;
967 type = "critical";
968 };
969 };
970
971 cooling-maps {
972 map0 {
973 trip = <&cpu_alert>;
974 cooling-device =
975 <&cpu0 THERMAL_NO_LIMIT
976 THERMAL_NO_LIMIT>,
977 <&cpu1 THERMAL_NO_LIMIT
978 THERMAL_NO_LIMIT>;
979 };
980 };
981 };
982 };
983};
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "skeleton64.dtsi"
49#include <dt-bindings/interrupt-controller/arm-gic.h>
50
51/ {
52 compatible = "fsl,ls1021a";
53 interrupt-parent = <&gic>;
54
55 aliases {
56 crypto = &crypto;
57 ethernet0 = &enet0;
58 ethernet1 = &enet1;
59 ethernet2 = &enet2;
60 serial0 = &lpuart0;
61 serial1 = &lpuart1;
62 serial2 = &lpuart2;
63 serial3 = &lpuart3;
64 serial4 = &lpuart4;
65 serial5 = &lpuart5;
66 sysclk = &sysclk;
67 };
68
69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 cpu@f00 {
74 compatible = "arm,cortex-a7";
75 device_type = "cpu";
76 reg = <0xf00>;
77 clocks = <&cluster1_clk>;
78 };
79
80 cpu@f01 {
81 compatible = "arm,cortex-a7";
82 device_type = "cpu";
83 reg = <0xf01>;
84 clocks = <&cluster1_clk>;
85 };
86 };
87
88 timer {
89 compatible = "arm,armv7-timer";
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
94 };
95
96 pmu {
97 compatible = "arm,cortex-a7-pmu";
98 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
100 };
101
102 soc {
103 compatible = "simple-bus";
104 #address-cells = <2>;
105 #size-cells = <2>;
106 device_type = "soc";
107 interrupt-parent = <&gic>;
108 ranges;
109
110 gic: interrupt-controller@1400000 {
111 compatible = "arm,cortex-a7-gic";
112 #interrupt-cells = <3>;
113 interrupt-controller;
114 reg = <0x0 0x1401000 0x0 0x1000>,
115 <0x0 0x1402000 0x0 0x1000>,
116 <0x0 0x1404000 0x0 0x2000>,
117 <0x0 0x1406000 0x0 0x2000>;
118 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
119
120 };
121
122 ifc: ifc@1530000 {
123 compatible = "fsl,ifc", "simple-bus";
124 reg = <0x0 0x1530000 0x0 0x10000>;
125 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
126 };
127
128 dcfg: dcfg@1ee0000 {
129 compatible = "fsl,ls1021a-dcfg", "syscon";
130 reg = <0x0 0x1ee0000 0x0 0x10000>;
131 big-endian;
132 };
133
134 esdhc: esdhc@1560000 {
135 compatible = "fsl,esdhc";
136 reg = <0x0 0x1560000 0x0 0x10000>;
137 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
138 clock-frequency = <0>;
139 voltage-ranges = <1800 1800 3300 3300>;
140 sdhci,auto-cmd12;
141 big-endian;
142 bus-width = <4>;
143 status = "disabled";
144 };
145
146 sata: sata@3200000 {
147 compatible = "fsl,ls1021a-ahci";
148 reg = <0x0 0x3200000 0x0 0x10000>,
149 <0x0 0x20220520 0x0 0x4>;
150 reg-names = "ahci", "sata-ecc";
151 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&platform_clk 1>;
153 dma-coherent;
154 status = "disabled";
155 };
156
157 scfg: scfg@1570000 {
158 compatible = "fsl,ls1021a-scfg", "syscon";
159 reg = <0x0 0x1570000 0x0 0x10000>;
160 big-endian;
161 };
162
163 crypto: crypto@1700000 {
164 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
165 fsl,sec-era = <7>;
166 #address-cells = <1>;
167 #size-cells = <1>;
168 reg = <0x0 0x1700000 0x0 0x100000>;
169 ranges = <0x0 0x0 0x1700000 0x100000>;
170 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
171
172 sec_jr0: jr@10000 {
173 compatible = "fsl,sec-v5.0-job-ring",
174 "fsl,sec-v4.0-job-ring";
175 reg = <0x10000 0x10000>;
176 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
177 };
178
179 sec_jr1: jr@20000 {
180 compatible = "fsl,sec-v5.0-job-ring",
181 "fsl,sec-v4.0-job-ring";
182 reg = <0x20000 0x10000>;
183 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
184 };
185
186 sec_jr2: jr@30000 {
187 compatible = "fsl,sec-v5.0-job-ring",
188 "fsl,sec-v4.0-job-ring";
189 reg = <0x30000 0x10000>;
190 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
191 };
192
193 sec_jr3: jr@40000 {
194 compatible = "fsl,sec-v5.0-job-ring",
195 "fsl,sec-v4.0-job-ring";
196 reg = <0x40000 0x10000>;
197 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
198 };
199
200 };
201
202 clockgen: clocking@1ee1000 {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 ranges = <0x0 0x0 0x1ee1000 0x10000>;
206
207 sysclk: sysclk {
208 compatible = "fixed-clock";
209 #clock-cells = <0>;
210 clock-output-names = "sysclk";
211 };
212
213 cga_pll1: pll@800 {
214 compatible = "fsl,qoriq-core-pll-2.0";
215 #clock-cells = <1>;
216 reg = <0x800 0x10>;
217 clocks = <&sysclk>;
218 clock-output-names = "cga-pll1", "cga-pll1-div2",
219 "cga-pll1-div4";
220 };
221
222 platform_clk: pll@c00 {
223 compatible = "fsl,qoriq-core-pll-2.0";
224 #clock-cells = <1>;
225 reg = <0xc00 0x10>;
226 clocks = <&sysclk>;
227 clock-output-names = "platform-clk", "platform-clk-div2";
228 };
229
230 cluster1_clk: clk0c0@0 {
231 compatible = "fsl,qoriq-core-mux-2.0";
232 #clock-cells = <0>;
233 reg = <0x0 0x10>;
234 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
235 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
236 clock-output-names = "cluster1-clk";
237 };
238 };
239
240 dspi0: dspi@2100000 {
241 compatible = "fsl,ls1021a-v1.0-dspi";
242 #address-cells = <1>;
243 #size-cells = <0>;
244 reg = <0x0 0x2100000 0x0 0x10000>;
245 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
246 clock-names = "dspi";
247 clocks = <&platform_clk 1>;
248 spi-num-chipselects = <5>;
249 big-endian;
250 status = "disabled";
251 };
252
253 dspi1: dspi@2110000 {
254 compatible = "fsl,ls1021a-v1.0-dspi";
255 #address-cells = <1>;
256 #size-cells = <0>;
257 reg = <0x0 0x2110000 0x0 0x10000>;
258 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
259 clock-names = "dspi";
260 clocks = <&platform_clk 1>;
261 spi-num-chipselects = <5>;
262 big-endian;
263 status = "disabled";
264 };
265
266 i2c0: i2c@2180000 {
267 compatible = "fsl,vf610-i2c";
268 #address-cells = <1>;
269 #size-cells = <0>;
270 reg = <0x0 0x2180000 0x0 0x10000>;
271 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
272 clock-names = "i2c";
273 clocks = <&platform_clk 1>;
274 status = "disabled";
275 };
276
277 i2c1: i2c@2190000 {
278 compatible = "fsl,vf610-i2c";
279 #address-cells = <1>;
280 #size-cells = <0>;
281 reg = <0x0 0x2190000 0x0 0x10000>;
282 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
283 clock-names = "i2c";
284 clocks = <&platform_clk 1>;
285 status = "disabled";
286 };
287
288 i2c2: i2c@21a0000 {
289 compatible = "fsl,vf610-i2c";
290 #address-cells = <1>;
291 #size-cells = <0>;
292 reg = <0x0 0x21a0000 0x0 0x10000>;
293 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
294 clock-names = "i2c";
295 clocks = <&platform_clk 1>;
296 status = "disabled";
297 };
298
299 uart0: serial@21c0500 {
300 compatible = "fsl,16550-FIFO64", "ns16550a";
301 reg = <0x0 0x21c0500 0x0 0x100>;
302 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
303 clock-frequency = <0>;
304 fifo-size = <15>;
305 status = "disabled";
306 };
307
308 uart1: serial@21c0600 {
309 compatible = "fsl,16550-FIFO64", "ns16550a";
310 reg = <0x0 0x21c0600 0x0 0x100>;
311 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
312 clock-frequency = <0>;
313 fifo-size = <15>;
314 status = "disabled";
315 };
316
317 uart2: serial@21d0500 {
318 compatible = "fsl,16550-FIFO64", "ns16550a";
319 reg = <0x0 0x21d0500 0x0 0x100>;
320 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
321 clock-frequency = <0>;
322 fifo-size = <15>;
323 status = "disabled";
324 };
325
326 uart3: serial@21d0600 {
327 compatible = "fsl,16550-FIFO64", "ns16550a";
328 reg = <0x0 0x21d0600 0x0 0x100>;
329 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
330 clock-frequency = <0>;
331 fifo-size = <15>;
332 status = "disabled";
333 };
334
335 lpuart0: serial@2950000 {
336 compatible = "fsl,ls1021a-lpuart";
337 reg = <0x0 0x2950000 0x0 0x1000>;
338 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&sysclk>;
340 clock-names = "ipg";
341 status = "disabled";
342 };
343
344 lpuart1: serial@2960000 {
345 compatible = "fsl,ls1021a-lpuart";
346 reg = <0x0 0x2960000 0x0 0x1000>;
347 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&platform_clk 1>;
349 clock-names = "ipg";
350 status = "disabled";
351 };
352
353 lpuart2: serial@2970000 {
354 compatible = "fsl,ls1021a-lpuart";
355 reg = <0x0 0x2970000 0x0 0x1000>;
356 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&platform_clk 1>;
358 clock-names = "ipg";
359 status = "disabled";
360 };
361
362 lpuart3: serial@2980000 {
363 compatible = "fsl,ls1021a-lpuart";
364 reg = <0x0 0x2980000 0x0 0x1000>;
365 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&platform_clk 1>;
367 clock-names = "ipg";
368 status = "disabled";
369 };
370
371 lpuart4: serial@2990000 {
372 compatible = "fsl,ls1021a-lpuart";
373 reg = <0x0 0x2990000 0x0 0x1000>;
374 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&platform_clk 1>;
376 clock-names = "ipg";
377 status = "disabled";
378 };
379
380 lpuart5: serial@29a0000 {
381 compatible = "fsl,ls1021a-lpuart";
382 reg = <0x0 0x29a0000 0x0 0x1000>;
383 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&platform_clk 1>;
385 clock-names = "ipg";
386 status = "disabled";
387 };
388
389 wdog0: watchdog@2ad0000 {
390 compatible = "fsl,imx21-wdt";
391 reg = <0x0 0x2ad0000 0x0 0x10000>;
392 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&platform_clk 1>;
394 clock-names = "wdog-en";
395 big-endian;
396 };
397
398 sai1: sai@2b50000 {
399 #sound-dai-cells = <0>;
400 compatible = "fsl,vf610-sai";
401 reg = <0x0 0x2b50000 0x0 0x10000>;
402 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&platform_clk 1>, <&platform_clk 1>,
404 <&platform_clk 1>, <&platform_clk 1>;
405 clock-names = "bus", "mclk1", "mclk2", "mclk3";
406 dma-names = "tx", "rx";
407 dmas = <&edma0 1 47>,
408 <&edma0 1 46>;
409 status = "disabled";
410 };
411
412 sai2: sai@2b60000 {
413 #sound-dai-cells = <0>;
414 compatible = "fsl,vf610-sai";
415 reg = <0x0 0x2b60000 0x0 0x10000>;
416 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&platform_clk 1>, <&platform_clk 1>,
418 <&platform_clk 1>, <&platform_clk 1>;
419 clock-names = "bus", "mclk1", "mclk2", "mclk3";
420 dma-names = "tx", "rx";
421 dmas = <&edma0 1 45>,
422 <&edma0 1 44>;
423 status = "disabled";
424 };
425
426 edma0: edma@2c00000 {
427 #dma-cells = <2>;
428 compatible = "fsl,vf610-edma";
429 reg = <0x0 0x2c00000 0x0 0x10000>,
430 <0x0 0x2c10000 0x0 0x10000>,
431 <0x0 0x2c20000 0x0 0x10000>;
432 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
434 interrupt-names = "edma-tx", "edma-err";
435 dma-channels = <32>;
436 big-endian;
437 clock-names = "dmamux0", "dmamux1";
438 clocks = <&platform_clk 1>,
439 <&platform_clk 1>;
440 };
441
442 dcu: dcu@2ce0000 {
443 compatible = "fsl,ls1021a-dcu";
444 reg = <0x0 0x2ce0000 0x0 0x10000>;
445 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&platform_clk 0>;
447 clock-names = "dcu";
448 big-endian;
449 status = "disabled";
450 };
451
452 mdio0: mdio@2d24000 {
453 compatible = "gianfar";
454 device_type = "mdio";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 reg = <0x0 0x2d24000 0x0 0x4000>;
458 };
459
460 ptp_clock@2d10e00 {
461 compatible = "fsl,etsec-ptp";
462 reg = <0x0 0x2d10e00 0x0 0xb0>;
463 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
464 fsl,tclk-period = <5>;
465 fsl,tmr-prsc = <2>;
466 fsl,tmr-add = <0xaaaaaaab>;
467 fsl,tmr-fiper1 = <999999990>;
468 fsl,tmr-fiper2 = <99990>;
469 fsl,max-adj = <499999999>;
470 };
471
472 enet0: ethernet@2d10000 {
473 compatible = "fsl,etsec2";
474 device_type = "network";
475 #address-cells = <2>;
476 #size-cells = <2>;
477 interrupt-parent = <&gic>;
478 model = "eTSEC";
479 fsl,magic-packet;
480 ranges;
481 dma-coherent;
482
483 queue-group@2d10000 {
484 #address-cells = <2>;
485 #size-cells = <2>;
486 reg = <0x0 0x2d10000 0x0 0x1000>;
487 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
490 };
491
492 queue-group@2d14000 {
493 #address-cells = <2>;
494 #size-cells = <2>;
495 reg = <0x0 0x2d14000 0x0 0x1000>;
496 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
499 };
500 };
501
502 enet1: ethernet@2d50000 {
503 compatible = "fsl,etsec2";
504 device_type = "network";
505 #address-cells = <2>;
506 #size-cells = <2>;
507 interrupt-parent = <&gic>;
508 model = "eTSEC";
509 ranges;
510 dma-coherent;
511
512 queue-group@2d50000 {
513 #address-cells = <2>;
514 #size-cells = <2>;
515 reg = <0x0 0x2d50000 0x0 0x1000>;
516 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
519 };
520
521 queue-group@2d54000 {
522 #address-cells = <2>;
523 #size-cells = <2>;
524 reg = <0x0 0x2d54000 0x0 0x1000>;
525 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
528 };
529 };
530
531 enet2: ethernet@2d90000 {
532 compatible = "fsl,etsec2";
533 device_type = "network";
534 #address-cells = <2>;
535 #size-cells = <2>;
536 interrupt-parent = <&gic>;
537 model = "eTSEC";
538 ranges;
539 dma-coherent;
540
541 queue-group@2d90000 {
542 #address-cells = <2>;
543 #size-cells = <2>;
544 reg = <0x0 0x2d90000 0x0 0x1000>;
545 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
548 };
549
550 queue-group@2d94000 {
551 #address-cells = <2>;
552 #size-cells = <2>;
553 reg = <0x0 0x2d94000 0x0 0x1000>;
554 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
557 };
558 };
559
560 usb@8600000 {
561 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
562 reg = <0x0 0x8600000 0x0 0x1000>;
563 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
564 dr_mode = "host";
565 phy_type = "ulpi";
566 };
567
568 usb3@3100000 {
569 compatible = "snps,dwc3";
570 reg = <0x0 0x3100000 0x0 0x10000>;
571 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
572 dr_mode = "host";
573 snps,quirk-frame-length-adjustment = <0x20>;
574 };
575
576 pcie@3400000 {
577 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
578 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
579 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
580 reg-names = "regs", "config";
581 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
582 fsl,pcie-scfg = <&scfg 0>;
583 #address-cells = <3>;
584 #size-cells = <2>;
585 device_type = "pci";
586 num-lanes = <4>;
587 bus-range = <0x0 0xff>;
588 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
589 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
590 #interrupt-cells = <1>;
591 interrupt-map-mask = <0 0 0 7>;
592 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
593 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
594 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
595 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
596 };
597
598 pcie@3500000 {
599 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
600 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
601 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
602 reg-names = "regs", "config";
603 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
604 fsl,pcie-scfg = <&scfg 1>;
605 #address-cells = <3>;
606 #size-cells = <2>;
607 device_type = "pci";
608 num-lanes = <4>;
609 bus-range = <0x0 0xff>;
610 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
611 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
612 #interrupt-cells = <1>;
613 interrupt-map-mask = <0 0 0 7>;
614 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
615 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
616 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
617 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
618 };
619 };
620};