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1/*
2 * Copyright 2013-2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 lamarr SoC clock nodes
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11clocks {
12 armpllclk: armpllclk@2620370 {
13 #clock-cells = <0>;
14 compatible = "ti,keystone,pll-clock";
15 clocks = <&refclksys>;
16 clock-output-names = "arm-pll-clk";
17 reg = <0x02620370 4>;
18 reg-names = "control";
19 };
20
21 mainpllclk: mainpllclk@2310110 {
22 #clock-cells = <0>;
23 compatible = "ti,keystone,main-pll-clock";
24 clocks = <&refclksys>;
25 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
26 reg-names = "control", "multiplier", "post-divider";
27 };
28
29 papllclk: papllclk@2620358 {
30 #clock-cells = <0>;
31 compatible = "ti,keystone,pll-clock";
32 clocks = <&refclksys>;
33 clock-output-names = "papllclk";
34 reg = <0x02620358 4>;
35 reg-names = "control";
36 };
37
38 ddr3apllclk: ddr3apllclk@2620360 {
39 #clock-cells = <0>;
40 compatible = "ti,keystone,pll-clock";
41 clocks = <&refclksys>;
42 clock-output-names = "ddr-3a-pll-clk";
43 reg = <0x02620360 4>;
44 reg-names = "control";
45 };
46
47 clkdfeiqnsys: clkdfeiqnsys {
48 #clock-cells = <0>;
49 compatible = "ti,keystone,psc-clock";
50 clocks = <&chipclk12>;
51 clock-output-names = "dfe";
52 reg-names = "control", "domain";
53 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
54 domain-id = <0>;
55 };
56
57 clkpcie1: clkpcie1 {
58 #clock-cells = <0>;
59 compatible = "ti,keystone,psc-clock";
60 clocks = <&chipclk12>;
61 clock-output-names = "pcie";
62 reg = <0x0235002c 0xb00>, <0x02350000 0x400>;
63 reg-names = "control", "domain";
64 domain-id = <4>;
65 };
66
67 clkgem1: clkgem1 {
68 #clock-cells = <0>;
69 compatible = "ti,keystone,psc-clock";
70 clocks = <&chipclk1>;
71 clock-output-names = "gem1";
72 reg = <0x02350040 0xb00>, <0x02350024 0x400>;
73 reg-names = "control", "domain";
74 domain-id = <9>;
75 };
76
77 clkgem2: clkgem2 {
78 #clock-cells = <0>;
79 compatible = "ti,keystone,psc-clock";
80 clocks = <&chipclk1>;
81 clock-output-names = "gem2";
82 reg = <0x02350044 0xb00>, <0x02350028 0x400>;
83 reg-names = "control", "domain";
84 domain-id = <10>;
85 };
86
87 clkgem3: clkgem3 {
88 #clock-cells = <0>;
89 compatible = "ti,keystone,psc-clock";
90 clocks = <&chipclk1>;
91 clock-output-names = "gem3";
92 reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
93 reg-names = "control", "domain";
94 domain-id = <11>;
95 };
96
97 clktac: clktac {
98 #clock-cells = <0>;
99 compatible = "ti,keystone,psc-clock";
100 clocks = <&chipclk13>;
101 clock-output-names = "tac";
102 reg = <0x02350064 0xb00>, <0x02350044 0x400>;
103 reg-names = "control", "domain";
104 domain-id = <17>;
105 };
106
107 clkrac: clkrac {
108 #clock-cells = <0>;
109 compatible = "ti,keystone,psc-clock";
110 clocks = <&chipclk13>;
111 clock-output-names = "rac";
112 reg = <0x02350068 0xb00>, <0x02350044 0x400>;
113 reg-names = "control", "domain";
114 domain-id = <17>;
115 };
116
117 clkdfepd0: clkdfepd0 {
118 #clock-cells = <0>;
119 compatible = "ti,keystone,psc-clock";
120 clocks = <&chipclk13>;
121 clock-output-names = "dfe-pd0";
122 reg = <0x0235006c 0xb00>, <0x02350044 0x400>;
123 reg-names = "control", "domain";
124 domain-id = <18>;
125 };
126
127 clkfftc0: clkfftc0 {
128 #clock-cells = <0>;
129 compatible = "ti,keystone,psc-clock";
130 clocks = <&chipclk13>;
131 clock-output-names = "fftc-0";
132 reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
133 reg-names = "control", "domain";
134 domain-id = <19>;
135 };
136
137 clkosr: clkosr {
138 #clock-cells = <0>;
139 compatible = "ti,keystone,psc-clock";
140 clocks = <&chipclk13>;
141 clock-output-names = "osr";
142 reg = <0x02350088 0xb00>, <0x0235004c 0x400>;
143 reg-names = "control", "domain";
144 domain-id = <21>;
145 };
146
147 clktcp3d0: clktcp3d0 {
148 #clock-cells = <0>;
149 compatible = "ti,keystone,psc-clock";
150 clocks = <&chipclk13>;
151 clock-output-names = "tcp3d-0";
152 reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
153 reg-names = "control", "domain";
154 domain-id = <22>;
155 };
156
157 clktcp3d1: clktcp3d1 {
158 #clock-cells = <0>;
159 compatible = "ti,keystone,psc-clock";
160 clocks = <&chipclk13>;
161 clock-output-names = "tcp3d-1";
162 reg = <0x02350094 0xb00>, <0x02350058 0x400>;
163 reg-names = "control", "domain";
164 domain-id = <23>;
165 };
166
167 clkvcp0: clkvcp0 {
168 #clock-cells = <0>;
169 compatible = "ti,keystone,psc-clock";
170 clocks = <&chipclk13>;
171 clock-output-names = "vcp-0";
172 reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
173 reg-names = "control", "domain";
174 domain-id = <24>;
175 };
176
177 clkvcp1: clkvcp1 {
178 #clock-cells = <0>;
179 compatible = "ti,keystone,psc-clock";
180 clocks = <&chipclk13>;
181 clock-output-names = "vcp-1";
182 reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
183 reg-names = "control", "domain";
184 domain-id = <24>;
185 };
186
187 clkvcp2: clkvcp2 {
188 #clock-cells = <0>;
189 compatible = "ti,keystone,psc-clock";
190 clocks = <&chipclk13>;
191 clock-output-names = "vcp-2";
192 reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
193 reg-names = "control", "domain";
194 domain-id = <24>;
195 };
196
197 clkvcp3: clkvcp3 {
198 #clock-cells = <0>;
199 compatible = "ti,keystone,psc-clock";
200 clocks = <&chipclk13>;
201 clock-output-names = "vcp-3";
202 reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
203 reg-names = "control", "domain";
204 domain-id = <24>;
205 };
206
207 clkbcp: clkbcp {
208 #clock-cells = <0>;
209 compatible = "ti,keystone,psc-clock";
210 clocks = <&chipclk13>;
211 clock-output-names = "bcp";
212 reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
213 reg-names = "control", "domain";
214 domain-id = <26>;
215 };
216
217 clkdfepd1: clkdfepd1 {
218 #clock-cells = <0>;
219 compatible = "ti,keystone,psc-clock";
220 clocks = <&chipclk13>;
221 clock-output-names = "dfe-pd1";
222 reg = <0x023500c0 0xb00>, <0x02350044 0x400>;
223 reg-names = "control", "domain";
224 domain-id = <27>;
225 };
226
227 clkfftc1: clkfftc1 {
228 #clock-cells = <0>;
229 compatible = "ti,keystone,psc-clock";
230 clocks = <&chipclk13>;
231 clock-output-names = "fftc-1";
232 reg = <0x023500c4 0xb00>, <0x023504c0 0x400>;
233 reg-names = "control", "domain";
234 domain-id = <28>;
235 };
236
237 clkiqnail: clkiqnail {
238 #clock-cells = <0>;
239 compatible = "ti,keystone,psc-clock";
240 clocks = <&chipclk13>;
241 clock-output-names = "iqn-ail";
242 reg = <0x023500c8 0xb00>, <0x0235004c 0x400>;
243 reg-names = "control", "domain";
244 domain-id = <29>;
245 };
246
247 clkuart2: clkuart2 {
248 #clock-cells = <0>;
249 compatible = "ti,keystone,psc-clock";
250 clocks = <&clkmodrst0>;
251 clock-output-names = "uart2";
252 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
253 reg-names = "control", "domain";
254 domain-id = <0>;
255 };
256
257 clkuart3: clkuart3 {
258 #clock-cells = <0>;
259 compatible = "ti,keystone,psc-clock";
260 clocks = <&clkmodrst0>;
261 clock-output-names = "uart3";
262 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
263 reg-names = "control", "domain";
264 domain-id = <0>;
265 };
266};