1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Copyright (c) 2013-2014 Linaro Ltd.
 4 * Copyright (c) 2013-2014 HiSilicon Limited.
 
 
 
 
 5 */
 6
 7/dts-v1/;
 8#include "hisi-x5hd2.dtsi"
 9
10/ {
11	model = "Hisilicon HIX5HD2 Development Board";
12	compatible = "hisilicon,hix5hd2";
13
14	chosen {
15		stdout-path = "serial0:115200n8";
16	};
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21		enable-method = "hisilicon,hix5hd2-smp";
22
23		cpu@0 {
24			compatible = "arm,cortex-a9";
25			device_type = "cpu";
26			reg = <0>;
27			next-level-cache = <&l2>;
28		};
29
30		cpu@1 {
31			compatible = "arm,cortex-a9";
32			device_type = "cpu";
33			reg = <1>;
34			next-level-cache = <&l2>;
35		};
36	};
37
38	memory@0 {
39		device_type = "memory";
40		reg = <0x00000000 0x80000000>;
41	};
42};
43
44&timer0 {
45	status = "okay";
46};
47
48&uart0 {
49	status = "okay";
50};
51
52&gmac0 {
53	#address-cells = <1>;
54	#size-cells = <0>;
55	phy-handle = <&phy2>;
56	phy-mode = "mii";
57	/* Placeholder, overwritten by bootloader */
58	mac-address = [00 00 00 00 00 00];
59	status = "okay";
60
61	phy2: ethernet-phy@2 {
62		reg = <2>;
63	};
64};
65
66&gmac1 {
67	#address-cells = <1>;
68	#size-cells = <0>;
69	phy-handle = <&phy1>;
70	phy-mode = "rgmii";
71	/* Placeholder, overwritten by bootloader */
72	mac-address = [00 00 00 00 00 00];
73	status = "okay";
74
75	phy1: ethernet-phy@1 {
76		reg = <1>;
77	};
78};
79
80&ahci {
81	phys = <&sata_phy>;
82	phy-names = "sata-phy";
83};

 
 1/*
 2 * Copyright (c) 2013-2014 Linaro Ltd.
 3 * Copyright (c) 2013-2014 Hisilicon Limited.
 4 *
 5 *  This program is free software; you can redistribute it and/or modify
 6 *  it under the terms of the GNU General Public License version 2 as
 7 *  publishhed by the Free Software Foundation.
 8 */
 9
10/dts-v1/;
11#include "hisi-x5hd2.dtsi"
12
13/ {
14	model = "Hisilicon HIX5HD2 Development Board";
15	compatible = "hisilicon,hix5hd2";
16
17	chosen {
18		stdout-path = "serial0:115200n8";
19	};
20
21	cpus {
22		#address-cells = <1>;
23		#size-cells = <0>;
24		enable-method = "hisilicon,hix5hd2-smp";
25
26		cpu@0 {
27			compatible = "arm,cortex-a9";
28			device_type = "cpu";
29			reg = <0>;
30			next-level-cache = <&l2>;
31		};
32
33		cpu@1 {
34			compatible = "arm,cortex-a9";
35			device_type = "cpu";
36			reg = <1>;
37			next-level-cache = <&l2>;
38		};
39	};
40
41	memory {
42		device_type = "memory";
43		reg = <0x00000000 0x80000000>;
44	};
45};
46
47&timer0 {
48	status = "okay";
49};
50
51&uart0 {
52	status = "okay";
53};
54
55&gmac0 {
56	#address-cells = <1>;
57	#size-cells = <0>;
58	phy-handle = <&phy2>;
59	phy-mode = "mii";
60	/* Placeholder, overwritten by bootloader */
61	mac-address = [00 00 00 00 00 00];
62	status = "okay";
63
64	phy2: ethernet-phy@2 {
65		reg = <2>;
66	};
67};
68
69&gmac1 {
70	#address-cells = <1>;
71	#size-cells = <0>;
72	phy-handle = <&phy1>;
73	phy-mode = "rgmii";
74	/* Placeholder, overwritten by bootloader */
75	mac-address = [00 00 00 00 00 00];
76	status = "okay";
77
78	phy1: ethernet-phy@1 {
79		reg = <1>;
80	};
81};
82
83&ahci {
84	phys = <&sata_phy>;
85	phy-names = "sata-phy";
86};