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1/*
2 * Samsung's Exynos4x12 SoCs device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20#include "exynos4.dtsi"
21#include "exynos4x12-pinctrl.dtsi"
22#include "exynos4-cpu-thermal.dtsi"
23
24/ {
25 aliases {
26 pinctrl0 = &pinctrl_0;
27 pinctrl1 = &pinctrl_1;
28 pinctrl2 = &pinctrl_2;
29 pinctrl3 = &pinctrl_3;
30 fimc-lite0 = &fimc_lite_0;
31 fimc-lite1 = &fimc_lite_1;
32 mshc0 = &mshc_0;
33 };
34
35 sysram@02020000 {
36 compatible = "mmio-sram";
37 reg = <0x02020000 0x40000>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges = <0 0x02020000 0x40000>;
41
42 smp-sysram@0 {
43 compatible = "samsung,exynos4210-sysram";
44 reg = <0x0 0x1000>;
45 };
46
47 smp-sysram@2f000 {
48 compatible = "samsung,exynos4210-sysram-ns";
49 reg = <0x2f000 0x1000>;
50 };
51 };
52
53 pd_isp: isp-power-domain@10023CA0 {
54 compatible = "samsung,exynos4210-pd";
55 reg = <0x10023CA0 0x20>;
56 #power-domain-cells = <0>;
57 };
58
59 l2c: l2-cache-controller@10502000 {
60 compatible = "arm,pl310-cache";
61 reg = <0x10502000 0x1000>;
62 cache-unified;
63 cache-level = <2>;
64 arm,tag-latency = <2 2 1>;
65 arm,data-latency = <3 2 1>;
66 arm,double-linefill = <1>;
67 arm,double-linefill-incr = <0>;
68 arm,double-linefill-wrap = <1>;
69 arm,prefetch-drop = <1>;
70 arm,prefetch-offset = <7>;
71 };
72
73 clock: clock-controller@10030000 {
74 compatible = "samsung,exynos4412-clock";
75 reg = <0x10030000 0x20000>;
76 #clock-cells = <1>;
77 };
78
79 mct@10050000 {
80 compatible = "samsung,exynos4412-mct";
81 reg = <0x10050000 0x800>;
82 interrupt-parent = <&mct_map>;
83 interrupts = <0>, <1>, <2>, <3>, <4>;
84 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
85 clock-names = "fin_pll", "mct";
86
87 mct_map: mct-map {
88 #interrupt-cells = <1>;
89 #address-cells = <0>;
90 #size-cells = <0>;
91 interrupt-map = <0 &gic 0 57 0>,
92 <1 &combiner 12 5>,
93 <2 &combiner 12 6>,
94 <3 &combiner 12 7>,
95 <4 &gic 1 12 0>;
96 };
97 };
98
99 adc: adc@126C0000 {
100 compatible = "samsung,exynos-adc-v1";
101 reg = <0x126C0000 0x100>;
102 interrupt-parent = <&combiner>;
103 interrupts = <10 3>;
104 clocks = <&clock CLK_TSADC>;
105 clock-names = "adc";
106 #io-channel-cells = <1>;
107 io-channel-ranges;
108 samsung,syscon-phandle = <&pmu_system_controller>;
109 status = "disabled";
110 };
111
112 g2d: g2d@10800000 {
113 compatible = "samsung,exynos4212-g2d";
114 reg = <0x10800000 0x1000>;
115 interrupts = <0 89 0>;
116 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
117 clock-names = "sclk_fimg2d", "fimg2d";
118 iommus = <&sysmmu_g2d>;
119 };
120
121 camera {
122 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
123 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
124 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
125
126 /* fimc_[0-3] are configured outside, under phandles */
127 fimc_lite_0: fimc-lite@12390000 {
128 compatible = "samsung,exynos4212-fimc-lite";
129 reg = <0x12390000 0x1000>;
130 interrupts = <0 105 0>;
131 power-domains = <&pd_isp>;
132 clocks = <&clock CLK_FIMC_LITE0>;
133 clock-names = "flite";
134 iommus = <&sysmmu_fimc_lite0>;
135 status = "disabled";
136 };
137
138 fimc_lite_1: fimc-lite@123A0000 {
139 compatible = "samsung,exynos4212-fimc-lite";
140 reg = <0x123A0000 0x1000>;
141 interrupts = <0 106 0>;
142 power-domains = <&pd_isp>;
143 clocks = <&clock CLK_FIMC_LITE1>;
144 clock-names = "flite";
145 iommus = <&sysmmu_fimc_lite1>;
146 status = "disabled";
147 };
148
149 fimc_is: fimc-is@12000000 {
150 compatible = "samsung,exynos4212-fimc-is", "simple-bus";
151 reg = <0x12000000 0x260000>;
152 interrupts = <0 90 0>, <0 95 0>;
153 power-domains = <&pd_isp>;
154 clocks = <&clock CLK_FIMC_LITE0>,
155 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
156 <&clock CLK_PPMUISPMX>,
157 <&clock CLK_MOUT_MPLL_USER_T>,
158 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
159 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
160 <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
161 <&clock CLK_DIV_MCUISP0>,
162 <&clock CLK_DIV_MCUISP1>,
163 <&clock CLK_UART_ISP_SCLK>,
164 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
165 <&clock CLK_ACLK400_MCUISP>,
166 <&clock CLK_DIV_ACLK400_MCUISP>;
167 clock-names = "lite0", "lite1", "ppmuispx",
168 "ppmuispmx", "mpll", "isp",
169 "drc", "fd", "mcuisp",
170 "ispdiv0", "ispdiv1", "mcuispdiv0",
171 "mcuispdiv1", "uart", "aclk200",
172 "div_aclk200", "aclk400mcuisp",
173 "div_aclk400mcuisp";
174 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
175 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
176 iommu-names = "isp", "drc", "fd", "mcuctl";
177 #address-cells = <1>;
178 #size-cells = <1>;
179 ranges;
180 status = "disabled";
181
182 pmu {
183 reg = <0x10020000 0x3000>;
184 };
185
186 i2c1_isp: i2c-isp@12140000 {
187 compatible = "samsung,exynos4212-i2c-isp";
188 reg = <0x12140000 0x100>;
189 clocks = <&clock CLK_I2C1_ISP>;
190 clock-names = "i2c_isp";
191 #address-cells = <1>;
192 #size-cells = <0>;
193 };
194 };
195 };
196
197 mshc_0: mmc@12550000 {
198 compatible = "samsung,exynos4412-dw-mshc";
199 reg = <0x12550000 0x1000>;
200 interrupts = <0 77 0>;
201 #address-cells = <1>;
202 #size-cells = <0>;
203 fifo-depth = <0x80>;
204 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
205 clock-names = "biu", "ciu";
206 status = "disabled";
207 };
208
209 sysmmu_g2d: sysmmu@10A40000{
210 compatible = "samsung,exynos-sysmmu";
211 reg = <0x10A40000 0x1000>;
212 interrupt-parent = <&combiner>;
213 interrupts = <4 7>;
214 clock-names = "sysmmu", "master";
215 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
216 #iommu-cells = <0>;
217 };
218
219 sysmmu_fimc_isp: sysmmu@12260000 {
220 compatible = "samsung,exynos-sysmmu";
221 reg = <0x12260000 0x1000>;
222 interrupt-parent = <&combiner>;
223 interrupts = <16 2>;
224 power-domains = <&pd_isp>;
225 clock-names = "sysmmu";
226 clocks = <&clock CLK_SMMU_ISP>;
227 #iommu-cells = <0>;
228 };
229
230 sysmmu_fimc_drc: sysmmu@12270000 {
231 compatible = "samsung,exynos-sysmmu";
232 reg = <0x12270000 0x1000>;
233 interrupt-parent = <&combiner>;
234 interrupts = <16 3>;
235 power-domains = <&pd_isp>;
236 clock-names = "sysmmu";
237 clocks = <&clock CLK_SMMU_DRC>;
238 #iommu-cells = <0>;
239 };
240
241 sysmmu_fimc_fd: sysmmu@122A0000 {
242 compatible = "samsung,exynos-sysmmu";
243 reg = <0x122A0000 0x1000>;
244 interrupt-parent = <&combiner>;
245 interrupts = <16 4>;
246 power-domains = <&pd_isp>;
247 clock-names = "sysmmu";
248 clocks = <&clock CLK_SMMU_FD>;
249 #iommu-cells = <0>;
250 };
251
252 sysmmu_fimc_mcuctl: sysmmu@122B0000 {
253 compatible = "samsung,exynos-sysmmu";
254 reg = <0x122B0000 0x1000>;
255 interrupt-parent = <&combiner>;
256 interrupts = <16 5>;
257 power-domains = <&pd_isp>;
258 clock-names = "sysmmu";
259 clocks = <&clock CLK_SMMU_ISPCX>;
260 #iommu-cells = <0>;
261 };
262
263 sysmmu_fimc_lite0: sysmmu@123B0000 {
264 compatible = "samsung,exynos-sysmmu";
265 reg = <0x123B0000 0x1000>;
266 interrupt-parent = <&combiner>;
267 interrupts = <16 0>;
268 power-domains = <&pd_isp>;
269 clock-names = "sysmmu", "master";
270 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>;
271 #iommu-cells = <0>;
272 };
273
274 sysmmu_fimc_lite1: sysmmu@123C0000 {
275 compatible = "samsung,exynos-sysmmu";
276 reg = <0x123C0000 0x1000>;
277 interrupt-parent = <&combiner>;
278 interrupts = <16 1>;
279 power-domains = <&pd_isp>;
280 clock-names = "sysmmu", "master";
281 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
282 #iommu-cells = <0>;
283 };
284};
285
286&combiner {
287 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
288 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
289 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
290 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
291 <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
292};
293
294&exynos_usbphy {
295 compatible = "samsung,exynos4x12-usb2-phy";
296 samsung,sysreg-phandle = <&sys_reg>;
297};
298
299&fimc_0 {
300 compatible = "samsung,exynos4212-fimc";
301 samsung,pix-limits = <4224 8192 1920 4224>;
302 samsung,mainscaler-ext;
303 samsung,isp-wb;
304 samsung,cam-if;
305};
306
307&fimc_1 {
308 compatible = "samsung,exynos4212-fimc";
309 samsung,pix-limits = <4224 8192 1920 4224>;
310 samsung,mainscaler-ext;
311 samsung,isp-wb;
312 samsung,cam-if;
313};
314
315&fimc_2 {
316 compatible = "samsung,exynos4212-fimc";
317 samsung,pix-limits = <4224 8192 1920 4224>;
318 samsung,mainscaler-ext;
319 samsung,isp-wb;
320 samsung,lcd-wb;
321 samsung,cam-if;
322};
323
324&fimc_3 {
325 compatible = "samsung,exynos4212-fimc";
326 samsung,pix-limits = <1920 8192 1366 1920>;
327 samsung,rotators = <0>;
328 samsung,mainscaler-ext;
329 samsung,isp-wb;
330 samsung,lcd-wb;
331};
332
333&hdmi {
334 compatible = "samsung,exynos4212-hdmi";
335};
336
337&jpeg_codec {
338 compatible = "samsung,exynos4212-jpeg";
339};
340
341&rotator {
342 compatible = "samsung,exynos4212-rotator";
343};
344
345&mixer {
346 compatible = "samsung,exynos4212-mixer";
347 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
348 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
349 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
350};
351
352&pinctrl_0 {
353 compatible = "samsung,exynos4x12-pinctrl";
354 reg = <0x11400000 0x1000>;
355 interrupts = <0 47 0>;
356};
357
358&pinctrl_1 {
359 compatible = "samsung,exynos4x12-pinctrl";
360 reg = <0x11000000 0x1000>;
361 interrupts = <0 46 0>;
362
363 wakup_eint: wakeup-interrupt-controller {
364 compatible = "samsung,exynos4210-wakeup-eint";
365 interrupt-parent = <&gic>;
366 interrupts = <0 32 0>;
367 };
368};
369
370&pinctrl_2 {
371 compatible = "samsung,exynos4x12-pinctrl";
372 reg = <0x03860000 0x1000>;
373 interrupt-parent = <&combiner>;
374 interrupts = <10 0>;
375};
376
377&pinctrl_3 {
378 compatible = "samsung,exynos4x12-pinctrl";
379 reg = <0x106E0000 0x1000>;
380 interrupts = <0 72 0>;
381};
382
383&pmu_system_controller {
384 compatible = "samsung,exynos4212-pmu", "syscon";
385 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
386 "clkout4", "clkout8", "clkout9";
387 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
388 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
389 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
390 #clock-cells = <1>;
391};
392
393&tmu {
394 compatible = "samsung,exynos4412-tmu";
395 interrupt-parent = <&combiner>;
396 interrupts = <2 4>;
397 reg = <0x100C0000 0x100>;
398 clocks = <&clock 383>;
399 clock-names = "tmu_apbif";
400 status = "disabled";
401};