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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Emma Mobile EV2 SoC
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10
11/ {
12 compatible = "renesas,emev2";
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
23 i2c0 = &iic0;
24 i2c1 = &iic1;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu0: cpu@0 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 reg = <0>;
35 clock-frequency = <533000000>;
36 };
37 cpu1: cpu@1 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a9";
40 reg = <1>;
41 clock-frequency = <533000000>;
42 };
43 };
44
45 gic: interrupt-controller@e0020000 {
46 compatible = "arm,pl390";
47 interrupt-controller;
48 #interrupt-cells = <3>;
49 reg = <0xe0028000 0x1000>,
50 <0xe0020000 0x0100>;
51 };
52
53 pmu {
54 compatible = "arm,cortex-a9-pmu";
55 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
57 interrupt-affinity = <&cpu0>, <&cpu1>;
58 };
59
60 clocks@e0110000 {
61 compatible = "renesas,emev2-smu";
62 reg = <0xe0110000 0x10000>;
63 #address-cells = <2>;
64 #size-cells = <0>;
65
66 c32ki: c32ki {
67 compatible = "fixed-clock";
68 clock-frequency = <32768>;
69 #clock-cells = <0>;
70 };
71 iic0_sclkdiv: iic0_sclkdiv@624,0 {
72 compatible = "renesas,emev2-smu-clkdiv";
73 reg = <0x624 0>;
74 clocks = <&pll3_fo>;
75 #clock-cells = <0>;
76 };
77 iic0_sclk: iic0_sclk@48c,1 {
78 compatible = "renesas,emev2-smu-gclk";
79 reg = <0x48c 1>;
80 clocks = <&iic0_sclkdiv>;
81 #clock-cells = <0>;
82 };
83 iic1_sclkdiv: iic1_sclkdiv@624,16 {
84 compatible = "renesas,emev2-smu-clkdiv";
85 reg = <0x624 16>;
86 clocks = <&pll3_fo>;
87 #clock-cells = <0>;
88 };
89 iic1_sclk: iic1_sclk@490,1 {
90 compatible = "renesas,emev2-smu-gclk";
91 reg = <0x490 1>;
92 clocks = <&iic1_sclkdiv>;
93 #clock-cells = <0>;
94 };
95 pll3_fo: pll3_fo {
96 compatible = "fixed-factor-clock";
97 clocks = <&c32ki>;
98 clock-div = <1>;
99 clock-mult = <7000>;
100 #clock-cells = <0>;
101 };
102 usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
103 compatible = "renesas,emev2-smu-clkdiv";
104 reg = <0x610 0>;
105 clocks = <&pll3_fo>;
106 #clock-cells = <0>;
107 };
108 usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 {
109 compatible = "renesas,emev2-smu-clkdiv";
110 reg = <0x65c 0>;
111 clocks = <&pll3_fo>;
112 #clock-cells = <0>;
113 };
114 usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 {
115 compatible = "renesas,emev2-smu-clkdiv";
116 reg = <0x65c 16>;
117 clocks = <&pll3_fo>;
118 #clock-cells = <0>;
119 };
120 usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 {
121 compatible = "renesas,emev2-smu-clkdiv";
122 reg = <0x660 0>;
123 clocks = <&pll3_fo>;
124 #clock-cells = <0>;
125 };
126 usia_u0_sclk: usia_u0_sclk@4a0,1 {
127 compatible = "renesas,emev2-smu-gclk";
128 reg = <0x4a0 1>;
129 clocks = <&usia_u0_sclkdiv>;
130 #clock-cells = <0>;
131 };
132 usib_u1_sclk: usib_u1_sclk@4b8,1 {
133 compatible = "renesas,emev2-smu-gclk";
134 reg = <0x4b8 1>;
135 clocks = <&usib_u1_sclkdiv>;
136 #clock-cells = <0>;
137 };
138 usib_u2_sclk: usib_u2_sclk@4bc,1 {
139 compatible = "renesas,emev2-smu-gclk";
140 reg = <0x4bc 1>;
141 clocks = <&usib_u2_sclkdiv>;
142 #clock-cells = <0>;
143 };
144 usib_u3_sclk: usib_u3_sclk@4c0,1 {
145 compatible = "renesas,emev2-smu-gclk";
146 reg = <0x4c0 1>;
147 clocks = <&usib_u3_sclkdiv>;
148 #clock-cells = <0>;
149 };
150 sti_sclk: sti_sclk@528,1 {
151 compatible = "renesas,emev2-smu-gclk";
152 reg = <0x528 1>;
153 clocks = <&c32ki>;
154 #clock-cells = <0>;
155 };
156 };
157
158 timer@e0180000 {
159 compatible = "renesas,em-sti";
160 reg = <0xe0180000 0x54>;
161 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
162 clocks = <&sti_sclk>;
163 clock-names = "sclk";
164 };
165
166 uart0: serial@e1020000 {
167 compatible = "renesas,em-uart";
168 reg = <0xe1020000 0x38>;
169 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&usia_u0_sclk>;
171 clock-names = "sclk";
172 };
173
174 uart1: serial@e1030000 {
175 compatible = "renesas,em-uart";
176 reg = <0xe1030000 0x38>;
177 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&usib_u1_sclk>;
179 clock-names = "sclk";
180 };
181
182 uart2: serial@e1040000 {
183 compatible = "renesas,em-uart";
184 reg = <0xe1040000 0x38>;
185 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&usib_u2_sclk>;
187 clock-names = "sclk";
188 };
189
190 uart3: serial@e1050000 {
191 compatible = "renesas,em-uart";
192 reg = <0xe1050000 0x38>;
193 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&usib_u3_sclk>;
195 clock-names = "sclk";
196 };
197
198 pfc: pinctrl@e0140200 {
199 compatible = "renesas,pfc-emev2";
200 reg = <0xe0140200 0x100>;
201 };
202
203 gpio0: gpio@e0050000 {
204 compatible = "renesas,em-gio";
205 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
206 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
208 gpio-controller;
209 gpio-ranges = <&pfc 0 0 32>;
210 #gpio-cells = <2>;
211 ngpios = <32>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 };
215
216 gpio1: gpio@e0050080 {
217 compatible = "renesas,em-gio";
218 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
219 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
221 gpio-controller;
222 gpio-ranges = <&pfc 0 32 32>;
223 #gpio-cells = <2>;
224 ngpios = <32>;
225 interrupt-controller;
226 #interrupt-cells = <2>;
227 };
228
229 gpio2: gpio@e0050100 {
230 compatible = "renesas,em-gio";
231 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
232 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
234 gpio-controller;
235 gpio-ranges = <&pfc 0 64 32>;
236 #gpio-cells = <2>;
237 ngpios = <32>;
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 };
241
242 gpio3: gpio@e0050180 {
243 compatible = "renesas,em-gio";
244 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
245 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
247 gpio-controller;
248 gpio-ranges = <&pfc 0 96 32>;
249 #gpio-cells = <2>;
250 ngpios = <32>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 };
254
255 gpio4: gpio@e0050200 {
256 compatible = "renesas,em-gio";
257 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
258 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
260 gpio-controller;
261 gpio-ranges = <&pfc 0 128 31>;
262 #gpio-cells = <2>;
263 ngpios = <31>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 };
267
268 iic0: i2c@e0070000 {
269 #address-cells = <1>;
270 #size-cells = <0>;
271 compatible = "renesas,iic-emev2";
272 reg = <0xe0070000 0x28>;
273 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
274 clocks = <&iic0_sclk>;
275 clock-names = "sclk";
276 status = "disabled";
277 };
278
279 iic1: i2c@e10a0000 {
280 #address-cells = <1>;
281 #size-cells = <0>;
282 compatible = "renesas,iic-emev2";
283 reg = <0xe10a0000 0x28>;
284 interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
285 clocks = <&iic1_sclk>;
286 clock-names = "sclk";
287 status = "disabled";
288 };
289};
1/*
2 * Device Tree Source for the EMEV2 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include "skeleton.dtsi"
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
15/ {
16 compatible = "renesas,emev2";
17 interrupt-parent = <&gic>;
18
19 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 gpio2 = &gpio2;
23 gpio3 = &gpio3;
24 gpio4 = &gpio4;
25 i2c0 = &iic0;
26 i2c1 = &iic1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a9";
36 reg = <0>;
37 clock-frequency = <533000000>;
38 };
39 cpu@1 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a9";
42 reg = <1>;
43 clock-frequency = <533000000>;
44 };
45 };
46
47 gic: interrupt-controller@e0020000 {
48 compatible = "arm,pl390";
49 interrupt-controller;
50 #interrupt-cells = <3>;
51 reg = <0xe0028000 0x1000>,
52 <0xe0020000 0x0100>;
53 };
54
55 pmu {
56 compatible = "arm,cortex-a9-pmu";
57 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
59 };
60
61 clocks@e0110000 {
62 compatible = "renesas,emev2-smu";
63 reg = <0xe0110000 0x10000>;
64 #address-cells = <2>;
65 #size-cells = <0>;
66
67 c32ki: c32ki {
68 compatible = "fixed-clock";
69 clock-frequency = <32768>;
70 #clock-cells = <0>;
71 };
72 iic0_sclkdiv: iic0_sclkdiv {
73 compatible = "renesas,emev2-smu-clkdiv";
74 reg = <0x624 0>;
75 clocks = <&pll3_fo>;
76 #clock-cells = <0>;
77 };
78 iic0_sclk: iic0_sclk {
79 compatible = "renesas,emev2-smu-gclk";
80 reg = <0x48c 1>;
81 clocks = <&iic0_sclkdiv>;
82 #clock-cells = <0>;
83 };
84 iic1_sclkdiv: iic1_sclkdiv {
85 compatible = "renesas,emev2-smu-clkdiv";
86 reg = <0x624 16>;
87 clocks = <&pll3_fo>;
88 #clock-cells = <0>;
89 };
90 iic1_sclk: iic1_sclk {
91 compatible = "renesas,emev2-smu-gclk";
92 reg = <0x490 1>;
93 clocks = <&iic1_sclkdiv>;
94 #clock-cells = <0>;
95 };
96 pll3_fo: pll3_fo {
97 compatible = "fixed-factor-clock";
98 clocks = <&c32ki>;
99 clock-div = <1>;
100 clock-mult = <7000>;
101 #clock-cells = <0>;
102 };
103 usia_u0_sclkdiv: usia_u0_sclkdiv {
104 compatible = "renesas,emev2-smu-clkdiv";
105 reg = <0x610 0>;
106 clocks = <&pll3_fo>;
107 #clock-cells = <0>;
108 };
109 usib_u1_sclkdiv: usib_u1_sclkdiv {
110 compatible = "renesas,emev2-smu-clkdiv";
111 reg = <0x65c 0>;
112 clocks = <&pll3_fo>;
113 #clock-cells = <0>;
114 };
115 usib_u2_sclkdiv: usib_u2_sclkdiv {
116 compatible = "renesas,emev2-smu-clkdiv";
117 reg = <0x65c 16>;
118 clocks = <&pll3_fo>;
119 #clock-cells = <0>;
120 };
121 usib_u3_sclkdiv: usib_u3_sclkdiv {
122 compatible = "renesas,emev2-smu-clkdiv";
123 reg = <0x660 0>;
124 clocks = <&pll3_fo>;
125 #clock-cells = <0>;
126 };
127 usia_u0_sclk: usia_u0_sclk {
128 compatible = "renesas,emev2-smu-gclk";
129 reg = <0x4a0 1>;
130 clocks = <&usia_u0_sclkdiv>;
131 #clock-cells = <0>;
132 };
133 usib_u1_sclk: usib_u1_sclk {
134 compatible = "renesas,emev2-smu-gclk";
135 reg = <0x4b8 1>;
136 clocks = <&usib_u1_sclkdiv>;
137 #clock-cells = <0>;
138 };
139 usib_u2_sclk: usib_u2_sclk {
140 compatible = "renesas,emev2-smu-gclk";
141 reg = <0x4bc 1>;
142 clocks = <&usib_u2_sclkdiv>;
143 #clock-cells = <0>;
144 };
145 usib_u3_sclk: usib_u3_sclk {
146 compatible = "renesas,emev2-smu-gclk";
147 reg = <0x4c0 1>;
148 clocks = <&usib_u3_sclkdiv>;
149 #clock-cells = <0>;
150 };
151 sti_sclk: sti_sclk {
152 compatible = "renesas,emev2-smu-gclk";
153 reg = <0x528 1>;
154 clocks = <&c32ki>;
155 #clock-cells = <0>;
156 };
157 };
158
159 timer@e0180000 {
160 compatible = "renesas,em-sti";
161 reg = <0xe0180000 0x54>;
162 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&sti_sclk>;
164 clock-names = "sclk";
165 };
166
167 uart0: serial@e1020000 {
168 compatible = "renesas,em-uart";
169 reg = <0xe1020000 0x38>;
170 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&usia_u0_sclk>;
172 clock-names = "sclk";
173 };
174
175 uart1: serial@e1030000 {
176 compatible = "renesas,em-uart";
177 reg = <0xe1030000 0x38>;
178 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&usib_u1_sclk>;
180 clock-names = "sclk";
181 };
182
183 uart2: serial@e1040000 {
184 compatible = "renesas,em-uart";
185 reg = <0xe1040000 0x38>;
186 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&usib_u2_sclk>;
188 clock-names = "sclk";
189 };
190
191 uart3: serial@e1050000 {
192 compatible = "renesas,em-uart";
193 reg = <0xe1050000 0x38>;
194 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&usib_u3_sclk>;
196 clock-names = "sclk";
197 };
198
199 pfc: pfc@e0140200 {
200 compatible = "renesas,pfc-emev2";
201 reg = <0xe0140200 0x100>;
202 };
203
204 gpio0: gpio@e0050000 {
205 compatible = "renesas,em-gio";
206 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
207 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
209 gpio-controller;
210 gpio-ranges = <&pfc 0 0 32>;
211 #gpio-cells = <2>;
212 ngpios = <32>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
215 };
216 gpio1: gpio@e0050080 {
217 compatible = "renesas,em-gio";
218 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
219 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
221 gpio-controller;
222 gpio-ranges = <&pfc 0 32 32>;
223 #gpio-cells = <2>;
224 ngpios = <32>;
225 interrupt-controller;
226 #interrupt-cells = <2>;
227 };
228 gpio2: gpio@e0050100 {
229 compatible = "renesas,em-gio";
230 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
231 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
233 gpio-controller;
234 gpio-ranges = <&pfc 0 64 32>;
235 #gpio-cells = <2>;
236 ngpios = <32>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 };
240 gpio3: gpio@e0050180 {
241 compatible = "renesas,em-gio";
242 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
243 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
245 gpio-controller;
246 gpio-ranges = <&pfc 0 96 32>;
247 #gpio-cells = <2>;
248 ngpios = <32>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
252 gpio4: gpio@e0050200 {
253 compatible = "renesas,em-gio";
254 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
255 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
257 gpio-controller;
258 gpio-ranges = <&pfc 0 128 31>;
259 #gpio-cells = <2>;
260 ngpios = <31>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 };
264
265 iic0: i2c@e0070000 {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 compatible = "renesas,iic-emev2";
269 reg = <0xe0070000 0x28>;
270 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
271 clocks = <&iic0_sclk>;
272 clock-names = "sclk";
273 status = "disabled";
274 };
275
276 iic1: i2c@e10a0000 {
277 #address-cells = <1>;
278 #size-cells = <0>;
279 compatible = "renesas,iic-emev2";
280 reg = <0xe10a0000 0x28>;
281 interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
282 clocks = <&iic1_sclk>;
283 clock-names = "sclk";
284 status = "disabled";
285 };
286};