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1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/clock/aspeed-clock.h>
3#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
4
5/ {
6 model = "Aspeed BMC";
7 compatible = "aspeed,ast2500";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&vic>;
11
12 aliases {
13 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 i2c2 = &i2c2;
16 i2c3 = &i2c3;
17 i2c4 = &i2c4;
18 i2c5 = &i2c5;
19 i2c6 = &i2c6;
20 i2c7 = &i2c7;
21 i2c8 = &i2c8;
22 i2c9 = &i2c9;
23 i2c10 = &i2c10;
24 i2c11 = &i2c11;
25 i2c12 = &i2c12;
26 i2c13 = &i2c13;
27 serial0 = &uart1;
28 serial1 = &uart2;
29 serial2 = &uart3;
30 serial3 = &uart4;
31 serial4 = &uart5;
32 serial5 = &vuart;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu@0 {
40 compatible = "arm,arm1176jzf-s";
41 device_type = "cpu";
42 reg = <0>;
43 };
44 };
45
46 memory@80000000 {
47 device_type = "memory";
48 reg = <0x80000000 0>;
49 };
50
51 ahb {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 fmc: spi@1e620000 {
58 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
59 #address-cells = <1>;
60 #size-cells = <0>;
61 compatible = "aspeed,ast2500-fmc";
62 clocks = <&syscon ASPEED_CLK_AHB>;
63 status = "disabled";
64 interrupts = <19>;
65 flash@0 {
66 reg = < 0 >;
67 compatible = "jedec,spi-nor";
68 spi-max-frequency = <50000000>;
69 spi-rx-bus-width = <2>;
70 status = "disabled";
71 };
72 flash@1 {
73 reg = < 1 >;
74 compatible = "jedec,spi-nor";
75 spi-max-frequency = <50000000>;
76 spi-rx-bus-width = <2>;
77 status = "disabled";
78 };
79 flash@2 {
80 reg = < 2 >;
81 compatible = "jedec,spi-nor";
82 spi-max-frequency = <50000000>;
83 spi-rx-bus-width = <2>;
84 status = "disabled";
85 };
86 };
87
88 spi1: spi@1e630000 {
89 reg = <0x1e630000 0xc4>, <0x30000000 0x08000000>;
90 #address-cells = <1>;
91 #size-cells = <0>;
92 compatible = "aspeed,ast2500-spi";
93 clocks = <&syscon ASPEED_CLK_AHB>;
94 status = "disabled";
95 flash@0 {
96 reg = < 0 >;
97 compatible = "jedec,spi-nor";
98 spi-max-frequency = <50000000>;
99 spi-rx-bus-width = <2>;
100 status = "disabled";
101 };
102 flash@1 {
103 reg = < 1 >;
104 compatible = "jedec,spi-nor";
105 spi-max-frequency = <50000000>;
106 spi-rx-bus-width = <2>;
107 status = "disabled";
108 };
109 };
110
111 spi2: spi@1e631000 {
112 reg = <0x1e631000 0xc4>, <0x38000000 0x08000000>;
113 #address-cells = <1>;
114 #size-cells = <0>;
115 compatible = "aspeed,ast2500-spi";
116 clocks = <&syscon ASPEED_CLK_AHB>;
117 status = "disabled";
118 flash@0 {
119 reg = < 0 >;
120 compatible = "jedec,spi-nor";
121 spi-max-frequency = <50000000>;
122 spi-rx-bus-width = <2>;
123 status = "disabled";
124 };
125 flash@1 {
126 reg = < 1 >;
127 compatible = "jedec,spi-nor";
128 spi-max-frequency = <50000000>;
129 spi-rx-bus-width = <2>;
130 status = "disabled";
131 };
132 };
133
134 vic: interrupt-controller@1e6c0080 {
135 compatible = "aspeed,ast2400-vic";
136 interrupt-controller;
137 #interrupt-cells = <1>;
138 valid-sources = <0xfefff7ff 0x0807ffff>;
139 reg = <0x1e6c0080 0x80>;
140 };
141
142 cvic: copro-interrupt-controller@1e6c2000 {
143 compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
144 valid-sources = <0xffffffff>;
145 copro-sw-interrupts = <1>;
146 reg = <0x1e6c2000 0x80>;
147 };
148
149 mac0: ethernet@1e660000 {
150 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
151 reg = <0x1e660000 0x180>;
152 interrupts = <2>;
153 clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
154 status = "disabled";
155 };
156
157 mac1: ethernet@1e680000 {
158 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
159 reg = <0x1e680000 0x180>;
160 interrupts = <3>;
161 clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
162 status = "disabled";
163 };
164
165 ehci0: usb@1e6a1000 {
166 compatible = "aspeed,ast2500-ehci", "generic-ehci";
167 reg = <0x1e6a1000 0x100>;
168 interrupts = <5>;
169 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_usb2ah_default>;
172 status = "disabled";
173 };
174
175 ehci1: usb@1e6a3000 {
176 compatible = "aspeed,ast2500-ehci", "generic-ehci";
177 reg = <0x1e6a3000 0x100>;
178 interrupts = <13>;
179 clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usb2bh_default>;
182 status = "disabled";
183 };
184
185 uhci: usb@1e6b0000 {
186 compatible = "aspeed,ast2500-uhci", "generic-uhci";
187 reg = <0x1e6b0000 0x100>;
188 interrupts = <14>;
189 #ports = <2>;
190 clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
191 status = "disabled";
192 /*
193 * No default pinmux, it will follow EHCI, use an explicit pinmux
194 * override if you don't enable EHCI
195 */
196 };
197
198 vhub: usb-vhub@1e6a0000 {
199 compatible = "aspeed,ast2500-usb-vhub";
200 reg = <0x1e6a0000 0x300>;
201 interrupts = <5>;
202 clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
203 aspeed,vhub-downstream-ports = <5>;
204 aspeed,vhub-generic-endpoints = <15>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_usb2ad_default>;
207 status = "disabled";
208 };
209
210 apb {
211 compatible = "simple-bus";
212 #address-cells = <1>;
213 #size-cells = <1>;
214 ranges;
215
216 edac: memory-controller@1e6e0000 {
217 compatible = "aspeed,ast2500-sdram-edac";
218 reg = <0x1e6e0000 0x174>;
219 interrupts = <0>;
220 status = "disabled";
221 };
222
223 syscon: syscon@1e6e2000 {
224 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
225 reg = <0x1e6e2000 0x1a8>;
226 #address-cells = <1>;
227 #size-cells = <1>;
228 ranges = <0 0x1e6e2000 0x1000>;
229 #clock-cells = <1>;
230 #reset-cells = <1>;
231
232 scu_ic: interrupt-controller@18 {
233 #interrupt-cells = <1>;
234 compatible = "aspeed,ast2500-scu-ic";
235 reg = <0x18 0x4>;
236 interrupts = <21>;
237 interrupt-controller;
238 };
239
240 p2a: p2a-control@2c {
241 compatible = "aspeed,ast2500-p2a-ctrl";
242 reg = <0x2c 0x4>;
243 status = "disabled";
244 };
245
246 silicon-id@7c {
247 compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
248 reg = <0x7c 0x4 0x150 0x8>;
249 };
250
251 pinctrl: pinctrl@80 {
252 compatible = "aspeed,ast2500-pinctrl";
253 reg = <0x80 0x18>, <0xa0 0x10>;
254 aspeed,external-nodes = <&gfx>, <&lhc>;
255 };
256 };
257
258 rng: hwrng@1e6e2078 {
259 compatible = "timeriomem_rng";
260 reg = <0x1e6e2078 0x4>;
261 period = <1>;
262 quality = <100>;
263 };
264
265 hace: crypto@1e6e3000 {
266 compatible = "aspeed,ast2500-hace";
267 reg = <0x1e6e3000 0x100>;
268 interrupts = <4>;
269 clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
270 resets = <&syscon ASPEED_RESET_HACE>;
271 };
272
273 gfx: display@1e6e6000 {
274 compatible = "aspeed,ast2500-gfx", "syscon";
275 reg = <0x1e6e6000 0x1000>;
276 reg-io-width = <4>;
277 clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
278 resets = <&syscon ASPEED_RESET_CRT1>;
279 syscon = <&syscon>;
280 status = "disabled";
281 interrupts = <0x19>;
282 };
283
284 xdma: xdma@1e6e7000 {
285 compatible = "aspeed,ast2500-xdma";
286 reg = <0x1e6e7000 0x100>;
287 clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
288 resets = <&syscon ASPEED_RESET_XDMA>;
289 interrupts-extended = <&vic 6>, <&scu_ic ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI>;
290 aspeed,pcie-device = "bmc";
291 aspeed,scu = <&syscon>;
292 status = "disabled";
293 };
294
295 adc: adc@1e6e9000 {
296 compatible = "aspeed,ast2500-adc";
297 reg = <0x1e6e9000 0xb0>;
298 clocks = <&syscon ASPEED_CLK_APB>;
299 resets = <&syscon ASPEED_RESET_ADC>;
300 #io-channel-cells = <1>;
301 status = "disabled";
302 };
303
304 video: video@1e700000 {
305 compatible = "aspeed,ast2500-video-engine";
306 reg = <0x1e700000 0x1000>;
307 clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
308 <&syscon ASPEED_CLK_GATE_ECLK>;
309 clock-names = "vclk", "eclk";
310 interrupts = <7>;
311 status = "disabled";
312 };
313
314 sram: sram@1e720000 {
315 compatible = "mmio-sram";
316 reg = <0x1e720000 0x9000>; // 36K
317 };
318
319 sdmmc: sd-controller@1e740000 {
320 compatible = "aspeed,ast2500-sd-controller";
321 reg = <0x1e740000 0x100>;
322 #address-cells = <1>;
323 #size-cells = <1>;
324 ranges = <0 0x1e740000 0x10000>;
325 clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
326 status = "disabled";
327
328 sdhci0: sdhci@100 {
329 compatible = "aspeed,ast2500-sdhci";
330 reg = <0x100 0x100>;
331 interrupts = <26>;
332 sdhci,auto-cmd12;
333 clocks = <&syscon ASPEED_CLK_SDIO>;
334 status = "disabled";
335 };
336
337 sdhci1: sdhci@200 {
338 compatible = "aspeed,ast2500-sdhci";
339 reg = <0x200 0x100>;
340 interrupts = <26>;
341 sdhci,auto-cmd12;
342 clocks = <&syscon ASPEED_CLK_SDIO>;
343 status = "disabled";
344 };
345 };
346
347 gpio: gpio@1e780000 {
348 #gpio-cells = <2>;
349 gpio-controller;
350 compatible = "aspeed,ast2500-gpio";
351 reg = <0x1e780000 0x200>;
352 interrupts = <20>;
353 gpio-ranges = <&pinctrl 0 0 232>;
354 clocks = <&syscon ASPEED_CLK_APB>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 };
358
359 sgpio: sgpio@1e780200 {
360 #gpio-cells = <2>;
361 compatible = "aspeed,ast2500-sgpio";
362 gpio-controller;
363 interrupts = <40>;
364 reg = <0x1e780200 0x0100>;
365 clocks = <&syscon ASPEED_CLK_APB>;
366 interrupt-controller;
367 bus-frequency = <12000000>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_sgpm_default>;
370 status = "disabled";
371 };
372
373 rtc: rtc@1e781000 {
374 compatible = "aspeed,ast2500-rtc";
375 reg = <0x1e781000 0x18>;
376 status = "disabled";
377 };
378
379 timer: timer@1e782000 {
380 /* This timer is a Faraday FTTMR010 derivative */
381 compatible = "aspeed,ast2400-timer";
382 reg = <0x1e782000 0x90>;
383 interrupts = <16 17 18 35 36 37 38 39>;
384 clocks = <&syscon ASPEED_CLK_APB>;
385 clock-names = "PCLK";
386 };
387
388 uart1: serial@1e783000 {
389 compatible = "ns16550a";
390 reg = <0x1e783000 0x20>;
391 reg-shift = <2>;
392 interrupts = <9>;
393 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
394 resets = <&lpc_reset 4>;
395 no-loopback-test;
396 status = "disabled";
397 };
398
399 uart5: serial@1e784000 {
400 compatible = "ns16550a";
401 reg = <0x1e784000 0x20>;
402 reg-shift = <2>;
403 interrupts = <10>;
404 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
405 no-loopback-test;
406 status = "disabled";
407 };
408
409 wdt1: watchdog@1e785000 {
410 compatible = "aspeed,ast2500-wdt";
411 reg = <0x1e785000 0x20>;
412 clocks = <&syscon ASPEED_CLK_APB>;
413 };
414
415 wdt2: watchdog@1e785020 {
416 compatible = "aspeed,ast2500-wdt";
417 reg = <0x1e785020 0x20>;
418 clocks = <&syscon ASPEED_CLK_APB>;
419 };
420
421 wdt3: watchdog@1e785040 {
422 compatible = "aspeed,ast2500-wdt";
423 reg = <0x1e785040 0x20>;
424 clocks = <&syscon ASPEED_CLK_APB>;
425 status = "disabled";
426 };
427
428 pwm_tacho: pwm-tacho-controller@1e786000 {
429 compatible = "aspeed,ast2500-pwm-tacho";
430 #address-cells = <1>;
431 #size-cells = <0>;
432 reg = <0x1e786000 0x1000>;
433 clocks = <&syscon ASPEED_CLK_24M>;
434 resets = <&syscon ASPEED_RESET_PWM>;
435 status = "disabled";
436 };
437
438 vuart: serial@1e787000 {
439 compatible = "aspeed,ast2500-vuart";
440 reg = <0x1e787000 0x40>;
441 reg-shift = <2>;
442 interrupts = <8>;
443 clocks = <&syscon ASPEED_CLK_APB>;
444 no-loopback-test;
445 status = "disabled";
446 };
447
448 lpc: lpc@1e789000 {
449 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
450 reg = <0x1e789000 0x1000>;
451 reg-io-width = <4>;
452
453 #address-cells = <1>;
454 #size-cells = <1>;
455 ranges = <0x0 0x1e789000 0x1000>;
456
457 kcs1: kcs@24 {
458 compatible = "aspeed,ast2500-kcs-bmc-v2";
459 reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
460 interrupts = <8>;
461 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
462 status = "disabled";
463 };
464
465 kcs2: kcs@28 {
466 compatible = "aspeed,ast2500-kcs-bmc-v2";
467 reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
468 interrupts = <8>;
469 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
470 status = "disabled";
471 };
472
473 kcs3: kcs@2c {
474 compatible = "aspeed,ast2500-kcs-bmc-v2";
475 reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
476 interrupts = <8>;
477 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
478 status = "disabled";
479 };
480
481 kcs4: kcs@114 {
482 compatible = "aspeed,ast2500-kcs-bmc-v2";
483 reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
484 interrupts = <8>;
485 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
486 status = "disabled";
487 };
488
489 lpc_ctrl: lpc-ctrl@80 {
490 compatible = "aspeed,ast2500-lpc-ctrl";
491 reg = <0x80 0x10>;
492 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
493 status = "disabled";
494 };
495
496 lpc_snoop: lpc-snoop@90 {
497 compatible = "aspeed,ast2500-lpc-snoop";
498 reg = <0x90 0x8>;
499 interrupts = <8>;
500 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
501 status = "disabled";
502 };
503
504 lpc_reset: reset-controller@98 {
505 compatible = "aspeed,ast2500-lpc-reset";
506 reg = <0x98 0x4>;
507 #reset-cells = <1>;
508 };
509
510 uart_routing: uart-routing@9c {
511 compatible = "aspeed,ast2500-uart-routing";
512 reg = <0x9c 0x4>;
513 status = "disabled";
514 };
515
516 lhc: lhc@a0 {
517 compatible = "aspeed,ast2500-lhc";
518 reg = <0xa0 0x24 0xc8 0x8>;
519 };
520
521
522 ibt: ibt@140 {
523 compatible = "aspeed,ast2500-ibt-bmc";
524 reg = <0x140 0x18>;
525 interrupts = <8>;
526 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
527 status = "disabled";
528 };
529 };
530
531 peci0: peci-controller@1e78b000 {
532 compatible = "aspeed,ast2500-peci";
533 reg = <0x1e78b000 0x60>;
534 interrupts = <15>;
535 clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
536 resets = <&syscon ASPEED_RESET_PECI>;
537 cmd-timeout-ms = <1000>;
538 clock-frequency = <1000000>;
539 status = "disabled";
540 };
541
542 uart2: serial@1e78d000 {
543 compatible = "ns16550a";
544 reg = <0x1e78d000 0x20>;
545 reg-shift = <2>;
546 interrupts = <32>;
547 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
548 resets = <&lpc_reset 5>;
549 no-loopback-test;
550 status = "disabled";
551 };
552
553 uart3: serial@1e78e000 {
554 compatible = "ns16550a";
555 reg = <0x1e78e000 0x20>;
556 reg-shift = <2>;
557 interrupts = <33>;
558 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
559 resets = <&lpc_reset 6>;
560 no-loopback-test;
561 status = "disabled";
562 };
563
564 uart4: serial@1e78f000 {
565 compatible = "ns16550a";
566 reg = <0x1e78f000 0x20>;
567 reg-shift = <2>;
568 interrupts = <34>;
569 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
570 resets = <&lpc_reset 7>;
571 no-loopback-test;
572 status = "disabled";
573 };
574
575 i2c: bus@1e78a000 {
576 compatible = "simple-bus";
577 #address-cells = <1>;
578 #size-cells = <1>;
579 ranges = <0 0x1e78a000 0x1000>;
580 };
581 };
582 };
583};
584
585&i2c {
586 i2c_ic: interrupt-controller@0 {
587 #interrupt-cells = <1>;
588 compatible = "aspeed,ast2500-i2c-ic";
589 reg = <0x0 0x40>;
590 interrupts = <12>;
591 interrupt-controller;
592 };
593
594 i2c0: i2c-bus@40 {
595 #address-cells = <1>;
596 #size-cells = <0>;
597 #interrupt-cells = <1>;
598
599 reg = <0x40 0x40>;
600 compatible = "aspeed,ast2500-i2c-bus";
601 clocks = <&syscon ASPEED_CLK_APB>;
602 resets = <&syscon ASPEED_RESET_I2C>;
603 bus-frequency = <100000>;
604 interrupts = <0>;
605 interrupt-parent = <&i2c_ic>;
606 status = "disabled";
607 /* Does not need pinctrl properties */
608 };
609
610 i2c1: i2c-bus@80 {
611 #address-cells = <1>;
612 #size-cells = <0>;
613 #interrupt-cells = <1>;
614
615 reg = <0x80 0x40>;
616 compatible = "aspeed,ast2500-i2c-bus";
617 clocks = <&syscon ASPEED_CLK_APB>;
618 resets = <&syscon ASPEED_RESET_I2C>;
619 bus-frequency = <100000>;
620 interrupts = <1>;
621 interrupt-parent = <&i2c_ic>;
622 status = "disabled";
623 /* Does not need pinctrl properties */
624 };
625
626 i2c2: i2c-bus@c0 {
627 #address-cells = <1>;
628 #size-cells = <0>;
629 #interrupt-cells = <1>;
630
631 reg = <0xc0 0x40>;
632 compatible = "aspeed,ast2500-i2c-bus";
633 clocks = <&syscon ASPEED_CLK_APB>;
634 resets = <&syscon ASPEED_RESET_I2C>;
635 bus-frequency = <100000>;
636 interrupts = <2>;
637 interrupt-parent = <&i2c_ic>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&pinctrl_i2c3_default>;
640 status = "disabled";
641 };
642
643 i2c3: i2c-bus@100 {
644 #address-cells = <1>;
645 #size-cells = <0>;
646 #interrupt-cells = <1>;
647
648 reg = <0x100 0x40>;
649 compatible = "aspeed,ast2500-i2c-bus";
650 clocks = <&syscon ASPEED_CLK_APB>;
651 resets = <&syscon ASPEED_RESET_I2C>;
652 bus-frequency = <100000>;
653 interrupts = <3>;
654 interrupt-parent = <&i2c_ic>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&pinctrl_i2c4_default>;
657 status = "disabled";
658 };
659
660 i2c4: i2c-bus@140 {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 #interrupt-cells = <1>;
664
665 reg = <0x140 0x40>;
666 compatible = "aspeed,ast2500-i2c-bus";
667 clocks = <&syscon ASPEED_CLK_APB>;
668 resets = <&syscon ASPEED_RESET_I2C>;
669 bus-frequency = <100000>;
670 interrupts = <4>;
671 interrupt-parent = <&i2c_ic>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&pinctrl_i2c5_default>;
674 status = "disabled";
675 };
676
677 i2c5: i2c-bus@180 {
678 #address-cells = <1>;
679 #size-cells = <0>;
680 #interrupt-cells = <1>;
681
682 reg = <0x180 0x40>;
683 compatible = "aspeed,ast2500-i2c-bus";
684 clocks = <&syscon ASPEED_CLK_APB>;
685 resets = <&syscon ASPEED_RESET_I2C>;
686 bus-frequency = <100000>;
687 interrupts = <5>;
688 interrupt-parent = <&i2c_ic>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&pinctrl_i2c6_default>;
691 status = "disabled";
692 };
693
694 i2c6: i2c-bus@1c0 {
695 #address-cells = <1>;
696 #size-cells = <0>;
697 #interrupt-cells = <1>;
698
699 reg = <0x1c0 0x40>;
700 compatible = "aspeed,ast2500-i2c-bus";
701 clocks = <&syscon ASPEED_CLK_APB>;
702 resets = <&syscon ASPEED_RESET_I2C>;
703 bus-frequency = <100000>;
704 interrupts = <6>;
705 interrupt-parent = <&i2c_ic>;
706 pinctrl-names = "default";
707 pinctrl-0 = <&pinctrl_i2c7_default>;
708 status = "disabled";
709 };
710
711 i2c7: i2c-bus@300 {
712 #address-cells = <1>;
713 #size-cells = <0>;
714 #interrupt-cells = <1>;
715
716 reg = <0x300 0x40>;
717 compatible = "aspeed,ast2500-i2c-bus";
718 clocks = <&syscon ASPEED_CLK_APB>;
719 resets = <&syscon ASPEED_RESET_I2C>;
720 bus-frequency = <100000>;
721 interrupts = <7>;
722 interrupt-parent = <&i2c_ic>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&pinctrl_i2c8_default>;
725 status = "disabled";
726 };
727
728 i2c8: i2c-bus@340 {
729 #address-cells = <1>;
730 #size-cells = <0>;
731 #interrupt-cells = <1>;
732
733 reg = <0x340 0x40>;
734 compatible = "aspeed,ast2500-i2c-bus";
735 clocks = <&syscon ASPEED_CLK_APB>;
736 resets = <&syscon ASPEED_RESET_I2C>;
737 bus-frequency = <100000>;
738 interrupts = <8>;
739 interrupt-parent = <&i2c_ic>;
740 pinctrl-names = "default";
741 pinctrl-0 = <&pinctrl_i2c9_default>;
742 status = "disabled";
743 };
744
745 i2c9: i2c-bus@380 {
746 #address-cells = <1>;
747 #size-cells = <0>;
748 #interrupt-cells = <1>;
749
750 reg = <0x380 0x40>;
751 compatible = "aspeed,ast2500-i2c-bus";
752 clocks = <&syscon ASPEED_CLK_APB>;
753 resets = <&syscon ASPEED_RESET_I2C>;
754 bus-frequency = <100000>;
755 interrupts = <9>;
756 interrupt-parent = <&i2c_ic>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_i2c10_default>;
759 status = "disabled";
760 };
761
762 i2c10: i2c-bus@3c0 {
763 #address-cells = <1>;
764 #size-cells = <0>;
765 #interrupt-cells = <1>;
766
767 reg = <0x3c0 0x40>;
768 compatible = "aspeed,ast2500-i2c-bus";
769 clocks = <&syscon ASPEED_CLK_APB>;
770 resets = <&syscon ASPEED_RESET_I2C>;
771 bus-frequency = <100000>;
772 interrupts = <10>;
773 interrupt-parent = <&i2c_ic>;
774 pinctrl-names = "default";
775 pinctrl-0 = <&pinctrl_i2c11_default>;
776 status = "disabled";
777 };
778
779 i2c11: i2c-bus@400 {
780 #address-cells = <1>;
781 #size-cells = <0>;
782 #interrupt-cells = <1>;
783
784 reg = <0x400 0x40>;
785 compatible = "aspeed,ast2500-i2c-bus";
786 clocks = <&syscon ASPEED_CLK_APB>;
787 resets = <&syscon ASPEED_RESET_I2C>;
788 bus-frequency = <100000>;
789 interrupts = <11>;
790 interrupt-parent = <&i2c_ic>;
791 pinctrl-names = "default";
792 pinctrl-0 = <&pinctrl_i2c12_default>;
793 status = "disabled";
794 };
795
796 i2c12: i2c-bus@440 {
797 #address-cells = <1>;
798 #size-cells = <0>;
799 #interrupt-cells = <1>;
800
801 reg = <0x440 0x40>;
802 compatible = "aspeed,ast2500-i2c-bus";
803 clocks = <&syscon ASPEED_CLK_APB>;
804 resets = <&syscon ASPEED_RESET_I2C>;
805 bus-frequency = <100000>;
806 interrupts = <12>;
807 interrupt-parent = <&i2c_ic>;
808 pinctrl-names = "default";
809 pinctrl-0 = <&pinctrl_i2c13_default>;
810 status = "disabled";
811 };
812
813 i2c13: i2c-bus@480 {
814 #address-cells = <1>;
815 #size-cells = <0>;
816 #interrupt-cells = <1>;
817
818 reg = <0x480 0x40>;
819 compatible = "aspeed,ast2500-i2c-bus";
820 clocks = <&syscon ASPEED_CLK_APB>;
821 resets = <&syscon ASPEED_RESET_I2C>;
822 bus-frequency = <100000>;
823 interrupts = <13>;
824 interrupt-parent = <&i2c_ic>;
825 pinctrl-names = "default";
826 pinctrl-0 = <&pinctrl_i2c14_default>;
827 status = "disabled";
828 };
829};
830
831&pinctrl {
832 pinctrl_acpi_default: acpi_default {
833 function = "ACPI";
834 groups = "ACPI";
835 };
836
837 pinctrl_adc0_default: adc0_default {
838 function = "ADC0";
839 groups = "ADC0";
840 };
841
842 pinctrl_adc1_default: adc1_default {
843 function = "ADC1";
844 groups = "ADC1";
845 };
846
847 pinctrl_adc10_default: adc10_default {
848 function = "ADC10";
849 groups = "ADC10";
850 };
851
852 pinctrl_adc11_default: adc11_default {
853 function = "ADC11";
854 groups = "ADC11";
855 };
856
857 pinctrl_adc12_default: adc12_default {
858 function = "ADC12";
859 groups = "ADC12";
860 };
861
862 pinctrl_adc13_default: adc13_default {
863 function = "ADC13";
864 groups = "ADC13";
865 };
866
867 pinctrl_adc14_default: adc14_default {
868 function = "ADC14";
869 groups = "ADC14";
870 };
871
872 pinctrl_adc15_default: adc15_default {
873 function = "ADC15";
874 groups = "ADC15";
875 };
876
877 pinctrl_adc2_default: adc2_default {
878 function = "ADC2";
879 groups = "ADC2";
880 };
881
882 pinctrl_adc3_default: adc3_default {
883 function = "ADC3";
884 groups = "ADC3";
885 };
886
887 pinctrl_adc4_default: adc4_default {
888 function = "ADC4";
889 groups = "ADC4";
890 };
891
892 pinctrl_adc5_default: adc5_default {
893 function = "ADC5";
894 groups = "ADC5";
895 };
896
897 pinctrl_adc6_default: adc6_default {
898 function = "ADC6";
899 groups = "ADC6";
900 };
901
902 pinctrl_adc7_default: adc7_default {
903 function = "ADC7";
904 groups = "ADC7";
905 };
906
907 pinctrl_adc8_default: adc8_default {
908 function = "ADC8";
909 groups = "ADC8";
910 };
911
912 pinctrl_adc9_default: adc9_default {
913 function = "ADC9";
914 groups = "ADC9";
915 };
916
917 pinctrl_bmcint_default: bmcint_default {
918 function = "BMCINT";
919 groups = "BMCINT";
920 };
921
922 pinctrl_ddcclk_default: ddcclk_default {
923 function = "DDCCLK";
924 groups = "DDCCLK";
925 };
926
927 pinctrl_ddcdat_default: ddcdat_default {
928 function = "DDCDAT";
929 groups = "DDCDAT";
930 };
931
932 pinctrl_espi_default: espi_default {
933 function = "ESPI";
934 groups = "ESPI";
935 };
936
937 pinctrl_fwspics1_default: fwspics1_default {
938 function = "FWSPICS1";
939 groups = "FWSPICS1";
940 };
941
942 pinctrl_fwspics2_default: fwspics2_default {
943 function = "FWSPICS2";
944 groups = "FWSPICS2";
945 };
946
947 pinctrl_gpid0_default: gpid0_default {
948 function = "GPID0";
949 groups = "GPID0";
950 };
951
952 pinctrl_gpid2_default: gpid2_default {
953 function = "GPID2";
954 groups = "GPID2";
955 };
956
957 pinctrl_gpid4_default: gpid4_default {
958 function = "GPID4";
959 groups = "GPID4";
960 };
961
962 pinctrl_gpid6_default: gpid6_default {
963 function = "GPID6";
964 groups = "GPID6";
965 };
966
967 pinctrl_gpie0_default: gpie0_default {
968 function = "GPIE0";
969 groups = "GPIE0";
970 };
971
972 pinctrl_gpie2_default: gpie2_default {
973 function = "GPIE2";
974 groups = "GPIE2";
975 };
976
977 pinctrl_gpie4_default: gpie4_default {
978 function = "GPIE4";
979 groups = "GPIE4";
980 };
981
982 pinctrl_gpie6_default: gpie6_default {
983 function = "GPIE6";
984 groups = "GPIE6";
985 };
986
987 pinctrl_i2c10_default: i2c10_default {
988 function = "I2C10";
989 groups = "I2C10";
990 };
991
992 pinctrl_i2c11_default: i2c11_default {
993 function = "I2C11";
994 groups = "I2C11";
995 };
996
997 pinctrl_i2c12_default: i2c12_default {
998 function = "I2C12";
999 groups = "I2C12";
1000 };
1001
1002 pinctrl_i2c13_default: i2c13_default {
1003 function = "I2C13";
1004 groups = "I2C13";
1005 };
1006
1007 pinctrl_i2c14_default: i2c14_default {
1008 function = "I2C14";
1009 groups = "I2C14";
1010 };
1011
1012 pinctrl_i2c3_default: i2c3_default {
1013 function = "I2C3";
1014 groups = "I2C3";
1015 };
1016
1017 pinctrl_i2c4_default: i2c4_default {
1018 function = "I2C4";
1019 groups = "I2C4";
1020 };
1021
1022 pinctrl_i2c5_default: i2c5_default {
1023 function = "I2C5";
1024 groups = "I2C5";
1025 };
1026
1027 pinctrl_i2c6_default: i2c6_default {
1028 function = "I2C6";
1029 groups = "I2C6";
1030 };
1031
1032 pinctrl_i2c7_default: i2c7_default {
1033 function = "I2C7";
1034 groups = "I2C7";
1035 };
1036
1037 pinctrl_i2c8_default: i2c8_default {
1038 function = "I2C8";
1039 groups = "I2C8";
1040 };
1041
1042 pinctrl_i2c9_default: i2c9_default {
1043 function = "I2C9";
1044 groups = "I2C9";
1045 };
1046
1047 pinctrl_lad0_default: lad0_default {
1048 function = "LAD0";
1049 groups = "LAD0";
1050 };
1051
1052 pinctrl_lad1_default: lad1_default {
1053 function = "LAD1";
1054 groups = "LAD1";
1055 };
1056
1057 pinctrl_lad2_default: lad2_default {
1058 function = "LAD2";
1059 groups = "LAD2";
1060 };
1061
1062 pinctrl_lad3_default: lad3_default {
1063 function = "LAD3";
1064 groups = "LAD3";
1065 };
1066
1067 pinctrl_lclk_default: lclk_default {
1068 function = "LCLK";
1069 groups = "LCLK";
1070 };
1071
1072 pinctrl_lframe_default: lframe_default {
1073 function = "LFRAME";
1074 groups = "LFRAME";
1075 };
1076
1077 pinctrl_lpchc_default: lpchc_default {
1078 function = "LPCHC";
1079 groups = "LPCHC";
1080 };
1081
1082 pinctrl_lpcpd_default: lpcpd_default {
1083 function = "LPCPD";
1084 groups = "LPCPD";
1085 };
1086
1087 pinctrl_lpcplus_default: lpcplus_default {
1088 function = "LPCPLUS";
1089 groups = "LPCPLUS";
1090 };
1091
1092 pinctrl_lpcpme_default: lpcpme_default {
1093 function = "LPCPME";
1094 groups = "LPCPME";
1095 };
1096
1097 pinctrl_lpcrst_default: lpcrst_default {
1098 function = "LPCRST";
1099 groups = "LPCRST";
1100 };
1101
1102 pinctrl_lpcsmi_default: lpcsmi_default {
1103 function = "LPCSMI";
1104 groups = "LPCSMI";
1105 };
1106
1107 pinctrl_lsirq_default: lsirq_default {
1108 function = "LSIRQ";
1109 groups = "LSIRQ";
1110 };
1111
1112 pinctrl_mac1link_default: mac1link_default {
1113 function = "MAC1LINK";
1114 groups = "MAC1LINK";
1115 };
1116
1117 pinctrl_mac2link_default: mac2link_default {
1118 function = "MAC2LINK";
1119 groups = "MAC2LINK";
1120 };
1121
1122 pinctrl_mdio1_default: mdio1_default {
1123 function = "MDIO1";
1124 groups = "MDIO1";
1125 };
1126
1127 pinctrl_mdio2_default: mdio2_default {
1128 function = "MDIO2";
1129 groups = "MDIO2";
1130 };
1131
1132 pinctrl_ncts1_default: ncts1_default {
1133 function = "NCTS1";
1134 groups = "NCTS1";
1135 };
1136
1137 pinctrl_ncts2_default: ncts2_default {
1138 function = "NCTS2";
1139 groups = "NCTS2";
1140 };
1141
1142 pinctrl_ncts3_default: ncts3_default {
1143 function = "NCTS3";
1144 groups = "NCTS3";
1145 };
1146
1147 pinctrl_ncts4_default: ncts4_default {
1148 function = "NCTS4";
1149 groups = "NCTS4";
1150 };
1151
1152 pinctrl_ndcd1_default: ndcd1_default {
1153 function = "NDCD1";
1154 groups = "NDCD1";
1155 };
1156
1157 pinctrl_ndcd2_default: ndcd2_default {
1158 function = "NDCD2";
1159 groups = "NDCD2";
1160 };
1161
1162 pinctrl_ndcd3_default: ndcd3_default {
1163 function = "NDCD3";
1164 groups = "NDCD3";
1165 };
1166
1167 pinctrl_ndcd4_default: ndcd4_default {
1168 function = "NDCD4";
1169 groups = "NDCD4";
1170 };
1171
1172 pinctrl_ndsr1_default: ndsr1_default {
1173 function = "NDSR1";
1174 groups = "NDSR1";
1175 };
1176
1177 pinctrl_ndsr2_default: ndsr2_default {
1178 function = "NDSR2";
1179 groups = "NDSR2";
1180 };
1181
1182 pinctrl_ndsr3_default: ndsr3_default {
1183 function = "NDSR3";
1184 groups = "NDSR3";
1185 };
1186
1187 pinctrl_ndsr4_default: ndsr4_default {
1188 function = "NDSR4";
1189 groups = "NDSR4";
1190 };
1191
1192 pinctrl_ndtr1_default: ndtr1_default {
1193 function = "NDTR1";
1194 groups = "NDTR1";
1195 };
1196
1197 pinctrl_ndtr2_default: ndtr2_default {
1198 function = "NDTR2";
1199 groups = "NDTR2";
1200 };
1201
1202 pinctrl_ndtr3_default: ndtr3_default {
1203 function = "NDTR3";
1204 groups = "NDTR3";
1205 };
1206
1207 pinctrl_ndtr4_default: ndtr4_default {
1208 function = "NDTR4";
1209 groups = "NDTR4";
1210 };
1211
1212 pinctrl_nri1_default: nri1_default {
1213 function = "NRI1";
1214 groups = "NRI1";
1215 };
1216
1217 pinctrl_nri2_default: nri2_default {
1218 function = "NRI2";
1219 groups = "NRI2";
1220 };
1221
1222 pinctrl_nri3_default: nri3_default {
1223 function = "NRI3";
1224 groups = "NRI3";
1225 };
1226
1227 pinctrl_nri4_default: nri4_default {
1228 function = "NRI4";
1229 groups = "NRI4";
1230 };
1231
1232 pinctrl_nrts1_default: nrts1_default {
1233 function = "NRTS1";
1234 groups = "NRTS1";
1235 };
1236
1237 pinctrl_nrts2_default: nrts2_default {
1238 function = "NRTS2";
1239 groups = "NRTS2";
1240 };
1241
1242 pinctrl_nrts3_default: nrts3_default {
1243 function = "NRTS3";
1244 groups = "NRTS3";
1245 };
1246
1247 pinctrl_nrts4_default: nrts4_default {
1248 function = "NRTS4";
1249 groups = "NRTS4";
1250 };
1251
1252 pinctrl_oscclk_default: oscclk_default {
1253 function = "OSCCLK";
1254 groups = "OSCCLK";
1255 };
1256
1257 pinctrl_pewake_default: pewake_default {
1258 function = "PEWAKE";
1259 groups = "PEWAKE";
1260 };
1261
1262 pinctrl_pnor_default: pnor_default {
1263 function = "PNOR";
1264 groups = "PNOR";
1265 };
1266
1267 pinctrl_pwm0_default: pwm0_default {
1268 function = "PWM0";
1269 groups = "PWM0";
1270 };
1271
1272 pinctrl_pwm1_default: pwm1_default {
1273 function = "PWM1";
1274 groups = "PWM1";
1275 };
1276
1277 pinctrl_pwm2_default: pwm2_default {
1278 function = "PWM2";
1279 groups = "PWM2";
1280 };
1281
1282 pinctrl_pwm3_default: pwm3_default {
1283 function = "PWM3";
1284 groups = "PWM3";
1285 };
1286
1287 pinctrl_pwm4_default: pwm4_default {
1288 function = "PWM4";
1289 groups = "PWM4";
1290 };
1291
1292 pinctrl_pwm5_default: pwm5_default {
1293 function = "PWM5";
1294 groups = "PWM5";
1295 };
1296
1297 pinctrl_pwm6_default: pwm6_default {
1298 function = "PWM6";
1299 groups = "PWM6";
1300 };
1301
1302 pinctrl_pwm7_default: pwm7_default {
1303 function = "PWM7";
1304 groups = "PWM7";
1305 };
1306
1307 pinctrl_rgmii1_default: rgmii1_default {
1308 function = "RGMII1";
1309 groups = "RGMII1";
1310 };
1311
1312 pinctrl_rgmii2_default: rgmii2_default {
1313 function = "RGMII2";
1314 groups = "RGMII2";
1315 };
1316
1317 pinctrl_rmii1_default: rmii1_default {
1318 function = "RMII1";
1319 groups = "RMII1";
1320 };
1321
1322 pinctrl_rmii2_default: rmii2_default {
1323 function = "RMII2";
1324 groups = "RMII2";
1325 };
1326
1327 pinctrl_rxd1_default: rxd1_default {
1328 function = "RXD1";
1329 groups = "RXD1";
1330 };
1331
1332 pinctrl_rxd2_default: rxd2_default {
1333 function = "RXD2";
1334 groups = "RXD2";
1335 };
1336
1337 pinctrl_rxd3_default: rxd3_default {
1338 function = "RXD3";
1339 groups = "RXD3";
1340 };
1341
1342 pinctrl_rxd4_default: rxd4_default {
1343 function = "RXD4";
1344 groups = "RXD4";
1345 };
1346
1347 pinctrl_salt1_default: salt1_default {
1348 function = "SALT1";
1349 groups = "SALT1";
1350 };
1351
1352 pinctrl_salt10_default: salt10_default {
1353 function = "SALT10";
1354 groups = "SALT10";
1355 };
1356
1357 pinctrl_salt11_default: salt11_default {
1358 function = "SALT11";
1359 groups = "SALT11";
1360 };
1361
1362 pinctrl_salt12_default: salt12_default {
1363 function = "SALT12";
1364 groups = "SALT12";
1365 };
1366
1367 pinctrl_salt13_default: salt13_default {
1368 function = "SALT13";
1369 groups = "SALT13";
1370 };
1371
1372 pinctrl_salt14_default: salt14_default {
1373 function = "SALT14";
1374 groups = "SALT14";
1375 };
1376
1377 pinctrl_salt2_default: salt2_default {
1378 function = "SALT2";
1379 groups = "SALT2";
1380 };
1381
1382 pinctrl_salt3_default: salt3_default {
1383 function = "SALT3";
1384 groups = "SALT3";
1385 };
1386
1387 pinctrl_salt4_default: salt4_default {
1388 function = "SALT4";
1389 groups = "SALT4";
1390 };
1391
1392 pinctrl_salt5_default: salt5_default {
1393 function = "SALT5";
1394 groups = "SALT5";
1395 };
1396
1397 pinctrl_salt6_default: salt6_default {
1398 function = "SALT6";
1399 groups = "SALT6";
1400 };
1401
1402 pinctrl_salt7_default: salt7_default {
1403 function = "SALT7";
1404 groups = "SALT7";
1405 };
1406
1407 pinctrl_salt8_default: salt8_default {
1408 function = "SALT8";
1409 groups = "SALT8";
1410 };
1411
1412 pinctrl_salt9_default: salt9_default {
1413 function = "SALT9";
1414 groups = "SALT9";
1415 };
1416
1417 pinctrl_scl1_default: scl1_default {
1418 function = "SCL1";
1419 groups = "SCL1";
1420 };
1421
1422 pinctrl_scl2_default: scl2_default {
1423 function = "SCL2";
1424 groups = "SCL2";
1425 };
1426
1427 pinctrl_sd1_default: sd1_default {
1428 function = "SD1";
1429 groups = "SD1";
1430 };
1431
1432 pinctrl_sd2_default: sd2_default {
1433 function = "SD2";
1434 groups = "SD2";
1435 };
1436
1437 pinctrl_sda1_default: sda1_default {
1438 function = "SDA1";
1439 groups = "SDA1";
1440 };
1441
1442 pinctrl_sda2_default: sda2_default {
1443 function = "SDA2";
1444 groups = "SDA2";
1445 };
1446
1447 pinctrl_sgpm_default: sgpm_default {
1448 function = "SGPM";
1449 groups = "SGPM";
1450 };
1451
1452 pinctrl_sgps1_default: sgps1_default {
1453 function = "SGPS1";
1454 groups = "SGPS1";
1455 };
1456
1457 pinctrl_sgps2_default: sgps2_default {
1458 function = "SGPS2";
1459 groups = "SGPS2";
1460 };
1461
1462 pinctrl_sioonctrl_default: sioonctrl_default {
1463 function = "SIOONCTRL";
1464 groups = "SIOONCTRL";
1465 };
1466
1467 pinctrl_siopbi_default: siopbi_default {
1468 function = "SIOPBI";
1469 groups = "SIOPBI";
1470 };
1471
1472 pinctrl_siopbo_default: siopbo_default {
1473 function = "SIOPBO";
1474 groups = "SIOPBO";
1475 };
1476
1477 pinctrl_siopwreq_default: siopwreq_default {
1478 function = "SIOPWREQ";
1479 groups = "SIOPWREQ";
1480 };
1481
1482 pinctrl_siopwrgd_default: siopwrgd_default {
1483 function = "SIOPWRGD";
1484 groups = "SIOPWRGD";
1485 };
1486
1487 pinctrl_sios3_default: sios3_default {
1488 function = "SIOS3";
1489 groups = "SIOS3";
1490 };
1491
1492 pinctrl_sios5_default: sios5_default {
1493 function = "SIOS5";
1494 groups = "SIOS5";
1495 };
1496
1497 pinctrl_siosci_default: siosci_default {
1498 function = "SIOSCI";
1499 groups = "SIOSCI";
1500 };
1501
1502 pinctrl_spi1_default: spi1_default {
1503 function = "SPI1";
1504 groups = "SPI1";
1505 };
1506
1507 pinctrl_spi1cs1_default: spi1cs1_default {
1508 function = "SPI1CS1";
1509 groups = "SPI1CS1";
1510 };
1511
1512 pinctrl_spi1debug_default: spi1debug_default {
1513 function = "SPI1DEBUG";
1514 groups = "SPI1DEBUG";
1515 };
1516
1517 pinctrl_spi1passthru_default: spi1passthru_default {
1518 function = "SPI1PASSTHRU";
1519 groups = "SPI1PASSTHRU";
1520 };
1521
1522 pinctrl_spi2ck_default: spi2ck_default {
1523 function = "SPI2CK";
1524 groups = "SPI2CK";
1525 };
1526
1527 pinctrl_spi2cs0_default: spi2cs0_default {
1528 function = "SPI2CS0";
1529 groups = "SPI2CS0";
1530 };
1531
1532 pinctrl_spi2cs1_default: spi2cs1_default {
1533 function = "SPI2CS1";
1534 groups = "SPI2CS1";
1535 };
1536
1537 pinctrl_spi2miso_default: spi2miso_default {
1538 function = "SPI2MISO";
1539 groups = "SPI2MISO";
1540 };
1541
1542 pinctrl_spi2mosi_default: spi2mosi_default {
1543 function = "SPI2MOSI";
1544 groups = "SPI2MOSI";
1545 };
1546
1547 pinctrl_timer3_default: timer3_default {
1548 function = "TIMER3";
1549 groups = "TIMER3";
1550 };
1551
1552 pinctrl_timer4_default: timer4_default {
1553 function = "TIMER4";
1554 groups = "TIMER4";
1555 };
1556
1557 pinctrl_timer5_default: timer5_default {
1558 function = "TIMER5";
1559 groups = "TIMER5";
1560 };
1561
1562 pinctrl_timer6_default: timer6_default {
1563 function = "TIMER6";
1564 groups = "TIMER6";
1565 };
1566
1567 pinctrl_timer7_default: timer7_default {
1568 function = "TIMER7";
1569 groups = "TIMER7";
1570 };
1571
1572 pinctrl_timer8_default: timer8_default {
1573 function = "TIMER8";
1574 groups = "TIMER8";
1575 };
1576
1577 pinctrl_txd1_default: txd1_default {
1578 function = "TXD1";
1579 groups = "TXD1";
1580 };
1581
1582 pinctrl_txd2_default: txd2_default {
1583 function = "TXD2";
1584 groups = "TXD2";
1585 };
1586
1587 pinctrl_txd3_default: txd3_default {
1588 function = "TXD3";
1589 groups = "TXD3";
1590 };
1591
1592 pinctrl_txd4_default: txd4_default {
1593 function = "TXD4";
1594 groups = "TXD4";
1595 };
1596
1597 pinctrl_uart6_default: uart6_default {
1598 function = "UART6";
1599 groups = "UART6";
1600 };
1601
1602 pinctrl_usbcki_default: usbcki_default {
1603 function = "USBCKI";
1604 groups = "USBCKI";
1605 };
1606
1607 pinctrl_usb2ah_default: usb2ah_default {
1608 function = "USB2AH";
1609 groups = "USB2AH";
1610 };
1611
1612 pinctrl_usb2ad_default: usb2ad_default {
1613 function = "USB2AD";
1614 groups = "USB2AD";
1615 };
1616
1617 pinctrl_usb11bhid_default: usb11bhid_default {
1618 function = "USB11BHID";
1619 groups = "USB11BHID";
1620 };
1621
1622 pinctrl_usb2bh_default: usb2bh_default {
1623 function = "USB2BH";
1624 groups = "USB2BH";
1625 };
1626
1627 pinctrl_vgabiosrom_default: vgabiosrom_default {
1628 function = "VGABIOSROM";
1629 groups = "VGABIOSROM";
1630 };
1631
1632 pinctrl_vgahs_default: vgahs_default {
1633 function = "VGAHS";
1634 groups = "VGAHS";
1635 };
1636
1637 pinctrl_vgavs_default: vgavs_default {
1638 function = "VGAVS";
1639 groups = "VGAVS";
1640 };
1641
1642 pinctrl_vpi24_default: vpi24_default {
1643 function = "VPI24";
1644 groups = "VPI24";
1645 };
1646
1647 pinctrl_vpo_default: vpo_default {
1648 function = "VPO";
1649 groups = "VPO";
1650 };
1651
1652 pinctrl_wdtrst1_default: wdtrst1_default {
1653 function = "WDTRST1";
1654 groups = "WDTRST1";
1655 };
1656
1657 pinctrl_wdtrst2_default: wdtrst2_default {
1658 function = "WDTRST2";
1659 groups = "WDTRST2";
1660 };
1661};