Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
4 */
5/dts-v1/;
6
7#include "am33xx.dtsi"
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 model = "TI AM335x EVM";
12 compatible = "ti,am335x-evm", "ti,am33xx";
13
14 cpus {
15 cpu@0 {
16 cpu0-supply = <&vdd1_reg>;
17 };
18 };
19
20 memory@80000000 {
21 device_type = "memory";
22 reg = <0x80000000 0x10000000>; /* 256 MB */
23 };
24
25 chosen {
26 stdout-path = &uart0;
27 };
28
29 vbat: fixedregulator0 {
30 compatible = "regulator-fixed";
31 regulator-name = "vbat";
32 regulator-min-microvolt = <5000000>;
33 regulator-max-microvolt = <5000000>;
34 regulator-boot-on;
35 };
36
37 lis3_reg: fixedregulator1 {
38 compatible = "regulator-fixed";
39 regulator-name = "lis3_reg";
40 regulator-boot-on;
41 };
42
43 wlan_en_reg: fixedregulator2 {
44 compatible = "regulator-fixed";
45 regulator-name = "wlan-en-regulator";
46 regulator-min-microvolt = <1800000>;
47 regulator-max-microvolt = <1800000>;
48
49 /* WLAN_EN GPIO for this board - Bank1, pin16 */
50 gpio = <&gpio1 16 0>;
51
52 /* WLAN card specific delay */
53 startup-delay-us = <70000>;
54 enable-active-high;
55 };
56
57 /* TPS79501 */
58 v1_8d_reg: fixedregulator-v1_8d {
59 compatible = "regulator-fixed";
60 regulator-name = "v1_8d";
61 vin-supply = <&vbat>;
62 regulator-min-microvolt = <1800000>;
63 regulator-max-microvolt = <1800000>;
64 };
65
66 /* TPS79501 */
67 v3_3d_reg: fixedregulator-v3_3d {
68 compatible = "regulator-fixed";
69 regulator-name = "v3_3d";
70 vin-supply = <&vbat>;
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 };
74
75 matrix_keypad: matrix_keypad0 {
76 compatible = "gpio-matrix-keypad";
77 debounce-delay-ms = <5>;
78 col-scan-delay-us = <2>;
79
80 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
81 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
82 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
83
84 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
85 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
86
87 linux,keymap = <0x0000008b /* MENU */
88 0x0100009e /* BACK */
89 0x02000069 /* LEFT */
90 0x0001006a /* RIGHT */
91 0x0101001c /* ENTER */
92 0x0201006c>; /* DOWN */
93 };
94
95 gpio_keys: volume-keys {
96 compatible = "gpio-keys";
97 autorepeat;
98
99 switch-9 {
100 label = "volume-up";
101 linux,code = <115>;
102 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
103 wakeup-source;
104 };
105
106 switch-10 {
107 label = "volume-down";
108 linux,code = <114>;
109 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
110 wakeup-source;
111 };
112 };
113
114 backlight: backlight {
115 compatible = "pwm-backlight";
116 pwms = <&ecap0 0 50000 0>;
117 brightness-levels = <0 51 53 56 62 75 101 152 255>;
118 default-brightness-level = <8>;
119 };
120
121 panel {
122 compatible = "tfc,s9700rtwv43tr-01b";
123
124 pinctrl-names = "default";
125 pinctrl-0 = <&lcd_pins_s0>;
126 backlight = <&backlight>;
127
128 port {
129 panel_0: endpoint {
130 remote-endpoint = <&lcdc_0>;
131 };
132 };
133 };
134
135 sound {
136 compatible = "simple-audio-card";
137 simple-audio-card,name = "AM335x-EVM";
138 simple-audio-card,widgets =
139 "Headphone", "Headphone Jack",
140 "Line", "Line In";
141 simple-audio-card,routing =
142 "Headphone Jack", "HPLOUT",
143 "Headphone Jack", "HPROUT",
144 "LINE1L", "Line In",
145 "LINE1R", "Line In";
146 simple-audio-card,format = "dsp_b";
147 simple-audio-card,bitclock-master = <&sound_master>;
148 simple-audio-card,frame-master = <&sound_master>;
149 simple-audio-card,bitclock-inversion;
150
151 simple-audio-card,cpu {
152 sound-dai = <&mcasp1>;
153 };
154
155 sound_master: simple-audio-card,codec {
156 sound-dai = <&tlv320aic3106>;
157 system-clock-frequency = <12000000>;
158 };
159 };
160};
161
162&am33xx_pinmux {
163 pinctrl-names = "default";
164 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
165
166 matrix_keypad_s0: matrix_keypad_s0 {
167 pinctrl-single,pins = <
168 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */
169 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */
170 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */
171 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */
172 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */
173 >;
174 };
175
176 volume_keys_s0: volume_keys_s0 {
177 pinctrl-single,pins = <
178 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */
179 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */
180 >;
181 };
182
183 i2c0_pins: pinmux_i2c0_pins {
184 pinctrl-single,pins = <
185 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */
186 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */
187 >;
188 };
189
190 i2c1_pins: pinmux_i2c1_pins {
191 pinctrl-single,pins = <
192 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */
193 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */
194 >;
195 };
196
197 uart0_pins: pinmux_uart0_pins {
198 pinctrl-single,pins = <
199 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
200 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
201 >;
202 };
203
204 uart1_pins: pinmux_uart1_pins {
205 pinctrl-single,pins = <
206 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
207 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
208 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
209 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
210 >;
211 };
212
213 clkout2_pin: pinmux_clkout2_pin {
214 pinctrl-single,pins = <
215 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */
216 >;
217 };
218
219 nandflash_pins_s0: nandflash_pins_s0 {
220 pinctrl-single,pins = <
221 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
222 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
223 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
224 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
225 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
226 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
227 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
228 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
229 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
230 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
231 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
232 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
233 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
234 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
235 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
236 >;
237 };
238
239 ecap0_pins: backlight_pins {
240 pinctrl-single,pins = <
241 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)
242 >;
243 };
244
245 cpsw_default: cpsw_default {
246 pinctrl-single,pins = <
247 /* Slave 1 */
248 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */
249 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
250 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
251 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
252 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
253 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
254 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
255 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
256 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
257 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
258 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
259 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
260 >;
261 };
262
263 cpsw_sleep: cpsw_sleep {
264 pinctrl-single,pins = <
265 /* Slave 1 reset value */
266 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
267 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
268 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
269 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
270 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
271 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
272 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
273 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
274 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
275 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
276 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
277 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
278 >;
279 };
280
281 davinci_mdio_default: davinci_mdio_default {
282 pinctrl-single,pins = <
283 /* MDIO */
284 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
285 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
286 >;
287 };
288
289 davinci_mdio_sleep: davinci_mdio_sleep {
290 pinctrl-single,pins = <
291 /* MDIO reset value */
292 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
293 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
294 >;
295 };
296
297 mmc1_pins: pinmux_mmc1_pins {
298 pinctrl-single,pins = <
299 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */
300 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
301 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
302 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
303 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
304 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
305 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
306 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
307 >;
308 };
309
310 mmc3_pins: pinmux_mmc3_pins {
311 pinctrl-single,pins = <
312 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
313 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
314 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
315 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
316 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
317 AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
318 >;
319 };
320
321 wlan_pins: pinmux_wlan_pins {
322 pinctrl-single,pins = <
323 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */
324 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
325 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
326 >;
327 };
328
329 lcd_pins_s0: lcd_pins_s0 {
330 pinctrl-single,pins = <
331 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */
332 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */
333 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */
334 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */
335 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */
336 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */
337 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */
338 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */
339 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
340 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
341 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
342 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
343 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
344 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
345 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
346 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
347 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
348 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
349 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
350 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
351 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
352 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
353 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
354 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
355 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
356 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
357 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
358 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
359 >;
360 };
361
362 mcasp1_pins: mcasp1_pins {
363 pinctrl-single,pins = <
364 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
365 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
366 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
367 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
368 >;
369 };
370
371 mcasp1_pins_sleep: mcasp1_pins_sleep {
372 pinctrl-single,pins = <
373 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
374 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
375 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
376 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
377 >;
378 };
379
380 dcan1_pins_default: dcan1_pins_default {
381 pinctrl-single,pins = <
382 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
383 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
384 >;
385 };
386};
387
388&uart0 {
389 pinctrl-names = "default";
390 pinctrl-0 = <&uart0_pins>;
391
392 status = "okay";
393};
394
395&uart1 {
396 pinctrl-names = "default";
397 pinctrl-0 = <&uart1_pins>;
398
399 status = "okay";
400};
401
402&i2c0 {
403 pinctrl-names = "default";
404 pinctrl-0 = <&i2c0_pins>;
405
406 status = "okay";
407 clock-frequency = <400000>;
408
409 tps: tps@2d {
410 reg = <0x2d>;
411 };
412};
413
414&usb1 {
415 dr_mode = "host";
416};
417
418&i2c1 {
419 pinctrl-names = "default";
420 pinctrl-0 = <&i2c1_pins>;
421
422 status = "okay";
423 clock-frequency = <100000>;
424
425 lis331dlh: lis331dlh@18 {
426 compatible = "st,lis331dlh", "st,lis3lv02d";
427 reg = <0x18>;
428 Vdd-supply = <&lis3_reg>;
429 Vdd_IO-supply = <&lis3_reg>;
430
431 st,click-single-x;
432 st,click-single-y;
433 st,click-single-z;
434 st,click-thresh-x = <10>;
435 st,click-thresh-y = <10>;
436 st,click-thresh-z = <10>;
437 st,irq1-click;
438 st,irq2-click;
439 st,wakeup-x-lo;
440 st,wakeup-x-hi;
441 st,wakeup-y-lo;
442 st,wakeup-y-hi;
443 st,wakeup-z-lo;
444 st,wakeup-z-hi;
445 st,min-limit-x = <120>;
446 st,min-limit-y = <120>;
447 st,min-limit-z = <140>;
448 st,max-limit-x = <550>;
449 st,max-limit-y = <550>;
450 st,max-limit-z = <750>;
451 };
452
453 tsl2550: tsl2550@39 {
454 compatible = "taos,tsl2550";
455 reg = <0x39>;
456 };
457
458 tmp275: tmp275@48 {
459 compatible = "ti,tmp275";
460 reg = <0x48>;
461 };
462
463 tlv320aic3106: tlv320aic3106@1b {
464 #sound-dai-cells = <0>;
465 compatible = "ti,tlv320aic3106";
466 reg = <0x1b>;
467 status = "okay";
468
469 /* Regulators */
470 AVDD-supply = <&v3_3d_reg>;
471 IOVDD-supply = <&v3_3d_reg>;
472 DRVDD-supply = <&v3_3d_reg>;
473 DVDD-supply = <&v1_8d_reg>;
474 };
475};
476
477&lcdc {
478 status = "okay";
479
480 blue-and-red-wiring = "crossed";
481
482 port {
483 lcdc_0: endpoint@0 {
484 remote-endpoint = <&panel_0>;
485 };
486 };
487};
488
489&elm {
490 status = "okay";
491};
492
493&epwmss0 {
494 status = "okay";
495
496 ecap0: pwm@100 {
497 status = "okay";
498 pinctrl-names = "default";
499 pinctrl-0 = <&ecap0_pins>;
500 };
501};
502
503&gpmc {
504 status = "okay";
505 pinctrl-names = "default";
506 pinctrl-0 = <&nandflash_pins_s0>;
507 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
508 nand@0,0 {
509 compatible = "ti,omap2-nand";
510 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
511 interrupt-parent = <&gpmc>;
512 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
513 <1 IRQ_TYPE_NONE>; /* termcount */
514 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
515 ti,nand-xfer-type = "prefetch-dma";
516 ti,nand-ecc-opt = "bch8";
517 ti,elm-id = <&elm>;
518 nand-bus-width = <8>;
519 gpmc,device-width = <1>;
520 gpmc,sync-clk-ps = <0>;
521 gpmc,cs-on-ns = <0>;
522 gpmc,cs-rd-off-ns = <44>;
523 gpmc,cs-wr-off-ns = <44>;
524 gpmc,adv-on-ns = <6>;
525 gpmc,adv-rd-off-ns = <34>;
526 gpmc,adv-wr-off-ns = <44>;
527 gpmc,we-on-ns = <0>;
528 gpmc,we-off-ns = <40>;
529 gpmc,oe-on-ns = <0>;
530 gpmc,oe-off-ns = <54>;
531 gpmc,access-ns = <64>;
532 gpmc,rd-cycle-ns = <82>;
533 gpmc,wr-cycle-ns = <82>;
534 gpmc,bus-turnaround-ns = <0>;
535 gpmc,cycle2cycle-delay-ns = <0>;
536 gpmc,clk-activation-ns = <0>;
537 gpmc,wr-access-ns = <40>;
538 gpmc,wr-data-mux-bus-ns = <0>;
539 /* MTD partition table */
540 /* All SPL-* partitions are sized to minimal length
541 * which can be independently programmable. For
542 * NAND flash this is equal to size of erase-block */
543 #address-cells = <1>;
544 #size-cells = <1>;
545 partition@0 {
546 label = "NAND.SPL";
547 reg = <0x00000000 0x00020000>;
548 };
549 partition@1 {
550 label = "NAND.SPL.backup1";
551 reg = <0x00020000 0x00020000>;
552 };
553 partition@2 {
554 label = "NAND.SPL.backup2";
555 reg = <0x00040000 0x00020000>;
556 };
557 partition@3 {
558 label = "NAND.SPL.backup3";
559 reg = <0x00060000 0x00020000>;
560 };
561 partition@4 {
562 label = "NAND.u-boot-spl-os";
563 reg = <0x00080000 0x00040000>;
564 };
565 partition@5 {
566 label = "NAND.u-boot";
567 reg = <0x000C0000 0x00100000>;
568 };
569 partition@6 {
570 label = "NAND.u-boot-env";
571 reg = <0x001C0000 0x00020000>;
572 };
573 partition@7 {
574 label = "NAND.u-boot-env.backup1";
575 reg = <0x001E0000 0x00020000>;
576 };
577 partition@8 {
578 label = "NAND.kernel";
579 reg = <0x00200000 0x00800000>;
580 };
581 partition@9 {
582 label = "NAND.file-system";
583 reg = <0x00A00000 0x0F600000>;
584 };
585 };
586};
587
588#include "tps65910.dtsi"
589
590&mcasp1 {
591 #sound-dai-cells = <0>;
592 pinctrl-names = "default", "sleep";
593 pinctrl-0 = <&mcasp1_pins>;
594 pinctrl-1 = <&mcasp1_pins_sleep>;
595
596 status = "okay";
597
598 op-mode = <0>; /* MCASP_IIS_MODE */
599 tdm-slots = <2>;
600 /* 4 serializers */
601 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
602 0 0 1 2
603 >;
604 tx-num-evt = <32>;
605 rx-num-evt = <32>;
606};
607
608&tps {
609 vcc1-supply = <&vbat>;
610 vcc2-supply = <&vbat>;
611 vcc3-supply = <&vbat>;
612 vcc4-supply = <&vbat>;
613 vcc5-supply = <&vbat>;
614 vcc6-supply = <&vbat>;
615 vcc7-supply = <&vbat>;
616 vccio-supply = <&vbat>;
617
618 regulators {
619 vrtc_reg: regulator@0 {
620 regulator-always-on;
621 };
622
623 vio_reg: regulator@1 {
624 regulator-always-on;
625 };
626
627 vdd1_reg: regulator@2 {
628 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
629 regulator-name = "vdd_mpu";
630 regulator-min-microvolt = <912500>;
631 regulator-max-microvolt = <1351500>;
632 regulator-boot-on;
633 regulator-always-on;
634 };
635
636 vdd2_reg: regulator@3 {
637 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
638 regulator-name = "vdd_core";
639 regulator-min-microvolt = <912500>;
640 regulator-max-microvolt = <1150000>;
641 regulator-boot-on;
642 regulator-always-on;
643 };
644
645 vdd3_reg: regulator@4 {
646 regulator-always-on;
647 };
648
649 vdig1_reg: regulator@5 {
650 regulator-always-on;
651 };
652
653 vdig2_reg: regulator@6 {
654 regulator-always-on;
655 };
656
657 vpll_reg: regulator@7 {
658 regulator-always-on;
659 };
660
661 vdac_reg: regulator@8 {
662 regulator-always-on;
663 };
664
665 vaux1_reg: regulator@9 {
666 regulator-always-on;
667 };
668
669 vaux2_reg: regulator@10 {
670 regulator-always-on;
671 };
672
673 vaux33_reg: regulator@11 {
674 regulator-always-on;
675 };
676
677 vmmc_reg: regulator@12 {
678 regulator-min-microvolt = <1800000>;
679 regulator-max-microvolt = <3300000>;
680 regulator-always-on;
681 };
682 };
683};
684
685&mac_sw {
686 pinctrl-names = "default", "sleep";
687 pinctrl-0 = <&cpsw_default>;
688 pinctrl-1 = <&cpsw_sleep>;
689 status = "okay";
690};
691
692&davinci_mdio_sw {
693 pinctrl-names = "default", "sleep";
694 pinctrl-0 = <&davinci_mdio_default>;
695 pinctrl-1 = <&davinci_mdio_sleep>;
696
697 ethphy0: ethernet-phy@0 {
698 reg = <0>;
699 };
700};
701
702&cpsw_port1 {
703 phy-handle = <ðphy0>;
704 phy-mode = "rgmii-id";
705 ti,dual-emac-pvid = <1>;
706};
707
708&cpsw_port2 {
709 status = "disabled";
710};
711
712&tscadc {
713 status = "okay";
714 tsc {
715 ti,wires = <4>;
716 ti,x-plate-resistance = <200>;
717 ti,coordinate-readouts = <5>;
718 ti,wire-config = <0x00 0x11 0x22 0x33>;
719 ti,charge-delay = <0x400>;
720 };
721
722 adc {
723 ti,adc-channels = <4 5 6 7>;
724 };
725};
726
727&mmc1 {
728 status = "okay";
729 vmmc-supply = <&vmmc_reg>;
730 bus-width = <4>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&mmc1_pins>;
733 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
734};
735
736&mmc3 {
737 /* these are on the crossbar and are outlined in the
738 xbar-event-map element */
739 dmas = <&edma_xbar 12 0 1
740 &edma_xbar 13 0 2>;
741 dma-names = "tx", "rx";
742 status = "okay";
743 vmmc-supply = <&wlan_en_reg>;
744 bus-width = <4>;
745 pinctrl-names = "default";
746 pinctrl-0 = <&mmc3_pins &wlan_pins>;
747 non-removable;
748 cap-power-off-card;
749 keep-power-in-suspend;
750
751 #address-cells = <1>;
752 #size-cells = <0>;
753 wlcore: wlcore@0 {
754 compatible = "ti,wl1835";
755 reg = <2>;
756 interrupt-parent = <&gpio3>;
757 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
758 };
759};
760
761&sham {
762 status = "okay";
763};
764
765&aes {
766 status = "okay";
767};
768
769&dcan1 {
770 status = "disabled"; /* Enable only if Profile 1 is selected */
771 pinctrl-names = "default";
772 pinctrl-0 = <&dcan1_pins_default>;
773};
774
775&rtc {
776 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
777 clock-names = "ext-clk", "int-clk";
778};
779
780&pruss_tm {
781 status = "okay";
782};
783
784&wkup_m3_ipc {
785 firmware-name = "am335x-evm-scale-data.bin";
786};
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "am33xx.dtsi"
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 model = "TI AM335x EVM";
15 compatible = "ti,am335x-evm", "ti,am33xx";
16
17 cpus {
18 cpu@0 {
19 cpu0-supply = <&vdd1_reg>;
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x80000000 0x10000000>; /* 256 MB */
26 };
27
28 vbat: fixedregulator@0 {
29 compatible = "regulator-fixed";
30 regulator-name = "vbat";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
33 regulator-boot-on;
34 };
35
36 lis3_reg: fixedregulator@1 {
37 compatible = "regulator-fixed";
38 regulator-name = "lis3_reg";
39 regulator-boot-on;
40 };
41
42 wlan_en_reg: fixedregulator@2 {
43 compatible = "regulator-fixed";
44 regulator-name = "wlan-en-regulator";
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47
48 /* WLAN_EN GPIO for this board - Bank1, pin16 */
49 gpio = <&gpio1 16 0>;
50
51 /* WLAN card specific delay */
52 startup-delay-us = <70000>;
53 enable-active-high;
54 };
55
56 matrix_keypad: matrix_keypad@0 {
57 compatible = "gpio-matrix-keypad";
58 debounce-delay-ms = <5>;
59 col-scan-delay-us = <2>;
60
61 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
62 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
63 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
64
65 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
66 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
67
68 linux,keymap = <0x0000008b /* MENU */
69 0x0100009e /* BACK */
70 0x02000069 /* LEFT */
71 0x0001006a /* RIGHT */
72 0x0101001c /* ENTER */
73 0x0201006c>; /* DOWN */
74 };
75
76 gpio_keys: volume_keys@0 {
77 compatible = "gpio-keys";
78 #address-cells = <1>;
79 #size-cells = <0>;
80 autorepeat;
81
82 switch@9 {
83 label = "volume-up";
84 linux,code = <115>;
85 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
86 wakeup-source;
87 };
88
89 switch@10 {
90 label = "volume-down";
91 linux,code = <114>;
92 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
93 wakeup-source;
94 };
95 };
96
97 backlight {
98 compatible = "pwm-backlight";
99 pwms = <&ecap0 0 50000 0>;
100 brightness-levels = <0 51 53 56 62 75 101 152 255>;
101 default-brightness-level = <8>;
102 };
103
104 panel {
105 compatible = "ti,tilcdc,panel";
106 status = "okay";
107 pinctrl-names = "default";
108 pinctrl-0 = <&lcd_pins_s0>;
109 panel-info {
110 ac-bias = <255>;
111 ac-bias-intrpt = <0>;
112 dma-burst-sz = <16>;
113 bpp = <32>;
114 fdd = <0x80>;
115 sync-edge = <0>;
116 sync-ctrl = <1>;
117 raster-order = <0>;
118 fifo-th = <0>;
119 };
120
121 display-timings {
122 800x480p62 {
123 clock-frequency = <30000000>;
124 hactive = <800>;
125 vactive = <480>;
126 hfront-porch = <39>;
127 hback-porch = <39>;
128 hsync-len = <47>;
129 vback-porch = <29>;
130 vfront-porch = <13>;
131 vsync-len = <2>;
132 hsync-active = <1>;
133 vsync-active = <1>;
134 };
135 };
136 };
137
138 sound {
139 compatible = "simple-audio-card";
140 simple-audio-card,name = "AM335x-EVM";
141 simple-audio-card,widgets =
142 "Headphone", "Headphone Jack",
143 "Line", "Line In";
144 simple-audio-card,routing =
145 "Headphone Jack", "HPLOUT",
146 "Headphone Jack", "HPROUT",
147 "LINE1L", "Line In",
148 "LINE1R", "Line In";
149 simple-audio-card,format = "dsp_b";
150 simple-audio-card,bitclock-master = <&sound_master>;
151 simple-audio-card,frame-master = <&sound_master>;
152 simple-audio-card,bitclock-inversion;
153
154 simple-audio-card,cpu {
155 sound-dai = <&mcasp1>;
156 };
157
158 sound_master: simple-audio-card,codec {
159 sound-dai = <&tlv320aic3106>;
160 system-clock-frequency = <12000000>;
161 };
162 };
163};
164
165&am33xx_pinmux {
166 pinctrl-names = "default";
167 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
168
169 matrix_keypad_s0: matrix_keypad_s0 {
170 pinctrl-single,pins = <
171 AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
172 AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
173 AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
174 AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
175 AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
176 >;
177 };
178
179 volume_keys_s0: volume_keys_s0 {
180 pinctrl-single,pins = <
181 AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
182 AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
183 >;
184 };
185
186 i2c0_pins: pinmux_i2c0_pins {
187 pinctrl-single,pins = <
188 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
189 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
190 >;
191 };
192
193 i2c1_pins: pinmux_i2c1_pins {
194 pinctrl-single,pins = <
195 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
196 AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
197 >;
198 };
199
200 uart0_pins: pinmux_uart0_pins {
201 pinctrl-single,pins = <
202 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
203 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
204 >;
205 };
206
207 uart1_pins: pinmux_uart1_pins {
208 pinctrl-single,pins = <
209 AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
210 AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
211 AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
212 AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
213 >;
214 };
215
216 clkout2_pin: pinmux_clkout2_pin {
217 pinctrl-single,pins = <
218 AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
219 >;
220 };
221
222 nandflash_pins_s0: nandflash_pins_s0 {
223 pinctrl-single,pins = <
224 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
225 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
226 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
227 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
228 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
229 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
230 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
231 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
232 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
233 AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
234 AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
235 AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
236 AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
237 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
238 AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
239 >;
240 };
241
242 ecap0_pins: backlight_pins {
243 pinctrl-single,pins = <
244 AM33XX_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
245 >;
246 };
247
248 cpsw_default: cpsw_default {
249 pinctrl-single,pins = <
250 /* Slave 1 */
251 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
252 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
253 AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
254 AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
255 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
256 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
257 AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
258 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
259 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
260 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
261 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
262 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
263 >;
264 };
265
266 cpsw_sleep: cpsw_sleep {
267 pinctrl-single,pins = <
268 /* Slave 1 reset value */
269 AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
270 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
271 AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
272 AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
273 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
274 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
275 AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
276 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
277 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
278 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
279 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
280 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
281 >;
282 };
283
284 davinci_mdio_default: davinci_mdio_default {
285 pinctrl-single,pins = <
286 /* MDIO */
287 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
288 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
289 >;
290 };
291
292 davinci_mdio_sleep: davinci_mdio_sleep {
293 pinctrl-single,pins = <
294 /* MDIO reset value */
295 AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
296 AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
297 >;
298 };
299
300 mmc1_pins: pinmux_mmc1_pins {
301 pinctrl-single,pins = <
302 AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
303 >;
304 };
305
306 mmc3_pins: pinmux_mmc3_pins {
307 pinctrl-single,pins = <
308 AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
309 AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
310 AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
311 AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
312 AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
313 AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
314 >;
315 };
316
317 wlan_pins: pinmux_wlan_pins {
318 pinctrl-single,pins = <
319 AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
320 AM33XX_IOPAD(0x99c, PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
321 AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
322 >;
323 };
324
325 lcd_pins_s0: lcd_pins_s0 {
326 pinctrl-single,pins = <
327 AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
328 AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
329 AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
330 AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
331 AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
332 AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
333 AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
334 AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
335 AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
336 AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
337 AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
338 AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
339 AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
340 AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
341 AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
342 AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
343 AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
344 AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
345 AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
346 AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
347 AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
348 AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
349 AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
350 AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
351 AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
352 AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
353 AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
354 AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
355 >;
356 };
357
358 mcasp1_pins: mcasp1_pins {
359 pinctrl-single,pins = <
360 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
361 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
362 AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
363 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
364 >;
365 };
366
367 mcasp1_pins_sleep: mcasp1_pins_sleep {
368 pinctrl-single,pins = <
369 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
370 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
371 AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
372 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
373 >;
374 };
375
376 dcan1_pins_default: dcan1_pins_default {
377 pinctrl-single,pins = <
378 AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
379 AM33XX_IOPAD(0x96c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
380 >;
381 };
382};
383
384&uart0 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&uart0_pins>;
387
388 status = "okay";
389};
390
391&uart1 {
392 pinctrl-names = "default";
393 pinctrl-0 = <&uart1_pins>;
394
395 status = "okay";
396};
397
398&i2c0 {
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2c0_pins>;
401
402 status = "okay";
403 clock-frequency = <400000>;
404
405 tps: tps@2d {
406 reg = <0x2d>;
407 };
408};
409
410&usb {
411 status = "okay";
412};
413
414&usb_ctrl_mod {
415 status = "okay";
416};
417
418&usb0_phy {
419 status = "okay";
420};
421
422&usb1_phy {
423 status = "okay";
424};
425
426&usb0 {
427 status = "okay";
428};
429
430&usb1 {
431 status = "okay";
432 dr_mode = "host";
433};
434
435&cppi41dma {
436 status = "okay";
437};
438
439&i2c1 {
440 pinctrl-names = "default";
441 pinctrl-0 = <&i2c1_pins>;
442
443 status = "okay";
444 clock-frequency = <100000>;
445
446 lis331dlh: lis331dlh@18 {
447 compatible = "st,lis331dlh", "st,lis3lv02d";
448 reg = <0x18>;
449 Vdd-supply = <&lis3_reg>;
450 Vdd_IO-supply = <&lis3_reg>;
451
452 st,click-single-x;
453 st,click-single-y;
454 st,click-single-z;
455 st,click-thresh-x = <10>;
456 st,click-thresh-y = <10>;
457 st,click-thresh-z = <10>;
458 st,irq1-click;
459 st,irq2-click;
460 st,wakeup-x-lo;
461 st,wakeup-x-hi;
462 st,wakeup-y-lo;
463 st,wakeup-y-hi;
464 st,wakeup-z-lo;
465 st,wakeup-z-hi;
466 st,min-limit-x = <120>;
467 st,min-limit-y = <120>;
468 st,min-limit-z = <140>;
469 st,max-limit-x = <550>;
470 st,max-limit-y = <550>;
471 st,max-limit-z = <750>;
472 };
473
474 tsl2550: tsl2550@39 {
475 compatible = "taos,tsl2550";
476 reg = <0x39>;
477 };
478
479 tmp275: tmp275@48 {
480 compatible = "ti,tmp275";
481 reg = <0x48>;
482 };
483
484 tlv320aic3106: tlv320aic3106@1b {
485 #sound-dai-cells = <0>;
486 compatible = "ti,tlv320aic3106";
487 reg = <0x1b>;
488 status = "okay";
489
490 /* Regulators */
491 AVDD-supply = <&vaux2_reg>;
492 IOVDD-supply = <&vaux2_reg>;
493 DRVDD-supply = <&vaux2_reg>;
494 DVDD-supply = <&vbat>;
495 };
496};
497
498&lcdc {
499 status = "okay";
500};
501
502&elm {
503 status = "okay";
504};
505
506&epwmss0 {
507 status = "okay";
508
509 ecap0: ecap@48300100 {
510 status = "okay";
511 pinctrl-names = "default";
512 pinctrl-0 = <&ecap0_pins>;
513 };
514};
515
516&gpmc {
517 status = "okay";
518 pinctrl-names = "default";
519 pinctrl-0 = <&nandflash_pins_s0>;
520 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
521 nand@0,0 {
522 compatible = "ti,omap2-nand";
523 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
524 interrupt-parent = <&gpmc>;
525 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
526 <1 IRQ_TYPE_NONE>; /* termcount */
527 ti,nand-ecc-opt = "bch8";
528 ti,elm-id = <&elm>;
529 nand-bus-width = <8>;
530 gpmc,device-width = <1>;
531 gpmc,sync-clk-ps = <0>;
532 gpmc,cs-on-ns = <0>;
533 gpmc,cs-rd-off-ns = <44>;
534 gpmc,cs-wr-off-ns = <44>;
535 gpmc,adv-on-ns = <6>;
536 gpmc,adv-rd-off-ns = <34>;
537 gpmc,adv-wr-off-ns = <44>;
538 gpmc,we-on-ns = <0>;
539 gpmc,we-off-ns = <40>;
540 gpmc,oe-on-ns = <0>;
541 gpmc,oe-off-ns = <54>;
542 gpmc,access-ns = <64>;
543 gpmc,rd-cycle-ns = <82>;
544 gpmc,wr-cycle-ns = <82>;
545 gpmc,bus-turnaround-ns = <0>;
546 gpmc,cycle2cycle-delay-ns = <0>;
547 gpmc,clk-activation-ns = <0>;
548 gpmc,wr-access-ns = <40>;
549 gpmc,wr-data-mux-bus-ns = <0>;
550 /* MTD partition table */
551 /* All SPL-* partitions are sized to minimal length
552 * which can be independently programmable. For
553 * NAND flash this is equal to size of erase-block */
554 #address-cells = <1>;
555 #size-cells = <1>;
556 partition@0 {
557 label = "NAND.SPL";
558 reg = <0x00000000 0x000020000>;
559 };
560 partition@1 {
561 label = "NAND.SPL.backup1";
562 reg = <0x00020000 0x00020000>;
563 };
564 partition@2 {
565 label = "NAND.SPL.backup2";
566 reg = <0x00040000 0x00020000>;
567 };
568 partition@3 {
569 label = "NAND.SPL.backup3";
570 reg = <0x00060000 0x00020000>;
571 };
572 partition@4 {
573 label = "NAND.u-boot-spl-os";
574 reg = <0x00080000 0x00040000>;
575 };
576 partition@5 {
577 label = "NAND.u-boot";
578 reg = <0x000C0000 0x00100000>;
579 };
580 partition@6 {
581 label = "NAND.u-boot-env";
582 reg = <0x001C0000 0x00020000>;
583 };
584 partition@7 {
585 label = "NAND.u-boot-env.backup1";
586 reg = <0x001E0000 0x00020000>;
587 };
588 partition@8 {
589 label = "NAND.kernel";
590 reg = <0x00200000 0x00800000>;
591 };
592 partition@9 {
593 label = "NAND.file-system";
594 reg = <0x00A00000 0x0F600000>;
595 };
596 };
597};
598
599#include "tps65910.dtsi"
600
601&mcasp1 {
602 #sound-dai-cells = <0>;
603 pinctrl-names = "default", "sleep";
604 pinctrl-0 = <&mcasp1_pins>;
605 pinctrl-1 = <&mcasp1_pins_sleep>;
606
607 status = "okay";
608
609 op-mode = <0>; /* MCASP_IIS_MODE */
610 tdm-slots = <2>;
611 /* 4 serializers */
612 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
613 0 0 1 2
614 >;
615 tx-num-evt = <32>;
616 rx-num-evt = <32>;
617};
618
619&tps {
620 vcc1-supply = <&vbat>;
621 vcc2-supply = <&vbat>;
622 vcc3-supply = <&vbat>;
623 vcc4-supply = <&vbat>;
624 vcc5-supply = <&vbat>;
625 vcc6-supply = <&vbat>;
626 vcc7-supply = <&vbat>;
627 vccio-supply = <&vbat>;
628
629 regulators {
630 vrtc_reg: regulator@0 {
631 regulator-always-on;
632 };
633
634 vio_reg: regulator@1 {
635 regulator-always-on;
636 };
637
638 vdd1_reg: regulator@2 {
639 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
640 regulator-name = "vdd_mpu";
641 regulator-min-microvolt = <912500>;
642 regulator-max-microvolt = <1312500>;
643 regulator-boot-on;
644 regulator-always-on;
645 };
646
647 vdd2_reg: regulator@3 {
648 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
649 regulator-name = "vdd_core";
650 regulator-min-microvolt = <912500>;
651 regulator-max-microvolt = <1150000>;
652 regulator-boot-on;
653 regulator-always-on;
654 };
655
656 vdd3_reg: regulator@4 {
657 regulator-always-on;
658 };
659
660 vdig1_reg: regulator@5 {
661 regulator-always-on;
662 };
663
664 vdig2_reg: regulator@6 {
665 regulator-always-on;
666 };
667
668 vpll_reg: regulator@7 {
669 regulator-always-on;
670 };
671
672 vdac_reg: regulator@8 {
673 regulator-always-on;
674 };
675
676 vaux1_reg: regulator@9 {
677 regulator-always-on;
678 };
679
680 vaux2_reg: regulator@10 {
681 regulator-always-on;
682 };
683
684 vaux33_reg: regulator@11 {
685 regulator-always-on;
686 };
687
688 vmmc_reg: regulator@12 {
689 regulator-min-microvolt = <1800000>;
690 regulator-max-microvolt = <3300000>;
691 regulator-always-on;
692 };
693 };
694};
695
696&mac {
697 pinctrl-names = "default", "sleep";
698 pinctrl-0 = <&cpsw_default>;
699 pinctrl-1 = <&cpsw_sleep>;
700 status = "okay";
701};
702
703&davinci_mdio {
704 pinctrl-names = "default", "sleep";
705 pinctrl-0 = <&davinci_mdio_default>;
706 pinctrl-1 = <&davinci_mdio_sleep>;
707 status = "okay";
708};
709
710&cpsw_emac0 {
711 phy_id = <&davinci_mdio>, <0>;
712 phy-mode = "rgmii-txid";
713};
714
715&cpsw_emac1 {
716 phy_id = <&davinci_mdio>, <1>;
717 phy-mode = "rgmii-txid";
718};
719
720&tscadc {
721 status = "okay";
722 tsc {
723 ti,wires = <4>;
724 ti,x-plate-resistance = <200>;
725 ti,coordinate-readouts = <5>;
726 ti,wire-config = <0x00 0x11 0x22 0x33>;
727 ti,charge-delay = <0x400>;
728 };
729
730 adc {
731 ti,adc-channels = <4 5 6 7>;
732 };
733};
734
735&mmc1 {
736 status = "okay";
737 vmmc-supply = <&vmmc_reg>;
738 bus-width = <4>;
739 pinctrl-names = "default";
740 pinctrl-0 = <&mmc1_pins>;
741 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
742};
743
744&mmc3 {
745 /* these are on the crossbar and are outlined in the
746 xbar-event-map element */
747 dmas = <&edma_xbar 12 0 1
748 &edma_xbar 13 0 2>;
749 dma-names = "tx", "rx";
750 status = "okay";
751 vmmc-supply = <&wlan_en_reg>;
752 bus-width = <4>;
753 pinctrl-names = "default";
754 pinctrl-0 = <&mmc3_pins &wlan_pins>;
755 ti,non-removable;
756 ti,needs-special-hs-handling;
757 cap-power-off-card;
758 keep-power-in-suspend;
759
760 #address-cells = <1>;
761 #size-cells = <0>;
762 wlcore: wlcore@0 {
763 compatible = "ti,wl1835";
764 reg = <2>;
765 interrupt-parent = <&gpio3>;
766 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
767 };
768};
769
770&sham {
771 status = "okay";
772};
773
774&aes {
775 status = "okay";
776};
777
778&dcan1 {
779 status = "disabled"; /* Enable only if Profile 1 is selected */
780 pinctrl-names = "default";
781 pinctrl-0 = <&dcan1_pins_default>;
782};