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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
4 * Author: Rostislav Lisovy <lisovy@jablotron.cz>
5 */
6#include "am33xx.dtsi"
7#include <dt-bindings/interrupt-controller/irq.h>
8
9/ {
10 model = "Grinn AM335x ChiliSOM";
11 compatible = "grinn,am335x-chilisom", "ti,am33xx";
12
13 cpus {
14 cpu@0 {
15 cpu0-supply = <&dcdc2_reg>;
16 };
17 };
18
19 memory@80000000 {
20 device_type = "memory";
21 reg = <0x80000000 0x20000000>; /* 512 MB */
22 };
23};
24
25&am33xx_pinmux {
26 pinctrl-names = "default";
27
28 i2c0_pins: pinmux_i2c0_pins {
29 pinctrl-single,pins = <
30 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
31 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
32 >;
33 };
34
35 nandflash_pins: nandflash_pins {
36 pinctrl-single,pins = <
37 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
38 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
39 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
40 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
41 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0)
42 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0)
43 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0)
44 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0)
45
46 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
47 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0)
48 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0)
49 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0)
50 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0)
51 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0)
52 >;
53 };
54};
55
56&i2c0 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&i2c0_pins>;
59
60 status = "okay";
61 clock-frequency = <400000>;
62
63 tps: tps@24 {
64 reg = <0x24>;
65 };
66
67};
68
69/include/ "tps65217.dtsi"
70
71&tps {
72 regulators {
73 dcdc1_reg: regulator@0 {
74 regulator-name = "vdds_dpr";
75 regulator-always-on;
76 };
77
78 dcdc2_reg: regulator@1 {
79 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
80 regulator-name = "vdd_mpu";
81 regulator-min-microvolt = <925000>;
82 regulator-max-microvolt = <1325000>;
83 regulator-boot-on;
84 regulator-always-on;
85 };
86
87 dcdc3_reg: regulator@2 {
88 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
89 regulator-name = "vdd_core";
90 regulator-min-microvolt = <925000>;
91 regulator-max-microvolt = <1150000>;
92 regulator-boot-on;
93 regulator-always-on;
94 };
95
96 ldo1_reg: regulator@3 {
97 regulator-name = "vio,vrtc,vdds";
98 regulator-boot-on;
99 regulator-always-on;
100 };
101
102 ldo2_reg: regulator@4 {
103 regulator-name = "vdd_3v3aux";
104 regulator-boot-on;
105 regulator-always-on;
106 };
107
108 ldo3_reg: regulator@5 {
109 regulator-name = "vdd_1v8";
110 regulator-boot-on;
111 regulator-always-on;
112 };
113
114 ldo4_reg: regulator@6 {
115 regulator-name = "vdd_3v3d";
116 regulator-boot-on;
117 regulator-always-on;
118 };
119 };
120};
121
122&rtc {
123 system-power-controller;
124
125 pinctrl-0 = <&ext_wakeup>;
126 pinctrl-names = "default";
127
128 ext_wakeup: ext-wakeup {
129 pins = "ext_wakeup0";
130 input-enable;
131 };
132};
133
134/* NAND Flash */
135&elm {
136 status = "okay";
137};
138
139&gpmc {
140 status = "okay";
141 pinctrl-names = "default";
142 pinctrl-0 = <&nandflash_pins>;
143 ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
144 nand@0,0 {
145 compatible = "ti,omap2-nand";
146 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
147 interrupt-parent = <&gpmc>;
148 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
149 <1 IRQ_TYPE_NONE>; /* termcount */
150 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
151 ti,nand-ecc-opt = "bch8";
152 ti,elm-id = <&elm>;
153 nand-bus-width = <8>;
154 gpmc,device-width = <1>;
155 gpmc,sync-clk-ps = <0>;
156 gpmc,cs-on-ns = <0>;
157 gpmc,cs-rd-off-ns = <44>;
158 gpmc,cs-wr-off-ns = <44>;
159 gpmc,adv-on-ns = <6>;
160 gpmc,adv-rd-off-ns = <34>;
161 gpmc,adv-wr-off-ns = <44>;
162 gpmc,we-on-ns = <0>;
163 gpmc,we-off-ns = <40>;
164 gpmc,oe-on-ns = <0>;
165 gpmc,oe-off-ns = <54>;
166 gpmc,access-ns = <64>;
167 gpmc,rd-cycle-ns = <82>;
168 gpmc,wr-cycle-ns = <82>;
169 gpmc,bus-turnaround-ns = <0>;
170 gpmc,cycle2cycle-delay-ns = <0>;
171 gpmc,clk-activation-ns = <0>;
172 gpmc,wr-access-ns = <40>;
173 gpmc,wr-data-mux-bus-ns = <0>;
174 };
175};
1/*
2 * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
3 * Author: Rostislav Lisovy <lisovy@jablotron.cz>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include "am33xx.dtsi"
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13 model = "Grinn AM335x ChiliSOM";
14 compatible = "grinn,am335x-chilisom", "ti,am33xx";
15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&dcdc2_reg>;
19 };
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x20000000>; /* 512 MB */
25 };
26};
27
28&am33xx_pinmux {
29 pinctrl-names = "default";
30
31 i2c0_pins: pinmux_i2c0_pins {
32 pinctrl-single,pins = <
33 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
34 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
35 >;
36 };
37
38 uart0_pins: pinmux_uart0_pins {
39 pinctrl-single,pins = <
40 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
41 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
42 >;
43 };
44
45 cpsw_default: cpsw_default {
46 pinctrl-single,pins = <
47 /* Slave 1 */
48 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
49 AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
50 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
51 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
52 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
53 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
54 AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
55 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */
56 >;
57 };
58
59 cpsw_sleep: cpsw_sleep {
60 pinctrl-single,pins = <
61 /* Slave 1 reset value */
62 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
63 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
64 AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
65 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
66 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
67 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
68 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
69 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
70 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
71 >;
72 };
73
74 davinci_mdio_default: davinci_mdio_default {
75 pinctrl-single,pins = <
76 /* mdio_data.mdio_data */
77 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
78 /* mdio_clk.mdio_clk */
79 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
80 >;
81 };
82
83 davinci_mdio_sleep: davinci_mdio_sleep {
84 pinctrl-single,pins = <
85 /* MDIO reset value */
86 AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
87 AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
88 >;
89 };
90
91 nandflash_pins: nandflash_pins {
92 pinctrl-single,pins = <
93 AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
94 AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
95 AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
96 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
97 AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
98 AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
99 AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
100 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
101
102 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
103 AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
104 AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
105 AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
106 AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */
107 AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
108 >;
109 };
110};
111
112&uart0 {
113 pinctrl-names = "default";
114 pinctrl-0 = <&uart0_pins>;
115
116 status = "okay";
117};
118
119&i2c0 {
120 pinctrl-names = "default";
121 pinctrl-0 = <&i2c0_pins>;
122
123 status = "okay";
124 clock-frequency = <400000>;
125
126 tps: tps@24 {
127 reg = <0x24>;
128 };
129
130};
131
132/include/ "tps65217.dtsi"
133
134&tps {
135 regulators {
136 dcdc1_reg: regulator@0 {
137 regulator-name = "vdds_dpr";
138 regulator-always-on;
139 };
140
141 dcdc2_reg: regulator@1 {
142 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
143 regulator-name = "vdd_mpu";
144 regulator-min-microvolt = <925000>;
145 regulator-max-microvolt = <1325000>;
146 regulator-boot-on;
147 regulator-always-on;
148 };
149
150 dcdc3_reg: regulator@2 {
151 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
152 regulator-name = "vdd_core";
153 regulator-min-microvolt = <925000>;
154 regulator-max-microvolt = <1150000>;
155 regulator-boot-on;
156 regulator-always-on;
157 };
158
159 ldo1_reg: regulator@3 {
160 regulator-name = "vio,vrtc,vdds";
161 regulator-boot-on;
162 regulator-always-on;
163 };
164
165 ldo2_reg: regulator@4 {
166 regulator-name = "vdd_3v3aux";
167 regulator-boot-on;
168 regulator-always-on;
169 };
170
171 ldo3_reg: regulator@5 {
172 regulator-name = "vdd_1v8";
173 regulator-boot-on;
174 regulator-always-on;
175 };
176
177 ldo4_reg: regulator@6 {
178 regulator-name = "vdd_3v3d";
179 regulator-boot-on;
180 regulator-always-on;
181 };
182 };
183};
184
185/* Ethernet MAC */
186&mac {
187 slaves = <1>;
188 pinctrl-names = "default", "sleep";
189 pinctrl-0 = <&cpsw_default>;
190 pinctrl-1 = <&cpsw_sleep>;
191 status = "okay";
192};
193
194&davinci_mdio {
195 pinctrl-names = "default", "sleep";
196 pinctrl-0 = <&davinci_mdio_default>;
197 pinctrl-1 = <&davinci_mdio_sleep>;
198 status = "okay";
199};
200
201/* NAND Flash */
202&elm {
203 status = "okay";
204};
205
206&gpmc {
207 status = "okay";
208 pinctrl-names = "default";
209 pinctrl-0 = <&nandflash_pins>;
210 ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
211 nand@0,0 {
212 compatible = "ti,omap2-nand";
213 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
214 interrupt-parent = <&gpmc>;
215 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
216 <1 IRQ_TYPE_NONE>; /* termcount */
217 ti,nand-ecc-opt = "bch8";
218 ti,elm-id = <&elm>;
219 nand-bus-width = <8>;
220 gpmc,device-width = <1>;
221 gpmc,sync-clk-ps = <0>;
222 gpmc,cs-on-ns = <0>;
223 gpmc,cs-rd-off-ns = <44>;
224 gpmc,cs-wr-off-ns = <44>;
225 gpmc,adv-on-ns = <6>;
226 gpmc,adv-rd-off-ns = <34>;
227 gpmc,adv-wr-off-ns = <44>;
228 gpmc,we-on-ns = <0>;
229 gpmc,we-off-ns = <40>;
230 gpmc,oe-on-ns = <0>;
231 gpmc,oe-off-ns = <54>;
232 gpmc,access-ns = <64>;
233 gpmc,rd-cycle-ns = <82>;
234 gpmc,wr-cycle-ns = <82>;
235 gpmc,bus-turnaround-ns = <0>;
236 gpmc,cycle2cycle-delay-ns = <0>;
237 gpmc,clk-activation-ns = <0>;
238 gpmc,wr-access-ns = <40>;
239 gpmc,wr-data-mux-bus-ns = <0>;
240 };
241};