Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
4 */
5/dts-v1/;
6
7/include/ "skeleton_hs_idu.dtsi"
8
9/ {
10 model = "snps,nsimosci_hs-smp";
11 compatible = "snps,nsimosci_hs";
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&core_intc>;
15
16 chosen {
17 /* this is for console on serial */
18 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
19 };
20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 fpga {
26 compatible = "simple-bus";
27 #address-cells = <1>;
28 #size-cells = <1>;
29
30 /* child and parent address space 1:1 mapped */
31 ranges;
32
33 core_clk: core_clk {
34 #clock-cells = <0>;
35 compatible = "fixed-clock";
36 clock-frequency = <5000000>;
37 };
38
39 core_intc: core-interrupt-controller {
40 compatible = "snps,archs-intc";
41 interrupt-controller;
42 #interrupt-cells = <1>;
43 };
44
45 idu_intc: idu-interrupt-controller {
46 compatible = "snps,archs-idu-intc";
47 interrupt-controller;
48 interrupt-parent = <&core_intc>;
49 #interrupt-cells = <1>;
50 };
51
52 uart0: serial@f0000000 {
53 compatible = "ns8250";
54 reg = <0xf0000000 0x2000>;
55 interrupt-parent = <&idu_intc>;
56 interrupts = <0>;
57 clock-frequency = <3686400>;
58 baud = <115200>;
59 reg-shift = <2>;
60 reg-io-width = <4>;
61 no-loopback-test = <1>;
62 };
63
64 pguclk: pguclk {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <25175000>;
68 };
69
70 pgu@f9000000 {
71 compatible = "snps,arcpgu";
72 reg = <0xf9000000 0x400>;
73 clocks = <&pguclk>;
74 clock-names = "pxlclk";
75 };
76
77 ps2: ps2@f9001000 {
78 compatible = "snps,arc_ps2";
79 reg = <0xf9000400 0x14>;
80 interrupts = <3>;
81 interrupt-parent = <&idu_intc>;
82 interrupt-names = "arc_ps2_irq";
83 };
84
85 eth0: ethernet@f0003000 {
86 compatible = "ezchip,nps-mgt-enet";
87 reg = <0xf0003000 0x44>;
88 interrupt-parent = <&idu_intc>;
89 interrupts = <1>;
90 };
91
92 arcpct0: pct {
93 compatible = "snps,archs-pct";
94 #interrupt-cells = <1>;
95 interrupts = <20>;
96 };
97 };
98};
1/*
2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "skeleton.dtsi"
11
12/ {
13 compatible = "snps,nsimosci_hs";
14 clock-frequency = <5000000>; /* 5 MHZ */
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&core_intc>;
18
19 chosen {
20 /* this is for console on serial */
21 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug";
22 };
23
24 aliases {
25 serial0 = &uart0;
26 };
27
28 fpga {
29 compatible = "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <1>;
32
33 /* child and parent address space 1:1 mapped */
34 ranges;
35
36 core_intc: core-interrupt-controller {
37 compatible = "snps,archs-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40/* interrupts = <16 17 18 19 20 21 22 23 24 25>; */
41 };
42
43 idu_intc: idu-interrupt-controller {
44 compatible = "snps,archs-idu-intc";
45 interrupt-controller;
46 interrupt-parent = <&core_intc>;
47
48 /*
49 * <hwirq distribution>
50 * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
51 */
52 #interrupt-cells = <2>;
53
54 /*
55 * upstream irqs to core intc - downstream these are
56 * "COMMON" irq 0,1..
57 */
58 interrupts = <24 25 26 27 28 29 30 31>;
59 };
60
61 uart0: serial@f0000000 {
62 compatible = "ns8250";
63 reg = <0xf0000000 0x2000>;
64 interrupt-parent = <&idu_intc>;
65 interrupts = <0 0>; /* cmn irq 0 -> cpu irq 24
66 RR distribute to all cpus */
67 clock-frequency = <3686400>;
68 baud = <115200>;
69 reg-shift = <2>;
70 reg-io-width = <4>;
71 no-loopback-test = <1>;
72 };
73
74 pgu0: pgu@f9000000 {
75 compatible = "snps,arcpgufb";
76 reg = <0xf9000000 0x400>;
77 };
78
79 ps2: ps2@f9001000 {
80 compatible = "snps,arc_ps2";
81 reg = <0xf9000400 0x14>;
82 interrupts = <3 0>;
83 interrupt-parent = <&idu_intc>;
84 interrupt-names = "arc_ps2_irq";
85 };
86
87 eth0: ethernet@f0003000 {
88 compatible = "ezchip,nps-mgt-enet";
89 reg = <0xf0003000 0x44>;
90 interrupt-parent = <&idu_intc>;
91 interrupts = <1 2>;
92 };
93
94 arcpct0: pct {
95 compatible = "snps,archs-pct";
96 #interrupt-cells = <1>;
97 interrupts = <20>;
98 };
99 };
100};