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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Octeon Watchdog driver
4 *
5 * Copyright (C) 2007-2017 Cavium, Inc.
6 *
7 * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>.
8 *
9 * Some parts derived from wdt.c
10 *
11 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
12 * All Rights Reserved.
13 *
14 * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
15 * warranty for any of this software. This material is provided
16 * "AS-IS" and at no charge.
17 *
18 * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk>
19 *
20 * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock.
21 * For most systems this is less than 10 seconds, so to allow for
22 * software to request longer watchdog heartbeats, we maintain software
23 * counters to count multiples of the base rate. If the system locks
24 * up in such a manner that we can not run the software counters, the
25 * only result is a watchdog reset sooner than was requested. But
26 * that is OK, because in this case userspace would likely not be able
27 * to do anything anyhow.
28 *
29 * The hardware watchdog interval we call the period. The OCTEON
30 * watchdog goes through several stages, after the first period an
31 * irq is asserted, then if it is not reset, after the next period NMI
32 * is asserted, then after an additional period a chip wide soft reset.
33 * So for the software counters, we reset watchdog after each period
34 * and decrement the counter. But for the last two periods we need to
35 * let the watchdog progress to the NMI stage so we disable the irq
36 * and let it proceed. Once in the NMI, we print the register state
37 * to the serial port and then wait for the reset.
38 *
39 * A watchdog is maintained for each CPU in the system, that way if
40 * one CPU suffers a lockup, we also get a register dump and reset.
41 * The userspace ping resets the watchdog on all CPUs.
42 *
43 * Before userspace opens the watchdog device, we still run the
44 * watchdogs to catch any lockups that may be kernel related.
45 *
46 */
47
48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
50#include <linux/interrupt.h>
51#include <linux/watchdog.h>
52#include <linux/cpumask.h>
53#include <linux/module.h>
54#include <linux/delay.h>
55#include <linux/cpu.h>
56#include <linux/irq.h>
57#include <linux/irqdomain.h>
58
59#include <asm/mipsregs.h>
60#include <asm/uasm.h>
61
62#include <asm/octeon/octeon.h>
63#include <asm/octeon/cvmx-boot-vector.h>
64#include <asm/octeon/cvmx-ciu2-defs.h>
65#include <asm/octeon/cvmx-rst-defs.h>
66
67/* Watchdog interrupt major block number (8 MSBs of intsn) */
68#define WD_BLOCK_NUMBER 0x01
69
70static int divisor;
71
72/* The count needed to achieve timeout_sec. */
73static unsigned int timeout_cnt;
74
75/* The maximum period supported. */
76static unsigned int max_timeout_sec;
77
78/* The current period. */
79static unsigned int timeout_sec;
80
81/* Set to non-zero when userspace countdown mode active */
82static bool do_countdown;
83static unsigned int countdown_reset;
84static unsigned int per_cpu_countdown[NR_CPUS];
85
86static cpumask_t irq_enabled_cpus;
87
88#define WD_TIMO 60 /* Default heartbeat = 60 seconds */
89
90#define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull)
91
92static int heartbeat = WD_TIMO;
93module_param(heartbeat, int, 0444);
94MODULE_PARM_DESC(heartbeat,
95 "Watchdog heartbeat in seconds. (0 < heartbeat, default="
96 __MODULE_STRING(WD_TIMO) ")");
97
98static bool nowayout = WATCHDOG_NOWAYOUT;
99module_param(nowayout, bool, 0444);
100MODULE_PARM_DESC(nowayout,
101 "Watchdog cannot be stopped once started (default="
102 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
103
104static int disable;
105module_param(disable, int, 0444);
106MODULE_PARM_DESC(disable,
107 "Disable the watchdog entirely (default=0)");
108
109static struct cvmx_boot_vector_element *octeon_wdt_bootvector;
110
111void octeon_wdt_nmi_stage2(void);
112
113static int cpu2core(int cpu)
114{
115#ifdef CONFIG_SMP
116 return cpu_logical_map(cpu) & 0x3f;
117#else
118 return cvmx_get_core_num();
119#endif
120}
121
122/**
123 * octeon_wdt_poke_irq - Poke the watchdog when an interrupt is received
124 *
125 * @cpl:
126 * @dev_id:
127 *
128 * Returns
129 */
130static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
131{
132 int cpu = raw_smp_processor_id();
133 unsigned int core = cpu2core(cpu);
134 int node = cpu_to_node(cpu);
135
136 if (do_countdown) {
137 if (per_cpu_countdown[cpu] > 0) {
138 /* We're alive, poke the watchdog */
139 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
140 per_cpu_countdown[cpu]--;
141 } else {
142 /* Bad news, you are about to reboot. */
143 disable_irq_nosync(cpl);
144 cpumask_clear_cpu(cpu, &irq_enabled_cpus);
145 }
146 } else {
147 /* Not open, just ping away... */
148 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
149 }
150 return IRQ_HANDLED;
151}
152
153/* From setup.c */
154extern int prom_putchar(char c);
155
156/**
157 * octeon_wdt_write_string - Write a string to the uart
158 *
159 * @str: String to write
160 */
161static void octeon_wdt_write_string(const char *str)
162{
163 /* Just loop writing one byte at a time */
164 while (*str)
165 prom_putchar(*str++);
166}
167
168/**
169 * octeon_wdt_write_hex() - Write a hex number out of the uart
170 *
171 * @value: Number to display
172 * @digits: Number of digits to print (1 to 16)
173 */
174static void octeon_wdt_write_hex(u64 value, int digits)
175{
176 int d;
177 int v;
178
179 for (d = 0; d < digits; d++) {
180 v = (value >> ((digits - d - 1) * 4)) & 0xf;
181 if (v >= 10)
182 prom_putchar('a' + v - 10);
183 else
184 prom_putchar('0' + v);
185 }
186}
187
188static const char reg_name[][3] = {
189 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
190 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
191 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
192 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
193};
194
195/**
196 * octeon_wdt_nmi_stage3:
197 *
198 * NMI stage 3 handler. NMIs are handled in the following manner:
199 * 1) The first NMI handler enables CVMSEG and transfers from
200 * the bootbus region into normal memory. It is careful to not
201 * destroy any registers.
202 * 2) The second stage handler uses CVMSEG to save the registers
203 * and create a stack for C code. It then calls the third level
204 * handler with one argument, a pointer to the register values.
205 * 3) The third, and final, level handler is the following C
206 * function that prints out some useful infomration.
207 *
208 * @reg: Pointer to register state before the NMI
209 */
210void octeon_wdt_nmi_stage3(u64 reg[32])
211{
212 u64 i;
213
214 unsigned int coreid = cvmx_get_core_num();
215 /*
216 * Save status and cause early to get them before any changes
217 * might happen.
218 */
219 u64 cp0_cause = read_c0_cause();
220 u64 cp0_status = read_c0_status();
221 u64 cp0_error_epc = read_c0_errorepc();
222 u64 cp0_epc = read_c0_epc();
223
224 /* Delay so output from all cores output is not jumbled together. */
225 udelay(85000 * coreid);
226
227 octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
228 octeon_wdt_write_hex(coreid, 2);
229 octeon_wdt_write_string(" ***\r\n");
230 for (i = 0; i < 32; i++) {
231 octeon_wdt_write_string("\t");
232 octeon_wdt_write_string(reg_name[i]);
233 octeon_wdt_write_string("\t0x");
234 octeon_wdt_write_hex(reg[i], 16);
235 if (i & 1)
236 octeon_wdt_write_string("\r\n");
237 }
238 octeon_wdt_write_string("\terr_epc\t0x");
239 octeon_wdt_write_hex(cp0_error_epc, 16);
240
241 octeon_wdt_write_string("\tepc\t0x");
242 octeon_wdt_write_hex(cp0_epc, 16);
243 octeon_wdt_write_string("\r\n");
244
245 octeon_wdt_write_string("\tstatus\t0x");
246 octeon_wdt_write_hex(cp0_status, 16);
247 octeon_wdt_write_string("\tcause\t0x");
248 octeon_wdt_write_hex(cp0_cause, 16);
249 octeon_wdt_write_string("\r\n");
250
251 /* The CIU register is different for each Octeon model. */
252 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
253 octeon_wdt_write_string("\tsrc_wd\t0x");
254 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16);
255 octeon_wdt_write_string("\ten_wd\t0x");
256 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16);
257 octeon_wdt_write_string("\r\n");
258 octeon_wdt_write_string("\tsrc_rml\t0x");
259 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16);
260 octeon_wdt_write_string("\ten_rml\t0x");
261 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16);
262 octeon_wdt_write_string("\r\n");
263 octeon_wdt_write_string("\tsum\t0x");
264 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16);
265 octeon_wdt_write_string("\r\n");
266 } else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) {
267 octeon_wdt_write_string("\tsum0\t0x");
268 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
269 octeon_wdt_write_string("\ten0\t0x");
270 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
271 octeon_wdt_write_string("\r\n");
272 }
273
274 octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");
275
276 /*
277 * G-30204: We must trigger a soft reset before watchdog
278 * does an incomplete job of doing it.
279 */
280 if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) {
281 u64 scr;
282 unsigned int node = cvmx_get_node_num();
283 unsigned int lcore = cvmx_get_local_core_num();
284 union cvmx_ciu_wdogx ciu_wdog;
285
286 /*
287 * Wait for other cores to print out information, but
288 * not too long. Do the soft reset before watchdog
289 * can trigger it.
290 */
291 do {
292 ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore));
293 } while (ciu_wdog.s.cnt > 0x10000);
294
295 scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0));
296 scr |= 1 << 11; /* Indicate watchdog in bit 11 */
297 cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr);
298 cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1);
299 }
300}
301
302static int octeon_wdt_cpu_to_irq(int cpu)
303{
304 unsigned int coreid;
305 int node;
306 int irq;
307
308 coreid = cpu2core(cpu);
309 node = cpu_to_node(cpu);
310
311 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
312 struct irq_domain *domain;
313 int hwirq;
314
315 domain = octeon_irq_get_block_domain(node,
316 WD_BLOCK_NUMBER);
317 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid;
318 irq = irq_find_mapping(domain, hwirq);
319 } else {
320 irq = OCTEON_IRQ_WDOG0 + coreid;
321 }
322 return irq;
323}
324
325static int octeon_wdt_cpu_pre_down(unsigned int cpu)
326{
327 unsigned int core;
328 int node;
329 union cvmx_ciu_wdogx ciu_wdog;
330
331 core = cpu2core(cpu);
332
333 node = cpu_to_node(cpu);
334
335 /* Poke the watchdog to clear out its state */
336 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
337
338 /* Disable the hardware. */
339 ciu_wdog.u64 = 0;
340 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
341
342 free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq);
343 return 0;
344}
345
346static int octeon_wdt_cpu_online(unsigned int cpu)
347{
348 unsigned int core;
349 unsigned int irq;
350 union cvmx_ciu_wdogx ciu_wdog;
351 int node;
352 struct irq_domain *domain;
353 int hwirq;
354
355 core = cpu2core(cpu);
356 node = cpu_to_node(cpu);
357
358 octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2;
359
360 /* Disable it before doing anything with the interrupts. */
361 ciu_wdog.u64 = 0;
362 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
363
364 per_cpu_countdown[cpu] = countdown_reset;
365
366 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
367 /* Must get the domain for the watchdog block */
368 domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER);
369
370 /* Get a irq for the wd intsn (hardware interrupt) */
371 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core;
372 irq = irq_create_mapping(domain, hwirq);
373 irqd_set_trigger_type(irq_get_irq_data(irq),
374 IRQ_TYPE_EDGE_RISING);
375 } else
376 irq = OCTEON_IRQ_WDOG0 + core;
377
378 if (request_irq(irq, octeon_wdt_poke_irq,
379 IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq))
380 panic("octeon_wdt: Couldn't obtain irq %d", irq);
381
382 /* Must set the irq affinity here */
383 if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
384 cpumask_t mask;
385
386 cpumask_clear(&mask);
387 cpumask_set_cpu(cpu, &mask);
388 irq_set_affinity(irq, &mask);
389 }
390
391 cpumask_set_cpu(cpu, &irq_enabled_cpus);
392
393 /* Poke the watchdog to clear out its state */
394 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
395
396 /* Finally enable the watchdog now that all handlers are installed */
397 ciu_wdog.u64 = 0;
398 ciu_wdog.s.len = timeout_cnt;
399 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
400 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
401
402 return 0;
403}
404
405static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog)
406{
407 int cpu;
408 int coreid;
409 int node;
410
411 if (disable)
412 return 0;
413
414 for_each_online_cpu(cpu) {
415 coreid = cpu2core(cpu);
416 node = cpu_to_node(cpu);
417 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
418 per_cpu_countdown[cpu] = countdown_reset;
419 if ((countdown_reset || !do_countdown) &&
420 !cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
421 /* We have to enable the irq */
422 enable_irq(octeon_wdt_cpu_to_irq(cpu));
423 cpumask_set_cpu(cpu, &irq_enabled_cpus);
424 }
425 }
426 return 0;
427}
428
429static void octeon_wdt_calc_parameters(int t)
430{
431 unsigned int periods;
432
433 timeout_sec = max_timeout_sec;
434
435
436 /*
437 * Find the largest interrupt period, that can evenly divide
438 * the requested heartbeat time.
439 */
440 while ((t % timeout_sec) != 0)
441 timeout_sec--;
442
443 periods = t / timeout_sec;
444
445 /*
446 * The last two periods are after the irq is disabled, and
447 * then to the nmi, so we subtract them off.
448 */
449
450 countdown_reset = periods > 2 ? periods - 2 : 0;
451 heartbeat = t;
452 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8;
453}
454
455static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
456 unsigned int t)
457{
458 int cpu;
459 int coreid;
460 union cvmx_ciu_wdogx ciu_wdog;
461 int node;
462
463 if (t <= 0)
464 return -1;
465
466 octeon_wdt_calc_parameters(t);
467
468 if (disable)
469 return 0;
470
471 for_each_online_cpu(cpu) {
472 coreid = cpu2core(cpu);
473 node = cpu_to_node(cpu);
474 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
475 ciu_wdog.u64 = 0;
476 ciu_wdog.s.len = timeout_cnt;
477 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
478 cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
479 cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
480 }
481 octeon_wdt_ping(wdog); /* Get the irqs back on. */
482 return 0;
483}
484
485static int octeon_wdt_start(struct watchdog_device *wdog)
486{
487 octeon_wdt_ping(wdog);
488 do_countdown = 1;
489 return 0;
490}
491
492static int octeon_wdt_stop(struct watchdog_device *wdog)
493{
494 do_countdown = 0;
495 octeon_wdt_ping(wdog);
496 return 0;
497}
498
499static const struct watchdog_info octeon_wdt_info = {
500 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
501 .identity = "OCTEON",
502};
503
504static const struct watchdog_ops octeon_wdt_ops = {
505 .owner = THIS_MODULE,
506 .start = octeon_wdt_start,
507 .stop = octeon_wdt_stop,
508 .ping = octeon_wdt_ping,
509 .set_timeout = octeon_wdt_set_timeout,
510};
511
512static struct watchdog_device octeon_wdt = {
513 .info = &octeon_wdt_info,
514 .ops = &octeon_wdt_ops,
515};
516
517static enum cpuhp_state octeon_wdt_online;
518/**
519 * octeon_wdt_init - Module/ driver initialization.
520 *
521 * Returns Zero on success
522 */
523static int __init octeon_wdt_init(void)
524{
525 int ret;
526
527 octeon_wdt_bootvector = cvmx_boot_vector_get();
528 if (!octeon_wdt_bootvector) {
529 pr_err("Error: Cannot allocate boot vector.\n");
530 return -ENOMEM;
531 }
532
533 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
534 divisor = 0x200;
535 else if (OCTEON_IS_MODEL(OCTEON_CN78XX))
536 divisor = 0x400;
537 else
538 divisor = 0x100;
539
540 /*
541 * Watchdog time expiration length = The 16 bits of LEN
542 * represent the most significant bits of a 24 bit decrementer
543 * that decrements every divisor cycle.
544 *
545 * Try for a timeout of 5 sec, if that fails a smaller number
546 * of even seconds,
547 */
548 max_timeout_sec = 6;
549 do {
550 max_timeout_sec--;
551 timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8;
552 } while (timeout_cnt > 65535);
553
554 BUG_ON(timeout_cnt == 0);
555
556 octeon_wdt_calc_parameters(heartbeat);
557
558 pr_info("Initial granularity %d Sec\n", timeout_sec);
559
560 octeon_wdt.timeout = timeout_sec;
561 octeon_wdt.max_timeout = UINT_MAX;
562
563 watchdog_set_nowayout(&octeon_wdt, nowayout);
564
565 ret = watchdog_register_device(&octeon_wdt);
566 if (ret) {
567 pr_err("watchdog_register_device() failed: %d\n", ret);
568 return ret;
569 }
570
571 if (disable) {
572 pr_notice("disabled\n");
573 return 0;
574 }
575
576 cpumask_clear(&irq_enabled_cpus);
577
578 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "watchdog/octeon:online",
579 octeon_wdt_cpu_online, octeon_wdt_cpu_pre_down);
580 if (ret < 0)
581 goto err;
582 octeon_wdt_online = ret;
583 return 0;
584err:
585 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
586 watchdog_unregister_device(&octeon_wdt);
587 return ret;
588}
589
590/**
591 * octeon_wdt_cleanup - Module / driver shutdown
592 */
593static void __exit octeon_wdt_cleanup(void)
594{
595 watchdog_unregister_device(&octeon_wdt);
596
597 if (disable)
598 return;
599
600 cpuhp_remove_state(octeon_wdt_online);
601
602 /*
603 * Disable the boot-bus memory, the code it points to is soon
604 * to go missing.
605 */
606 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
607}
608
609MODULE_LICENSE("GPL");
610MODULE_AUTHOR("Cavium Inc. <support@cavium.com>");
611MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver.");
612module_init(octeon_wdt_init);
613module_exit(octeon_wdt_cleanup);
1/*
2 * Octeon Watchdog driver
3 *
4 * Copyright (C) 2007, 2008, 2009, 2010 Cavium Networks
5 *
6 * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>.
7 *
8 * Some parts derived from wdt.c
9 *
10 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
11 * All Rights Reserved.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 *
18 * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide
19 * warranty for any of this software. This material is provided
20 * "AS-IS" and at no charge.
21 *
22 * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk>
23 *
24 * This file is subject to the terms and conditions of the GNU General Public
25 * License. See the file "COPYING" in the main directory of this archive
26 * for more details.
27 *
28 *
29 * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock.
30 * For most systems this is less than 10 seconds, so to allow for
31 * software to request longer watchdog heartbeats, we maintain software
32 * counters to count multiples of the base rate. If the system locks
33 * up in such a manner that we can not run the software counters, the
34 * only result is a watchdog reset sooner than was requested. But
35 * that is OK, because in this case userspace would likely not be able
36 * to do anything anyhow.
37 *
38 * The hardware watchdog interval we call the period. The OCTEON
39 * watchdog goes through several stages, after the first period an
40 * irq is asserted, then if it is not reset, after the next period NMI
41 * is asserted, then after an additional period a chip wide soft reset.
42 * So for the software counters, we reset watchdog after each period
43 * and decrement the counter. But for the last two periods we need to
44 * let the watchdog progress to the NMI stage so we disable the irq
45 * and let it proceed. Once in the NMI, we print the register state
46 * to the serial port and then wait for the reset.
47 *
48 * A watchdog is maintained for each CPU in the system, that way if
49 * one CPU suffers a lockup, we also get a register dump and reset.
50 * The userspace ping resets the watchdog on all CPUs.
51 *
52 * Before userspace opens the watchdog device, we still run the
53 * watchdogs to catch any lockups that may be kernel related.
54 *
55 */
56
57#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58
59#include <linux/miscdevice.h>
60#include <linux/interrupt.h>
61#include <linux/watchdog.h>
62#include <linux/cpumask.h>
63#include <linux/bitops.h>
64#include <linux/kernel.h>
65#include <linux/module.h>
66#include <linux/string.h>
67#include <linux/delay.h>
68#include <linux/cpu.h>
69#include <linux/smp.h>
70#include <linux/fs.h>
71#include <linux/irq.h>
72
73#include <asm/mipsregs.h>
74#include <asm/uasm.h>
75
76#include <asm/octeon/octeon.h>
77
78/* The count needed to achieve timeout_sec. */
79static unsigned int timeout_cnt;
80
81/* The maximum period supported. */
82static unsigned int max_timeout_sec;
83
84/* The current period. */
85static unsigned int timeout_sec;
86
87/* Set to non-zero when userspace countdown mode active */
88static int do_coundown;
89static unsigned int countdown_reset;
90static unsigned int per_cpu_countdown[NR_CPUS];
91
92static cpumask_t irq_enabled_cpus;
93
94#define WD_TIMO 60 /* Default heartbeat = 60 seconds */
95
96static int heartbeat = WD_TIMO;
97module_param(heartbeat, int, S_IRUGO);
98MODULE_PARM_DESC(heartbeat,
99 "Watchdog heartbeat in seconds. (0 < heartbeat, default="
100 __MODULE_STRING(WD_TIMO) ")");
101
102static bool nowayout = WATCHDOG_NOWAYOUT;
103module_param(nowayout, bool, S_IRUGO);
104MODULE_PARM_DESC(nowayout,
105 "Watchdog cannot be stopped once started (default="
106 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
107
108static u32 nmi_stage1_insns[64] __initdata;
109/* We need one branch and therefore one relocation per target label. */
110static struct uasm_label labels[5] __initdata;
111static struct uasm_reloc relocs[5] __initdata;
112
113enum lable_id {
114 label_enter_bootloader = 1
115};
116
117/* Some CP0 registers */
118#define K0 26
119#define C0_CVMMEMCTL 11, 7
120#define C0_STATUS 12, 0
121#define C0_EBASE 15, 1
122#define C0_DESAVE 31, 0
123
124void octeon_wdt_nmi_stage2(void);
125
126static void __init octeon_wdt_build_stage1(void)
127{
128 int i;
129 int len;
130 u32 *p = nmi_stage1_insns;
131#ifdef CONFIG_HOTPLUG_CPU
132 struct uasm_label *l = labels;
133 struct uasm_reloc *r = relocs;
134#endif
135
136 /*
137 * For the next few instructions running the debugger may
138 * cause corruption of k0 in the saved registers. Since we're
139 * about to crash, nobody probably cares.
140 *
141 * Save K0 into the debug scratch register
142 */
143 uasm_i_dmtc0(&p, K0, C0_DESAVE);
144
145 uasm_i_mfc0(&p, K0, C0_STATUS);
146#ifdef CONFIG_HOTPLUG_CPU
147 if (octeon_bootloader_entry_addr)
148 uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI),
149 label_enter_bootloader);
150#endif
151 /* Force 64-bit addressing enabled */
152 uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX);
153 uasm_i_mtc0(&p, K0, C0_STATUS);
154
155#ifdef CONFIG_HOTPLUG_CPU
156 if (octeon_bootloader_entry_addr) {
157 uasm_i_mfc0(&p, K0, C0_EBASE);
158 /* Coreid number in K0 */
159 uasm_i_andi(&p, K0, K0, 0xf);
160 /* 8 * coreid in bits 16-31 */
161 uasm_i_dsll_safe(&p, K0, K0, 3 + 16);
162 uasm_i_ori(&p, K0, K0, 0x8001);
163 uasm_i_dsll_safe(&p, K0, K0, 16);
164 uasm_i_ori(&p, K0, K0, 0x0700);
165 uasm_i_drotr_safe(&p, K0, K0, 32);
166 /*
167 * Should result in: 0x8001,0700,0000,8*coreid which is
168 * CVMX_CIU_WDOGX(coreid) - 0x0500
169 *
170 * Now ld K0, CVMX_CIU_WDOGX(coreid)
171 */
172 uasm_i_ld(&p, K0, 0x500, K0);
173 /*
174 * If bit one set handle the NMI as a watchdog event.
175 * otherwise transfer control to bootloader.
176 */
177 uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader);
178 uasm_i_nop(&p);
179 }
180#endif
181
182 /* Clear Dcache so cvmseg works right. */
183 uasm_i_cache(&p, 1, 0, 0);
184
185 /* Use K0 to do a read/modify/write of CVMMEMCTL */
186 uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL);
187 /* Clear out the size of CVMSEG */
188 uasm_i_dins(&p, K0, 0, 0, 6);
189 /* Set CVMSEG to its largest value */
190 uasm_i_ori(&p, K0, K0, 0x1c0 | 54);
191 /* Store the CVMMEMCTL value */
192 uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL);
193
194 /* Load the address of the second stage handler */
195 UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2);
196 uasm_i_jr(&p, K0);
197 uasm_i_dmfc0(&p, K0, C0_DESAVE);
198
199#ifdef CONFIG_HOTPLUG_CPU
200 if (octeon_bootloader_entry_addr) {
201 uasm_build_label(&l, p, label_enter_bootloader);
202 /* Jump to the bootloader and restore K0 */
203 UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr);
204 uasm_i_jr(&p, K0);
205 uasm_i_dmfc0(&p, K0, C0_DESAVE);
206 }
207#endif
208 uasm_resolve_relocs(relocs, labels);
209
210 len = (int)(p - nmi_stage1_insns);
211 pr_debug("Synthesized NMI stage 1 handler (%d instructions)\n", len);
212
213 pr_debug("\t.set push\n");
214 pr_debug("\t.set noreorder\n");
215 for (i = 0; i < len; i++)
216 pr_debug("\t.word 0x%08x\n", nmi_stage1_insns[i]);
217 pr_debug("\t.set pop\n");
218
219 if (len > 32)
220 panic("NMI stage 1 handler exceeds 32 instructions, was %d\n",
221 len);
222}
223
224static int cpu2core(int cpu)
225{
226#ifdef CONFIG_SMP
227 return cpu_logical_map(cpu);
228#else
229 return cvmx_get_core_num();
230#endif
231}
232
233static int core2cpu(int coreid)
234{
235#ifdef CONFIG_SMP
236 return cpu_number_map(coreid);
237#else
238 return 0;
239#endif
240}
241
242/**
243 * Poke the watchdog when an interrupt is received
244 *
245 * @cpl:
246 * @dev_id:
247 *
248 * Returns
249 */
250static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
251{
252 unsigned int core = cvmx_get_core_num();
253 int cpu = core2cpu(core);
254
255 if (do_coundown) {
256 if (per_cpu_countdown[cpu] > 0) {
257 /* We're alive, poke the watchdog */
258 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
259 per_cpu_countdown[cpu]--;
260 } else {
261 /* Bad news, you are about to reboot. */
262 disable_irq_nosync(cpl);
263 cpumask_clear_cpu(cpu, &irq_enabled_cpus);
264 }
265 } else {
266 /* Not open, just ping away... */
267 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
268 }
269 return IRQ_HANDLED;
270}
271
272/* From setup.c */
273extern int prom_putchar(char c);
274
275/**
276 * Write a string to the uart
277 *
278 * @str: String to write
279 */
280static void octeon_wdt_write_string(const char *str)
281{
282 /* Just loop writing one byte at a time */
283 while (*str)
284 prom_putchar(*str++);
285}
286
287/**
288 * Write a hex number out of the uart
289 *
290 * @value: Number to display
291 * @digits: Number of digits to print (1 to 16)
292 */
293static void octeon_wdt_write_hex(u64 value, int digits)
294{
295 int d;
296 int v;
297
298 for (d = 0; d < digits; d++) {
299 v = (value >> ((digits - d - 1) * 4)) & 0xf;
300 if (v >= 10)
301 prom_putchar('a' + v - 10);
302 else
303 prom_putchar('0' + v);
304 }
305}
306
307static const char reg_name[][3] = {
308 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
309 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
310 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
311 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
312};
313
314/**
315 * NMI stage 3 handler. NMIs are handled in the following manner:
316 * 1) The first NMI handler enables CVMSEG and transfers from
317 * the bootbus region into normal memory. It is careful to not
318 * destroy any registers.
319 * 2) The second stage handler uses CVMSEG to save the registers
320 * and create a stack for C code. It then calls the third level
321 * handler with one argument, a pointer to the register values.
322 * 3) The third, and final, level handler is the following C
323 * function that prints out some useful infomration.
324 *
325 * @reg: Pointer to register state before the NMI
326 */
327void octeon_wdt_nmi_stage3(u64 reg[32])
328{
329 u64 i;
330
331 unsigned int coreid = cvmx_get_core_num();
332 /*
333 * Save status and cause early to get them before any changes
334 * might happen.
335 */
336 u64 cp0_cause = read_c0_cause();
337 u64 cp0_status = read_c0_status();
338 u64 cp0_error_epc = read_c0_errorepc();
339 u64 cp0_epc = read_c0_epc();
340
341 /* Delay so output from all cores output is not jumbled together. */
342 __delay(100000000ull * coreid);
343
344 octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
345 octeon_wdt_write_hex(coreid, 1);
346 octeon_wdt_write_string(" ***\r\n");
347 for (i = 0; i < 32; i++) {
348 octeon_wdt_write_string("\t");
349 octeon_wdt_write_string(reg_name[i]);
350 octeon_wdt_write_string("\t0x");
351 octeon_wdt_write_hex(reg[i], 16);
352 if (i & 1)
353 octeon_wdt_write_string("\r\n");
354 }
355 octeon_wdt_write_string("\terr_epc\t0x");
356 octeon_wdt_write_hex(cp0_error_epc, 16);
357
358 octeon_wdt_write_string("\tepc\t0x");
359 octeon_wdt_write_hex(cp0_epc, 16);
360 octeon_wdt_write_string("\r\n");
361
362 octeon_wdt_write_string("\tstatus\t0x");
363 octeon_wdt_write_hex(cp0_status, 16);
364 octeon_wdt_write_string("\tcause\t0x");
365 octeon_wdt_write_hex(cp0_cause, 16);
366 octeon_wdt_write_string("\r\n");
367
368 octeon_wdt_write_string("\tsum0\t0x");
369 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
370 octeon_wdt_write_string("\ten0\t0x");
371 octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
372 octeon_wdt_write_string("\r\n");
373
374 octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");
375}
376
377static void octeon_wdt_disable_interrupt(int cpu)
378{
379 unsigned int core;
380 unsigned int irq;
381 union cvmx_ciu_wdogx ciu_wdog;
382
383 core = cpu2core(cpu);
384
385 irq = OCTEON_IRQ_WDOG0 + core;
386
387 /* Poke the watchdog to clear out its state */
388 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
389
390 /* Disable the hardware. */
391 ciu_wdog.u64 = 0;
392 cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
393
394 free_irq(irq, octeon_wdt_poke_irq);
395}
396
397static void octeon_wdt_setup_interrupt(int cpu)
398{
399 unsigned int core;
400 unsigned int irq;
401 union cvmx_ciu_wdogx ciu_wdog;
402
403 core = cpu2core(cpu);
404
405 /* Disable it before doing anything with the interrupts. */
406 ciu_wdog.u64 = 0;
407 cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
408
409 per_cpu_countdown[cpu] = countdown_reset;
410
411 irq = OCTEON_IRQ_WDOG0 + core;
412
413 if (request_irq(irq, octeon_wdt_poke_irq,
414 IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq))
415 panic("octeon_wdt: Couldn't obtain irq %d", irq);
416
417 cpumask_set_cpu(cpu, &irq_enabled_cpus);
418
419 /* Poke the watchdog to clear out its state */
420 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
421
422 /* Finally enable the watchdog now that all handlers are installed */
423 ciu_wdog.u64 = 0;
424 ciu_wdog.s.len = timeout_cnt;
425 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
426 cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
427}
428
429static int octeon_wdt_cpu_callback(struct notifier_block *nfb,
430 unsigned long action, void *hcpu)
431{
432 unsigned int cpu = (unsigned long)hcpu;
433
434 switch (action) {
435 case CPU_DOWN_PREPARE:
436 octeon_wdt_disable_interrupt(cpu);
437 break;
438 case CPU_ONLINE:
439 case CPU_DOWN_FAILED:
440 octeon_wdt_setup_interrupt(cpu);
441 break;
442 default:
443 break;
444 }
445 return NOTIFY_OK;
446}
447
448static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog)
449{
450 int cpu;
451 int coreid;
452
453 for_each_online_cpu(cpu) {
454 coreid = cpu2core(cpu);
455 cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
456 per_cpu_countdown[cpu] = countdown_reset;
457 if ((countdown_reset || !do_coundown) &&
458 !cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
459 /* We have to enable the irq */
460 int irq = OCTEON_IRQ_WDOG0 + coreid;
461
462 enable_irq(irq);
463 cpumask_set_cpu(cpu, &irq_enabled_cpus);
464 }
465 }
466 return 0;
467}
468
469static void octeon_wdt_calc_parameters(int t)
470{
471 unsigned int periods;
472
473 timeout_sec = max_timeout_sec;
474
475
476 /*
477 * Find the largest interrupt period, that can evenly divide
478 * the requested heartbeat time.
479 */
480 while ((t % timeout_sec) != 0)
481 timeout_sec--;
482
483 periods = t / timeout_sec;
484
485 /*
486 * The last two periods are after the irq is disabled, and
487 * then to the nmi, so we subtract them off.
488 */
489
490 countdown_reset = periods > 2 ? periods - 2 : 0;
491 heartbeat = t;
492 timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8;
493}
494
495static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
496 unsigned int t)
497{
498 int cpu;
499 int coreid;
500 union cvmx_ciu_wdogx ciu_wdog;
501
502 if (t <= 0)
503 return -1;
504
505 octeon_wdt_calc_parameters(t);
506
507 for_each_online_cpu(cpu) {
508 coreid = cpu2core(cpu);
509 cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
510 ciu_wdog.u64 = 0;
511 ciu_wdog.s.len = timeout_cnt;
512 ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */
513 cvmx_write_csr(CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
514 cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
515 }
516 octeon_wdt_ping(wdog); /* Get the irqs back on. */
517 return 0;
518}
519
520static int octeon_wdt_start(struct watchdog_device *wdog)
521{
522 octeon_wdt_ping(wdog);
523 do_coundown = 1;
524 return 0;
525}
526
527static int octeon_wdt_stop(struct watchdog_device *wdog)
528{
529 do_coundown = 0;
530 octeon_wdt_ping(wdog);
531 return 0;
532}
533
534static struct notifier_block octeon_wdt_cpu_notifier = {
535 .notifier_call = octeon_wdt_cpu_callback,
536};
537
538static const struct watchdog_info octeon_wdt_info = {
539 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
540 .identity = "OCTEON",
541};
542
543static const struct watchdog_ops octeon_wdt_ops = {
544 .owner = THIS_MODULE,
545 .start = octeon_wdt_start,
546 .stop = octeon_wdt_stop,
547 .ping = octeon_wdt_ping,
548 .set_timeout = octeon_wdt_set_timeout,
549};
550
551static struct watchdog_device octeon_wdt = {
552 .info = &octeon_wdt_info,
553 .ops = &octeon_wdt_ops,
554};
555
556/**
557 * Module/ driver initialization.
558 *
559 * Returns Zero on success
560 */
561static int __init octeon_wdt_init(void)
562{
563 int i;
564 int ret;
565 int cpu;
566 u64 *ptr;
567
568 /*
569 * Watchdog time expiration length = The 16 bits of LEN
570 * represent the most significant bits of a 24 bit decrementer
571 * that decrements every 256 cycles.
572 *
573 * Try for a timeout of 5 sec, if that fails a smaller number
574 * of even seconds,
575 */
576 max_timeout_sec = 6;
577 do {
578 max_timeout_sec--;
579 timeout_cnt = ((octeon_get_io_clock_rate() >> 8) *
580 max_timeout_sec) >> 8;
581 } while (timeout_cnt > 65535);
582
583 BUG_ON(timeout_cnt == 0);
584
585 octeon_wdt_calc_parameters(heartbeat);
586
587 pr_info("Initial granularity %d Sec\n", timeout_sec);
588
589 octeon_wdt.timeout = timeout_sec;
590 octeon_wdt.max_timeout = UINT_MAX;
591
592 watchdog_set_nowayout(&octeon_wdt, nowayout);
593
594 ret = watchdog_register_device(&octeon_wdt);
595 if (ret) {
596 pr_err("watchdog_register_device() failed: %d\n", ret);
597 return ret;
598 }
599
600 /* Build the NMI handler ... */
601 octeon_wdt_build_stage1();
602
603 /* ... and install it. */
604 ptr = (u64 *) nmi_stage1_insns;
605 for (i = 0; i < 16; i++) {
606 cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
607 cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, ptr[i]);
608 }
609 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
610
611 cpumask_clear(&irq_enabled_cpus);
612
613 cpu_notifier_register_begin();
614 for_each_online_cpu(cpu)
615 octeon_wdt_setup_interrupt(cpu);
616
617 __register_hotcpu_notifier(&octeon_wdt_cpu_notifier);
618 cpu_notifier_register_done();
619
620 return 0;
621}
622
623/**
624 * Module / driver shutdown
625 */
626static void __exit octeon_wdt_cleanup(void)
627{
628 int cpu;
629
630 watchdog_unregister_device(&octeon_wdt);
631
632 cpu_notifier_register_begin();
633 __unregister_hotcpu_notifier(&octeon_wdt_cpu_notifier);
634
635 for_each_online_cpu(cpu) {
636 int core = cpu2core(cpu);
637 /* Disable the watchdog */
638 cvmx_write_csr(CVMX_CIU_WDOGX(core), 0);
639 /* Free the interrupt handler */
640 free_irq(OCTEON_IRQ_WDOG0 + core, octeon_wdt_poke_irq);
641 }
642
643 cpu_notifier_register_done();
644
645 /*
646 * Disable the boot-bus memory, the code it points to is soon
647 * to go missing.
648 */
649 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0);
650}
651
652MODULE_LICENSE("GPL");
653MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
654MODULE_DESCRIPTION("Cavium Networks Octeon Watchdog driver.");
655module_init(octeon_wdt_init);
656module_exit(octeon_wdt_cleanup);