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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
4 * Author: Jon Ringle <jringle@gridpoint.com>
5 *
6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/bitops.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/gpio/driver.h>
16#include <linux/i2c.h>
17#include <linux/mod_devicetable.h>
18#include <linux/module.h>
19#include <linux/property.h>
20#include <linux/regmap.h>
21#include <linux/serial_core.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <linux/spi/spi.h>
26#include <linux/uaccess.h>
27#include <uapi/linux/sched/types.h>
28
29#define SC16IS7XX_NAME "sc16is7xx"
30#define SC16IS7XX_MAX_DEVS 8
31
32/* SC16IS7XX register definitions */
33#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
34#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
35#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
36#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
37#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
38#define SC16IS7XX_LCR_REG (0x03) /* Line Control */
39#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
40#define SC16IS7XX_LSR_REG (0x05) /* Line Status */
41#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
42#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
43#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
44#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
45#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
46 * - only on 75x/76x
47 */
48#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
49 * - only on 75x/76x
50 */
51#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
52 * - only on 75x/76x
53 */
54#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
55 * - only on 75x/76x
56 */
57#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
58
59/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
60#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
61#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
62
63/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
64#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
65#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
66
67/* Enhanced Register set: Only if (LCR == 0xBF) */
68#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
69#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
70#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
71#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
72#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
73
74/* IER register bits */
75#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
76#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
77 * interrupt */
78#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
79 * interrupt */
80#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
81 * interrupt */
82
83/* IER register bits - write only if (EFR[4] == 1) */
84#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
85#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
86#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
87#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
88
89/* FCR register bits */
90#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
91#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
92#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
93#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
94#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
95
96/* FCR register bits - write only if (EFR[4] == 1) */
97#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
98#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
99
100/* IIR register bits */
101#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
102#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
103#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
104#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
105#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
106#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
107#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
108 * - only on 75x/76x
109 */
110#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
111 * - only on 75x/76x
112 */
113#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
114#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
115 * from active (LOW)
116 * to inactive (HIGH)
117 */
118/* LCR register bits */
119#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
120#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
121 *
122 * Word length bits table:
123 * 00 -> 5 bit words
124 * 01 -> 6 bit words
125 * 10 -> 7 bit words
126 * 11 -> 8 bit words
127 */
128#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
129 *
130 * STOP length bit table:
131 * 0 -> 1 stop bit
132 * 1 -> 1-1.5 stop bits if
133 * word length is 5,
134 * 2 stop bits otherwise
135 */
136#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
137#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
138#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
139#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
140#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
141#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
142#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
143#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
144#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
145#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
146 * reg set */
147#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
148 * reg set */
149
150/* MCR register bits */
151#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
152 * - only on 75x/76x
153 */
154#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
155#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
156#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
157#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
158 * - write enabled
159 * if (EFR[4] == 1)
160 */
161#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
162 * - write enabled
163 * if (EFR[4] == 1)
164 */
165#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
166 * - write enabled
167 * if (EFR[4] == 1)
168 */
169
170/* LSR register bits */
171#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
172#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
173#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
174#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
175#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
176#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
177#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
178#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
179#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
180
181/* MSR register bits */
182#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
183#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
184 * or (IO4)
185 * - only on 75x/76x
186 */
187#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
188 * or (IO7)
189 * - only on 75x/76x
190 */
191#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
192 * or (IO6)
193 * - only on 75x/76x
194 */
195#define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
196#define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
197 * - only on 75x/76x
198 */
199#define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
200 * - only on 75x/76x
201 */
202#define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
203 * - only on 75x/76x
204 */
205#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
206
207/*
208 * TCR register bits
209 * TCR trigger levels are available from 0 to 60 characters with a granularity
210 * of four.
211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
212 * no built-in hardware check to make sure this condition is met. Also, the TCR
213 * must be programmed with this condition before auto RTS or software flow
214 * control is enabled to avoid spurious operation of the device.
215 */
216#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
217#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
218
219/*
220 * TLR register bits
221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
223 * trigger levels. Trigger levels from 4 characters to 60 characters are
224 * available with a granularity of four.
225 *
226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
228 * the trigger level defined in FCR is discarded. This applies to both transmit
229 * FIFO and receive FIFO trigger level setting.
230 *
231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
232 * default state, that is, '00'.
233 */
234#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
235#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
236
237/* IOControl register bits (Only 750/760) */
238#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
239#define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
240#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
241
242/* EFCR register bits */
243#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
244 * mode (RS485) */
245#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
246#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
247#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
248#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
249#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
250 * 0 = rate upto 115.2 kbit/s
251 * - Only 750/760
252 * 1 = rate upto 1.152 Mbit/s
253 * - Only 760
254 */
255
256/* EFR register bits */
257#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
258#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
259#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
260#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
261 * and writing to IER[7:4],
262 * FCR[5:4], MCR[7:5]
263 */
264#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
265#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
266 *
267 * SWFLOW bits 3 & 2 table:
268 * 00 -> no transmitter flow
269 * control
270 * 01 -> transmitter generates
271 * XON2 and XOFF2
272 * 10 -> transmitter generates
273 * XON1 and XOFF1
274 * 11 -> transmitter generates
275 * XON1, XON2, XOFF1 and
276 * XOFF2
277 */
278#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
279#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
280 *
281 * SWFLOW bits 3 & 2 table:
282 * 00 -> no received flow
283 * control
284 * 01 -> receiver compares
285 * XON2 and XOFF2
286 * 10 -> receiver compares
287 * XON1 and XOFF1
288 * 11 -> receiver compares
289 * XON1, XON2, XOFF1 and
290 * XOFF2
291 */
292#define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \
293 SC16IS7XX_EFR_AUTOCTS_BIT | \
294 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
295 SC16IS7XX_EFR_SWFLOW3_BIT | \
296 SC16IS7XX_EFR_SWFLOW2_BIT | \
297 SC16IS7XX_EFR_SWFLOW1_BIT | \
298 SC16IS7XX_EFR_SWFLOW0_BIT)
299
300
301/* Misc definitions */
302#define SC16IS7XX_FIFO_SIZE (64)
303#define SC16IS7XX_REG_SHIFT 2
304
305struct sc16is7xx_devtype {
306 char name[10];
307 int nr_gpio;
308 int nr_uart;
309 int has_mctrl;
310};
311
312#define SC16IS7XX_RECONF_MD (1 << 0)
313#define SC16IS7XX_RECONF_IER (1 << 1)
314#define SC16IS7XX_RECONF_RS485 (1 << 2)
315
316struct sc16is7xx_one_config {
317 unsigned int flags;
318 u8 ier_mask;
319 u8 ier_val;
320};
321
322struct sc16is7xx_one {
323 struct uart_port port;
324 u8 line;
325 struct kthread_work tx_work;
326 struct kthread_work reg_work;
327 struct kthread_delayed_work ms_work;
328 struct sc16is7xx_one_config config;
329 bool irda_mode;
330 unsigned int old_mctrl;
331};
332
333struct sc16is7xx_port {
334 const struct sc16is7xx_devtype *devtype;
335 struct regmap *regmap;
336 struct clk *clk;
337#ifdef CONFIG_GPIOLIB
338 struct gpio_chip gpio;
339#endif
340 unsigned char buf[SC16IS7XX_FIFO_SIZE];
341 struct kthread_worker kworker;
342 struct task_struct *kworker_task;
343 struct mutex efr_lock;
344 struct sc16is7xx_one p[];
345};
346
347static unsigned long sc16is7xx_lines;
348
349static struct uart_driver sc16is7xx_uart = {
350 .owner = THIS_MODULE,
351 .dev_name = "ttySC",
352 .nr = SC16IS7XX_MAX_DEVS,
353};
354
355static void sc16is7xx_ier_set(struct uart_port *port, u8 bit);
356static void sc16is7xx_stop_tx(struct uart_port *port);
357
358#define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
359#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
360
361static int sc16is7xx_line(struct uart_port *port)
362{
363 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
364
365 return one->line;
366}
367
368static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
369{
370 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
371 unsigned int val = 0;
372 const u8 line = sc16is7xx_line(port);
373
374 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
375
376 return val;
377}
378
379static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
380{
381 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
382 const u8 line = sc16is7xx_line(port);
383
384 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
385}
386
387static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
388{
389 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
390 const u8 line = sc16is7xx_line(port);
391 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
392
393 regcache_cache_bypass(s->regmap, true);
394 regmap_raw_read(s->regmap, addr, s->buf, rxlen);
395 regcache_cache_bypass(s->regmap, false);
396}
397
398static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
399{
400 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
401 const u8 line = sc16is7xx_line(port);
402 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
403
404 /*
405 * Don't send zero-length data, at least on SPI it confuses the chip
406 * delivering wrong TXLVL data.
407 */
408 if (unlikely(!to_send))
409 return;
410
411 regcache_cache_bypass(s->regmap, true);
412 regmap_raw_write(s->regmap, addr, s->buf, to_send);
413 regcache_cache_bypass(s->regmap, false);
414}
415
416static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
417 u8 mask, u8 val)
418{
419 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
420 const u8 line = sc16is7xx_line(port);
421
422 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
423 mask, val);
424}
425
426static int sc16is7xx_alloc_line(void)
427{
428 int i;
429
430 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
431
432 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
433 if (!test_and_set_bit(i, &sc16is7xx_lines))
434 break;
435
436 return i;
437}
438
439static void sc16is7xx_power(struct uart_port *port, int on)
440{
441 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
442 SC16IS7XX_IER_SLEEP_BIT,
443 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
444}
445
446static const struct sc16is7xx_devtype sc16is74x_devtype = {
447 .name = "SC16IS74X",
448 .nr_gpio = 0,
449 .nr_uart = 1,
450 .has_mctrl = 0,
451};
452
453static const struct sc16is7xx_devtype sc16is750_devtype = {
454 .name = "SC16IS750",
455 .nr_gpio = 4,
456 .nr_uart = 1,
457 .has_mctrl = 1,
458};
459
460static const struct sc16is7xx_devtype sc16is752_devtype = {
461 .name = "SC16IS752",
462 .nr_gpio = 0,
463 .nr_uart = 2,
464 .has_mctrl = 1,
465};
466
467static const struct sc16is7xx_devtype sc16is760_devtype = {
468 .name = "SC16IS760",
469 .nr_gpio = 4,
470 .nr_uart = 1,
471 .has_mctrl = 1,
472};
473
474static const struct sc16is7xx_devtype sc16is762_devtype = {
475 .name = "SC16IS762",
476 .nr_gpio = 0,
477 .nr_uart = 2,
478 .has_mctrl = 1,
479};
480
481static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
482{
483 switch (reg >> SC16IS7XX_REG_SHIFT) {
484 case SC16IS7XX_RHR_REG:
485 case SC16IS7XX_IIR_REG:
486 case SC16IS7XX_LSR_REG:
487 case SC16IS7XX_MSR_REG:
488 case SC16IS7XX_TXLVL_REG:
489 case SC16IS7XX_RXLVL_REG:
490 case SC16IS7XX_IOSTATE_REG:
491 return true;
492 default:
493 break;
494 }
495
496 return false;
497}
498
499static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
500{
501 switch (reg >> SC16IS7XX_REG_SHIFT) {
502 case SC16IS7XX_RHR_REG:
503 return true;
504 default:
505 break;
506 }
507
508 return false;
509}
510
511static int sc16is7xx_set_baud(struct uart_port *port, int baud)
512{
513 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
514 u8 lcr;
515 u8 prescaler = 0;
516 unsigned long clk = port->uartclk, div = clk / 16 / baud;
517
518 if (div > 0xffff) {
519 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
520 div /= 4;
521 }
522
523 /* In an amazing feat of design, the Enhanced Features Register shares
524 * the address of the Interrupt Identification Register, and is
525 * switched in by writing a magic value (0xbf) to the Line Control
526 * Register. Any interrupt firing during this time will see the EFR
527 * where it expects the IIR to be, leading to "Unexpected interrupt"
528 * messages.
529 *
530 * Prevent this possibility by claiming a mutex while accessing the
531 * EFR, and claiming the same mutex from within the interrupt handler.
532 * This is similar to disabling the interrupt, but that doesn't work
533 * because the bulk of the interrupt processing is run as a workqueue
534 * job in thread context.
535 */
536 mutex_lock(&s->efr_lock);
537
538 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
539
540 /* Open the LCR divisors for configuration */
541 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
542 SC16IS7XX_LCR_CONF_MODE_B);
543
544 /* Enable enhanced features */
545 regcache_cache_bypass(s->regmap, true);
546 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
547 SC16IS7XX_EFR_ENABLE_BIT,
548 SC16IS7XX_EFR_ENABLE_BIT);
549
550 regcache_cache_bypass(s->regmap, false);
551
552 /* Put LCR back to the normal mode */
553 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
554
555 mutex_unlock(&s->efr_lock);
556
557 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
558 SC16IS7XX_MCR_CLKSEL_BIT,
559 prescaler);
560
561 /* Open the LCR divisors for configuration */
562 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
563 SC16IS7XX_LCR_CONF_MODE_A);
564
565 /* Write the new divisor */
566 regcache_cache_bypass(s->regmap, true);
567 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
568 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
569 regcache_cache_bypass(s->regmap, false);
570
571 /* Put LCR back to the normal mode */
572 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
573
574 return DIV_ROUND_CLOSEST(clk / 16, div);
575}
576
577static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
578 unsigned int iir)
579{
580 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
581 unsigned int lsr = 0, ch, flag, bytes_read, i;
582 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
583
584 if (unlikely(rxlen >= sizeof(s->buf))) {
585 dev_warn_ratelimited(port->dev,
586 "ttySC%i: Possible RX FIFO overrun: %d\n",
587 port->line, rxlen);
588 port->icount.buf_overrun++;
589 /* Ensure sanity of RX level */
590 rxlen = sizeof(s->buf);
591 }
592
593 while (rxlen) {
594 /* Only read lsr if there are possible errors in FIFO */
595 if (read_lsr) {
596 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
597 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
598 read_lsr = false; /* No errors left in FIFO */
599 } else
600 lsr = 0;
601
602 if (read_lsr) {
603 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
604 bytes_read = 1;
605 } else {
606 sc16is7xx_fifo_read(port, rxlen);
607 bytes_read = rxlen;
608 }
609
610 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
611
612 port->icount.rx++;
613 flag = TTY_NORMAL;
614
615 if (unlikely(lsr)) {
616 if (lsr & SC16IS7XX_LSR_BI_BIT) {
617 port->icount.brk++;
618 if (uart_handle_break(port))
619 continue;
620 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
621 port->icount.parity++;
622 else if (lsr & SC16IS7XX_LSR_FE_BIT)
623 port->icount.frame++;
624 else if (lsr & SC16IS7XX_LSR_OE_BIT)
625 port->icount.overrun++;
626
627 lsr &= port->read_status_mask;
628 if (lsr & SC16IS7XX_LSR_BI_BIT)
629 flag = TTY_BREAK;
630 else if (lsr & SC16IS7XX_LSR_PE_BIT)
631 flag = TTY_PARITY;
632 else if (lsr & SC16IS7XX_LSR_FE_BIT)
633 flag = TTY_FRAME;
634 else if (lsr & SC16IS7XX_LSR_OE_BIT)
635 flag = TTY_OVERRUN;
636 }
637
638 for (i = 0; i < bytes_read; ++i) {
639 ch = s->buf[i];
640 if (uart_handle_sysrq_char(port, ch))
641 continue;
642
643 if (lsr & port->ignore_status_mask)
644 continue;
645
646 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
647 flag);
648 }
649 rxlen -= bytes_read;
650 }
651
652 tty_flip_buffer_push(&port->state->port);
653}
654
655static void sc16is7xx_handle_tx(struct uart_port *port)
656{
657 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
658 struct circ_buf *xmit = &port->state->xmit;
659 unsigned int txlen, to_send, i;
660 unsigned long flags;
661
662 if (unlikely(port->x_char)) {
663 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
664 port->icount.tx++;
665 port->x_char = 0;
666 return;
667 }
668
669 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
670 spin_lock_irqsave(&port->lock, flags);
671 sc16is7xx_stop_tx(port);
672 spin_unlock_irqrestore(&port->lock, flags);
673 return;
674 }
675
676 /* Get length of data pending in circular buffer */
677 to_send = uart_circ_chars_pending(xmit);
678 if (likely(to_send)) {
679 /* Limit to size of TX FIFO */
680 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
681 if (txlen > SC16IS7XX_FIFO_SIZE) {
682 dev_err_ratelimited(port->dev,
683 "chip reports %d free bytes in TX fifo, but it only has %d",
684 txlen, SC16IS7XX_FIFO_SIZE);
685 txlen = 0;
686 }
687 to_send = (to_send > txlen) ? txlen : to_send;
688
689 /* Convert to linear buffer */
690 for (i = 0; i < to_send; ++i) {
691 s->buf[i] = xmit->buf[xmit->tail];
692 uart_xmit_advance(port, 1);
693 }
694
695 sc16is7xx_fifo_write(port, to_send);
696 }
697
698 spin_lock_irqsave(&port->lock, flags);
699 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
700 uart_write_wakeup(port);
701
702 if (uart_circ_empty(xmit))
703 sc16is7xx_stop_tx(port);
704 spin_unlock_irqrestore(&port->lock, flags);
705}
706
707static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
708{
709 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
710 unsigned int mctrl = 0;
711
712 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
713 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
714 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0;
715 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0;
716 return mctrl;
717}
718
719static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
720{
721 struct uart_port *port = &one->port;
722 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
723 unsigned long flags;
724 unsigned int status, changed;
725
726 lockdep_assert_held_once(&s->efr_lock);
727
728 status = sc16is7xx_get_hwmctrl(port);
729 changed = status ^ one->old_mctrl;
730
731 if (changed == 0)
732 return;
733
734 one->old_mctrl = status;
735
736 spin_lock_irqsave(&port->lock, flags);
737 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
738 port->icount.rng++;
739 if (changed & TIOCM_DSR)
740 port->icount.dsr++;
741 if (changed & TIOCM_CAR)
742 uart_handle_dcd_change(port, status & TIOCM_CAR);
743 if (changed & TIOCM_CTS)
744 uart_handle_cts_change(port, status & TIOCM_CTS);
745
746 wake_up_interruptible(&port->state->port.delta_msr_wait);
747 spin_unlock_irqrestore(&port->lock, flags);
748}
749
750static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
751{
752 struct uart_port *port = &s->p[portno].port;
753
754 do {
755 unsigned int iir, rxlen;
756 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
757
758 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
759 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
760 return false;
761
762 iir &= SC16IS7XX_IIR_ID_MASK;
763
764 switch (iir) {
765 case SC16IS7XX_IIR_RDI_SRC:
766 case SC16IS7XX_IIR_RLSE_SRC:
767 case SC16IS7XX_IIR_RTOI_SRC:
768 case SC16IS7XX_IIR_XOFFI_SRC:
769 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
770 if (rxlen)
771 sc16is7xx_handle_rx(port, rxlen, iir);
772 break;
773 /* CTSRTS interrupt comes only when CTS goes inactive */
774 case SC16IS7XX_IIR_CTSRTS_SRC:
775 case SC16IS7XX_IIR_MSI_SRC:
776 sc16is7xx_update_mlines(one);
777 break;
778 case SC16IS7XX_IIR_THRI_SRC:
779 sc16is7xx_handle_tx(port);
780 break;
781 default:
782 dev_err_ratelimited(port->dev,
783 "ttySC%i: Unexpected interrupt: %x",
784 port->line, iir);
785 break;
786 }
787 } while (0);
788 return true;
789}
790
791static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
792{
793 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
794
795 mutex_lock(&s->efr_lock);
796
797 while (1) {
798 bool keep_polling = false;
799 int i;
800
801 for (i = 0; i < s->devtype->nr_uart; ++i)
802 keep_polling |= sc16is7xx_port_irq(s, i);
803 if (!keep_polling)
804 break;
805 }
806
807 mutex_unlock(&s->efr_lock);
808
809 return IRQ_HANDLED;
810}
811
812static void sc16is7xx_tx_proc(struct kthread_work *ws)
813{
814 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
815 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
816 unsigned long flags;
817
818 if ((port->rs485.flags & SER_RS485_ENABLED) &&
819 (port->rs485.delay_rts_before_send > 0))
820 msleep(port->rs485.delay_rts_before_send);
821
822 mutex_lock(&s->efr_lock);
823 sc16is7xx_handle_tx(port);
824 mutex_unlock(&s->efr_lock);
825
826 spin_lock_irqsave(&port->lock, flags);
827 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
828 spin_unlock_irqrestore(&port->lock, flags);
829}
830
831static void sc16is7xx_reconf_rs485(struct uart_port *port)
832{
833 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
834 SC16IS7XX_EFCR_RTS_INVERT_BIT;
835 u32 efcr = 0;
836 struct serial_rs485 *rs485 = &port->rs485;
837 unsigned long irqflags;
838
839 spin_lock_irqsave(&port->lock, irqflags);
840 if (rs485->flags & SER_RS485_ENABLED) {
841 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
842
843 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
844 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
845 }
846 spin_unlock_irqrestore(&port->lock, irqflags);
847
848 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
849}
850
851static void sc16is7xx_reg_proc(struct kthread_work *ws)
852{
853 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
854 struct sc16is7xx_one_config config;
855 unsigned long irqflags;
856
857 spin_lock_irqsave(&one->port.lock, irqflags);
858 config = one->config;
859 memset(&one->config, 0, sizeof(one->config));
860 spin_unlock_irqrestore(&one->port.lock, irqflags);
861
862 if (config.flags & SC16IS7XX_RECONF_MD) {
863 u8 mcr = 0;
864
865 /* Device ignores RTS setting when hardware flow is enabled */
866 if (one->port.mctrl & TIOCM_RTS)
867 mcr |= SC16IS7XX_MCR_RTS_BIT;
868
869 if (one->port.mctrl & TIOCM_DTR)
870 mcr |= SC16IS7XX_MCR_DTR_BIT;
871
872 if (one->port.mctrl & TIOCM_LOOP)
873 mcr |= SC16IS7XX_MCR_LOOP_BIT;
874 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
875 SC16IS7XX_MCR_RTS_BIT |
876 SC16IS7XX_MCR_DTR_BIT |
877 SC16IS7XX_MCR_LOOP_BIT,
878 mcr);
879 }
880
881 if (config.flags & SC16IS7XX_RECONF_IER)
882 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
883 config.ier_mask, config.ier_val);
884
885 if (config.flags & SC16IS7XX_RECONF_RS485)
886 sc16is7xx_reconf_rs485(&one->port);
887}
888
889static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
890{
891 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
892 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
893
894 lockdep_assert_held_once(&port->lock);
895
896 one->config.flags |= SC16IS7XX_RECONF_IER;
897 one->config.ier_mask |= bit;
898 one->config.ier_val &= ~bit;
899 kthread_queue_work(&s->kworker, &one->reg_work);
900}
901
902static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
903{
904 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
905 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
906
907 lockdep_assert_held_once(&port->lock);
908
909 one->config.flags |= SC16IS7XX_RECONF_IER;
910 one->config.ier_mask |= bit;
911 one->config.ier_val |= bit;
912 kthread_queue_work(&s->kworker, &one->reg_work);
913}
914
915static void sc16is7xx_stop_tx(struct uart_port *port)
916{
917 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
918}
919
920static void sc16is7xx_stop_rx(struct uart_port *port)
921{
922 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
923}
924
925static void sc16is7xx_ms_proc(struct kthread_work *ws)
926{
927 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work);
928 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
929
930 if (one->port.state) {
931 mutex_lock(&s->efr_lock);
932 sc16is7xx_update_mlines(one);
933 mutex_unlock(&s->efr_lock);
934
935 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
936 }
937}
938
939static void sc16is7xx_enable_ms(struct uart_port *port)
940{
941 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
942 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
943
944 lockdep_assert_held_once(&port->lock);
945
946 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
947}
948
949static void sc16is7xx_start_tx(struct uart_port *port)
950{
951 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
952 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
953
954 kthread_queue_work(&s->kworker, &one->tx_work);
955}
956
957static void sc16is7xx_throttle(struct uart_port *port)
958{
959 unsigned long flags;
960
961 /*
962 * Hardware flow control is enabled and thus the device ignores RTS
963 * value set in MCR register. Stop reading data from RX FIFO so the
964 * AutoRTS feature will de-activate RTS output.
965 */
966 spin_lock_irqsave(&port->lock, flags);
967 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
968 spin_unlock_irqrestore(&port->lock, flags);
969}
970
971static void sc16is7xx_unthrottle(struct uart_port *port)
972{
973 unsigned long flags;
974
975 spin_lock_irqsave(&port->lock, flags);
976 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
977 spin_unlock_irqrestore(&port->lock, flags);
978}
979
980static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
981{
982 unsigned int lsr;
983
984 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
985
986 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
987}
988
989static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
990{
991 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
992
993 /* Called with port lock taken so we can only return cached value */
994 return one->old_mctrl;
995}
996
997static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
998{
999 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1000 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1001
1002 one->config.flags |= SC16IS7XX_RECONF_MD;
1003 kthread_queue_work(&s->kworker, &one->reg_work);
1004}
1005
1006static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
1007{
1008 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
1009 SC16IS7XX_LCR_TXBREAK_BIT,
1010 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
1011}
1012
1013static void sc16is7xx_set_termios(struct uart_port *port,
1014 struct ktermios *termios,
1015 const struct ktermios *old)
1016{
1017 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1018 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1019 unsigned int lcr, flow = 0;
1020 int baud;
1021 unsigned long flags;
1022
1023 kthread_cancel_delayed_work_sync(&one->ms_work);
1024
1025 /* Mask termios capabilities we don't support */
1026 termios->c_cflag &= ~CMSPAR;
1027
1028 /* Word size */
1029 switch (termios->c_cflag & CSIZE) {
1030 case CS5:
1031 lcr = SC16IS7XX_LCR_WORD_LEN_5;
1032 break;
1033 case CS6:
1034 lcr = SC16IS7XX_LCR_WORD_LEN_6;
1035 break;
1036 case CS7:
1037 lcr = SC16IS7XX_LCR_WORD_LEN_7;
1038 break;
1039 case CS8:
1040 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1041 break;
1042 default:
1043 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1044 termios->c_cflag &= ~CSIZE;
1045 termios->c_cflag |= CS8;
1046 break;
1047 }
1048
1049 /* Parity */
1050 if (termios->c_cflag & PARENB) {
1051 lcr |= SC16IS7XX_LCR_PARITY_BIT;
1052 if (!(termios->c_cflag & PARODD))
1053 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
1054 }
1055
1056 /* Stop bits */
1057 if (termios->c_cflag & CSTOPB)
1058 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
1059
1060 /* Set read status mask */
1061 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
1062 if (termios->c_iflag & INPCK)
1063 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
1064 SC16IS7XX_LSR_FE_BIT;
1065 if (termios->c_iflag & (BRKINT | PARMRK))
1066 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
1067
1068 /* Set status ignore mask */
1069 port->ignore_status_mask = 0;
1070 if (termios->c_iflag & IGNBRK)
1071 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
1072 if (!(termios->c_cflag & CREAD))
1073 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
1074
1075 /* As above, claim the mutex while accessing the EFR. */
1076 mutex_lock(&s->efr_lock);
1077
1078 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1079 SC16IS7XX_LCR_CONF_MODE_B);
1080
1081 /* Configure flow control */
1082 regcache_cache_bypass(s->regmap, true);
1083 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
1084 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
1085
1086 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1087 if (termios->c_cflag & CRTSCTS) {
1088 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
1089 SC16IS7XX_EFR_AUTORTS_BIT;
1090 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1091 }
1092 if (termios->c_iflag & IXON)
1093 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
1094 if (termios->c_iflag & IXOFF)
1095 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
1096
1097 sc16is7xx_port_update(port,
1098 SC16IS7XX_EFR_REG,
1099 SC16IS7XX_EFR_FLOWCTRL_BITS,
1100 flow);
1101 regcache_cache_bypass(s->regmap, false);
1102
1103 /* Update LCR register */
1104 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
1105
1106 mutex_unlock(&s->efr_lock);
1107
1108 /* Get baud rate generator configuration */
1109 baud = uart_get_baud_rate(port, termios, old,
1110 port->uartclk / 16 / 4 / 0xffff,
1111 port->uartclk / 16);
1112
1113 /* Setup baudrate generator */
1114 baud = sc16is7xx_set_baud(port, baud);
1115
1116 spin_lock_irqsave(&port->lock, flags);
1117
1118 /* Update timeout according to new baud rate */
1119 uart_update_timeout(port, termios->c_cflag, baud);
1120
1121 if (UART_ENABLE_MS(port, termios->c_cflag))
1122 sc16is7xx_enable_ms(port);
1123
1124 spin_unlock_irqrestore(&port->lock, flags);
1125}
1126
1127static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,
1128 struct serial_rs485 *rs485)
1129{
1130 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1131 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1132
1133 if (rs485->flags & SER_RS485_ENABLED) {
1134 /*
1135 * RTS signal is handled by HW, it's timing can't be influenced.
1136 * However, it's sometimes useful to delay TX even without RTS
1137 * control therefore we try to handle .delay_rts_before_send.
1138 */
1139 if (rs485->delay_rts_after_send)
1140 return -EINVAL;
1141 }
1142
1143 one->config.flags |= SC16IS7XX_RECONF_RS485;
1144 kthread_queue_work(&s->kworker, &one->reg_work);
1145
1146 return 0;
1147}
1148
1149static int sc16is7xx_startup(struct uart_port *port)
1150{
1151 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1152 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1153 unsigned int val;
1154 unsigned long flags;
1155
1156 sc16is7xx_power(port, 1);
1157
1158 /* Reset FIFOs*/
1159 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1160 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1161 udelay(5);
1162 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1163 SC16IS7XX_FCR_FIFO_BIT);
1164
1165 /* Enable EFR */
1166 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1167 SC16IS7XX_LCR_CONF_MODE_B);
1168
1169 regcache_cache_bypass(s->regmap, true);
1170
1171 /* Enable write access to enhanced features and internal clock div */
1172 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1173 SC16IS7XX_EFR_ENABLE_BIT,
1174 SC16IS7XX_EFR_ENABLE_BIT);
1175
1176 /* Enable TCR/TLR */
1177 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1178 SC16IS7XX_MCR_TCRTLR_BIT,
1179 SC16IS7XX_MCR_TCRTLR_BIT);
1180
1181 /* Configure flow control levels */
1182 /* Flow control halt level 48, resume level 24 */
1183 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1184 SC16IS7XX_TCR_RX_RESUME(24) |
1185 SC16IS7XX_TCR_RX_HALT(48));
1186
1187 regcache_cache_bypass(s->regmap, false);
1188
1189 /* Now, initialize the UART */
1190 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1191
1192 /* Enable IrDA mode if requested in DT */
1193 /* This bit must be written with LCR[7] = 0 */
1194 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1195 SC16IS7XX_MCR_IRDA_BIT,
1196 one->irda_mode ?
1197 SC16IS7XX_MCR_IRDA_BIT : 0);
1198
1199 /* Enable the Rx and Tx FIFO */
1200 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1201 SC16IS7XX_EFCR_RXDISABLE_BIT |
1202 SC16IS7XX_EFCR_TXDISABLE_BIT,
1203 0);
1204
1205 /* Enable RX, CTS change and modem lines interrupts */
1206 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
1207 SC16IS7XX_IER_MSI_BIT;
1208 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1209
1210 /* Enable modem status polling */
1211 spin_lock_irqsave(&port->lock, flags);
1212 sc16is7xx_enable_ms(port);
1213 spin_unlock_irqrestore(&port->lock, flags);
1214
1215 return 0;
1216}
1217
1218static void sc16is7xx_shutdown(struct uart_port *port)
1219{
1220 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1221 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1222
1223 kthread_cancel_delayed_work_sync(&one->ms_work);
1224
1225 /* Disable all interrupts */
1226 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1227 /* Disable TX/RX */
1228 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1229 SC16IS7XX_EFCR_RXDISABLE_BIT |
1230 SC16IS7XX_EFCR_TXDISABLE_BIT,
1231 SC16IS7XX_EFCR_RXDISABLE_BIT |
1232 SC16IS7XX_EFCR_TXDISABLE_BIT);
1233
1234 sc16is7xx_power(port, 0);
1235
1236 kthread_flush_worker(&s->kworker);
1237}
1238
1239static const char *sc16is7xx_type(struct uart_port *port)
1240{
1241 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1242
1243 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1244}
1245
1246static int sc16is7xx_request_port(struct uart_port *port)
1247{
1248 /* Do nothing */
1249 return 0;
1250}
1251
1252static void sc16is7xx_config_port(struct uart_port *port, int flags)
1253{
1254 if (flags & UART_CONFIG_TYPE)
1255 port->type = PORT_SC16IS7XX;
1256}
1257
1258static int sc16is7xx_verify_port(struct uart_port *port,
1259 struct serial_struct *s)
1260{
1261 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1262 return -EINVAL;
1263 if (s->irq != port->irq)
1264 return -EINVAL;
1265
1266 return 0;
1267}
1268
1269static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1270 unsigned int oldstate)
1271{
1272 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1273}
1274
1275static void sc16is7xx_null_void(struct uart_port *port)
1276{
1277 /* Do nothing */
1278}
1279
1280static const struct uart_ops sc16is7xx_ops = {
1281 .tx_empty = sc16is7xx_tx_empty,
1282 .set_mctrl = sc16is7xx_set_mctrl,
1283 .get_mctrl = sc16is7xx_get_mctrl,
1284 .stop_tx = sc16is7xx_stop_tx,
1285 .start_tx = sc16is7xx_start_tx,
1286 .throttle = sc16is7xx_throttle,
1287 .unthrottle = sc16is7xx_unthrottle,
1288 .stop_rx = sc16is7xx_stop_rx,
1289 .enable_ms = sc16is7xx_enable_ms,
1290 .break_ctl = sc16is7xx_break_ctl,
1291 .startup = sc16is7xx_startup,
1292 .shutdown = sc16is7xx_shutdown,
1293 .set_termios = sc16is7xx_set_termios,
1294 .type = sc16is7xx_type,
1295 .request_port = sc16is7xx_request_port,
1296 .release_port = sc16is7xx_null_void,
1297 .config_port = sc16is7xx_config_port,
1298 .verify_port = sc16is7xx_verify_port,
1299 .pm = sc16is7xx_pm,
1300};
1301
1302#ifdef CONFIG_GPIOLIB
1303static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1304{
1305 unsigned int val;
1306 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1307 struct uart_port *port = &s->p[0].port;
1308
1309 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1310
1311 return !!(val & BIT(offset));
1312}
1313
1314static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1315{
1316 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1317 struct uart_port *port = &s->p[0].port;
1318
1319 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1320 val ? BIT(offset) : 0);
1321}
1322
1323static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1324 unsigned offset)
1325{
1326 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1327 struct uart_port *port = &s->p[0].port;
1328
1329 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1330
1331 return 0;
1332}
1333
1334static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1335 unsigned offset, int val)
1336{
1337 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1338 struct uart_port *port = &s->p[0].port;
1339 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1340
1341 if (val)
1342 state |= BIT(offset);
1343 else
1344 state &= ~BIT(offset);
1345 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1346 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1347 BIT(offset));
1348
1349 return 0;
1350}
1351#endif
1352
1353static const struct serial_rs485 sc16is7xx_rs485_supported = {
1354 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND,
1355 .delay_rts_before_send = 1,
1356 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */
1357};
1358
1359static int sc16is7xx_probe(struct device *dev,
1360 const struct sc16is7xx_devtype *devtype,
1361 struct regmap *regmap, int irq)
1362{
1363 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1364 unsigned int val;
1365 u32 uartclk = 0;
1366 int i, ret;
1367 struct sc16is7xx_port *s;
1368
1369 if (IS_ERR(regmap))
1370 return PTR_ERR(regmap);
1371
1372 /*
1373 * This device does not have an identification register that would
1374 * tell us if we are really connected to the correct device.
1375 * The best we can do is to check if communication is at all possible.
1376 */
1377 ret = regmap_read(regmap,
1378 SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val);
1379 if (ret < 0)
1380 return -EPROBE_DEFER;
1381
1382 /* Alloc port structure */
1383 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1384 if (!s) {
1385 dev_err(dev, "Error allocating port structure\n");
1386 return -ENOMEM;
1387 }
1388
1389 /* Always ask for fixed clock rate from a property. */
1390 device_property_read_u32(dev, "clock-frequency", &uartclk);
1391
1392 s->clk = devm_clk_get_optional(dev, NULL);
1393 if (IS_ERR(s->clk))
1394 return PTR_ERR(s->clk);
1395
1396 ret = clk_prepare_enable(s->clk);
1397 if (ret)
1398 return ret;
1399
1400 freq = clk_get_rate(s->clk);
1401 if (freq == 0) {
1402 if (uartclk)
1403 freq = uartclk;
1404 if (pfreq)
1405 freq = *pfreq;
1406 if (freq)
1407 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1408 else
1409 return -EINVAL;
1410 }
1411
1412 s->regmap = regmap;
1413 s->devtype = devtype;
1414 dev_set_drvdata(dev, s);
1415 mutex_init(&s->efr_lock);
1416
1417 kthread_init_worker(&s->kworker);
1418 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1419 "sc16is7xx");
1420 if (IS_ERR(s->kworker_task)) {
1421 ret = PTR_ERR(s->kworker_task);
1422 goto out_clk;
1423 }
1424 sched_set_fifo(s->kworker_task);
1425
1426#ifdef CONFIG_GPIOLIB
1427 if (devtype->nr_gpio) {
1428 /* Setup GPIO cotroller */
1429 s->gpio.owner = THIS_MODULE;
1430 s->gpio.parent = dev;
1431 s->gpio.label = dev_name(dev);
1432 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1433 s->gpio.get = sc16is7xx_gpio_get;
1434 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1435 s->gpio.set = sc16is7xx_gpio_set;
1436 s->gpio.base = -1;
1437 s->gpio.ngpio = devtype->nr_gpio;
1438 s->gpio.can_sleep = 1;
1439 ret = gpiochip_add_data(&s->gpio, s);
1440 if (ret)
1441 goto out_thread;
1442 }
1443#endif
1444
1445 /* reset device, purging any pending irq / data */
1446 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
1447 SC16IS7XX_IOCONTROL_SRESET_BIT);
1448
1449 for (i = 0; i < devtype->nr_uart; ++i) {
1450 s->p[i].line = i;
1451 /* Initialize port data */
1452 s->p[i].port.dev = dev;
1453 s->p[i].port.irq = irq;
1454 s->p[i].port.type = PORT_SC16IS7XX;
1455 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1456 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1457 s->p[i].port.iobase = i;
1458 s->p[i].port.iotype = UPIO_PORT;
1459 s->p[i].port.uartclk = freq;
1460 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1461 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported;
1462 s->p[i].port.ops = &sc16is7xx_ops;
1463 s->p[i].old_mctrl = 0;
1464 s->p[i].port.line = sc16is7xx_alloc_line();
1465
1466 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1467 ret = -ENOMEM;
1468 goto out_ports;
1469 }
1470
1471 /* Disable all interrupts */
1472 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1473 /* Disable TX/RX */
1474 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1475 SC16IS7XX_EFCR_RXDISABLE_BIT |
1476 SC16IS7XX_EFCR_TXDISABLE_BIT);
1477
1478 /* Use GPIO lines as modem status registers */
1479 if (devtype->has_mctrl)
1480 sc16is7xx_port_write(&s->p[i].port,
1481 SC16IS7XX_IOCONTROL_REG,
1482 SC16IS7XX_IOCONTROL_MODEM_BIT);
1483
1484 /* Initialize kthread work structs */
1485 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1486 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1487 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc);
1488 /* Register port */
1489 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1490
1491 /* Enable EFR */
1492 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1493 SC16IS7XX_LCR_CONF_MODE_B);
1494
1495 regcache_cache_bypass(s->regmap, true);
1496
1497 /* Enable write access to enhanced features */
1498 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1499 SC16IS7XX_EFR_ENABLE_BIT);
1500
1501 regcache_cache_bypass(s->regmap, false);
1502
1503 /* Restore access to general registers */
1504 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1505
1506 /* Go to suspend mode */
1507 sc16is7xx_power(&s->p[i].port, 0);
1508 }
1509
1510 if (dev->of_node) {
1511 struct property *prop;
1512 const __be32 *p;
1513 u32 u;
1514
1515 of_property_for_each_u32(dev->of_node, "irda-mode-ports",
1516 prop, p, u)
1517 if (u < devtype->nr_uart)
1518 s->p[u].irda_mode = true;
1519 }
1520
1521 /*
1522 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1523 * If that succeeds, we can allow sharing the interrupt as well.
1524 * In case the interrupt controller doesn't support that, we fall
1525 * back to a non-shared falling-edge trigger.
1526 */
1527 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1528 IRQF_TRIGGER_LOW | IRQF_SHARED |
1529 IRQF_ONESHOT,
1530 dev_name(dev), s);
1531 if (!ret)
1532 return 0;
1533
1534 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1535 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1536 dev_name(dev), s);
1537 if (!ret)
1538 return 0;
1539
1540out_ports:
1541 for (i--; i >= 0; i--) {
1542 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1543 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1544 }
1545
1546#ifdef CONFIG_GPIOLIB
1547 if (devtype->nr_gpio)
1548 gpiochip_remove(&s->gpio);
1549
1550out_thread:
1551#endif
1552 kthread_stop(s->kworker_task);
1553
1554out_clk:
1555 clk_disable_unprepare(s->clk);
1556
1557 return ret;
1558}
1559
1560static void sc16is7xx_remove(struct device *dev)
1561{
1562 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1563 int i;
1564
1565#ifdef CONFIG_GPIOLIB
1566 if (s->devtype->nr_gpio)
1567 gpiochip_remove(&s->gpio);
1568#endif
1569
1570 for (i = 0; i < s->devtype->nr_uart; i++) {
1571 kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
1572 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1573 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1574 sc16is7xx_power(&s->p[i].port, 0);
1575 }
1576
1577 kthread_flush_worker(&s->kworker);
1578 kthread_stop(s->kworker_task);
1579
1580 clk_disable_unprepare(s->clk);
1581}
1582
1583static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1584 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1585 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1586 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1587 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1588 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1589 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1590 { }
1591};
1592MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1593
1594static struct regmap_config regcfg = {
1595 .reg_bits = 7,
1596 .pad_bits = 1,
1597 .val_bits = 8,
1598 .cache_type = REGCACHE_RBTREE,
1599 .volatile_reg = sc16is7xx_regmap_volatile,
1600 .precious_reg = sc16is7xx_regmap_precious,
1601};
1602
1603#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1604static int sc16is7xx_spi_probe(struct spi_device *spi)
1605{
1606 const struct sc16is7xx_devtype *devtype;
1607 struct regmap *regmap;
1608 int ret;
1609
1610 /* Setup SPI bus */
1611 spi->bits_per_word = 8;
1612 /* only supports mode 0 on SC16IS762 */
1613 spi->mode = spi->mode ? : SPI_MODE_0;
1614 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1615 ret = spi_setup(spi);
1616 if (ret)
1617 return ret;
1618
1619 if (spi->dev.of_node) {
1620 devtype = device_get_match_data(&spi->dev);
1621 if (!devtype)
1622 return -ENODEV;
1623 } else {
1624 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1625
1626 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1627 }
1628
1629 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1630 (devtype->nr_uart - 1);
1631 regmap = devm_regmap_init_spi(spi, ®cfg);
1632
1633 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq);
1634}
1635
1636static void sc16is7xx_spi_remove(struct spi_device *spi)
1637{
1638 sc16is7xx_remove(&spi->dev);
1639}
1640
1641static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1642 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1643 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1644 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1645 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1646 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1647 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1648 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1649 { }
1650};
1651
1652MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1653
1654static struct spi_driver sc16is7xx_spi_uart_driver = {
1655 .driver = {
1656 .name = SC16IS7XX_NAME,
1657 .of_match_table = sc16is7xx_dt_ids,
1658 },
1659 .probe = sc16is7xx_spi_probe,
1660 .remove = sc16is7xx_spi_remove,
1661 .id_table = sc16is7xx_spi_id_table,
1662};
1663
1664MODULE_ALIAS("spi:sc16is7xx");
1665#endif
1666
1667#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1668static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1669 const struct i2c_device_id *id)
1670{
1671 const struct sc16is7xx_devtype *devtype;
1672 struct regmap *regmap;
1673
1674 if (i2c->dev.of_node) {
1675 devtype = device_get_match_data(&i2c->dev);
1676 if (!devtype)
1677 return -ENODEV;
1678 } else {
1679 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1680 }
1681
1682 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1683 (devtype->nr_uart - 1);
1684 regmap = devm_regmap_init_i2c(i2c, ®cfg);
1685
1686 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq);
1687}
1688
1689static void sc16is7xx_i2c_remove(struct i2c_client *client)
1690{
1691 sc16is7xx_remove(&client->dev);
1692}
1693
1694static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1695 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1696 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1697 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1698 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1699 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1700 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1701 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1702 { }
1703};
1704MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1705
1706static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1707 .driver = {
1708 .name = SC16IS7XX_NAME,
1709 .of_match_table = sc16is7xx_dt_ids,
1710 },
1711 .probe = sc16is7xx_i2c_probe,
1712 .remove = sc16is7xx_i2c_remove,
1713 .id_table = sc16is7xx_i2c_id_table,
1714};
1715
1716#endif
1717
1718static int __init sc16is7xx_init(void)
1719{
1720 int ret;
1721
1722 ret = uart_register_driver(&sc16is7xx_uart);
1723 if (ret) {
1724 pr_err("Registering UART driver failed\n");
1725 return ret;
1726 }
1727
1728#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1729 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1730 if (ret < 0) {
1731 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1732 goto err_i2c;
1733 }
1734#endif
1735
1736#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1737 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1738 if (ret < 0) {
1739 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1740 goto err_spi;
1741 }
1742#endif
1743 return ret;
1744
1745#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1746err_spi:
1747#endif
1748#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1749 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1750err_i2c:
1751#endif
1752 uart_unregister_driver(&sc16is7xx_uart);
1753 return ret;
1754}
1755module_init(sc16is7xx_init);
1756
1757static void __exit sc16is7xx_exit(void)
1758{
1759#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1760 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1761#endif
1762
1763#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1764 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1765#endif
1766 uart_unregister_driver(&sc16is7xx_uart);
1767}
1768module_exit(sc16is7xx_exit);
1769
1770MODULE_LICENSE("GPL");
1771MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1772MODULE_DESCRIPTION("SC16IS7XX serial driver");
1/*
2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
4 *
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/bitops.h>
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/device.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/regmap.h>
26#include <linux/serial_core.h>
27#include <linux/serial.h>
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30#include <linux/spi/spi.h>
31#include <linux/uaccess.h>
32
33#define SC16IS7XX_NAME "sc16is7xx"
34#define SC16IS7XX_MAX_DEVS 8
35
36/* SC16IS7XX register definitions */
37#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
38#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
39#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
40#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
41#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
42#define SC16IS7XX_LCR_REG (0x03) /* Line Control */
43#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
44#define SC16IS7XX_LSR_REG (0x05) /* Line Status */
45#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
46#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
47#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
48#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
49#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
50 * - only on 75x/76x
51 */
52#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
53 * - only on 75x/76x
54 */
55#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
56 * - only on 75x/76x
57 */
58#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
59 * - only on 75x/76x
60 */
61#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
62
63/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
64#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
65#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
66
67/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
68#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
69#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
70
71/* Enhanced Register set: Only if (LCR == 0xBF) */
72#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
73#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
74#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
75#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
76#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
77
78/* IER register bits */
79#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
80#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
81 * interrupt */
82#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
83 * interrupt */
84#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
85 * interrupt */
86
87/* IER register bits - write only if (EFR[4] == 1) */
88#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
89#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
90#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
91#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
92
93/* FCR register bits */
94#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
95#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
96#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
97#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
98#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
99
100/* FCR register bits - write only if (EFR[4] == 1) */
101#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
102#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
103
104/* IIR register bits */
105#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
106#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
107#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
108#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
109#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
110#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
111#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
112 * - only on 75x/76x
113 */
114#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
115 * - only on 75x/76x
116 */
117#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
118#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
119 * from active (LOW)
120 * to inactive (HIGH)
121 */
122/* LCR register bits */
123#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
124#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
125 *
126 * Word length bits table:
127 * 00 -> 5 bit words
128 * 01 -> 6 bit words
129 * 10 -> 7 bit words
130 * 11 -> 8 bit words
131 */
132#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
133 *
134 * STOP length bit table:
135 * 0 -> 1 stop bit
136 * 1 -> 1-1.5 stop bits if
137 * word length is 5,
138 * 2 stop bits otherwise
139 */
140#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
141#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
142#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
143#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
144#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
145#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
146#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
147#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
148#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
149#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
150 * reg set */
151#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
152 * reg set */
153
154/* MCR register bits */
155#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
156 * - only on 75x/76x
157 */
158#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
159#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
160#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
161#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
162 * - write enabled
163 * if (EFR[4] == 1)
164 */
165#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
166 * - write enabled
167 * if (EFR[4] == 1)
168 */
169#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
170 * - write enabled
171 * if (EFR[4] == 1)
172 */
173
174/* LSR register bits */
175#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
176#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
177#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
178#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
179#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
180#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
181#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
182#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
183#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
184
185/* MSR register bits */
186#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
187#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
188 * or (IO4)
189 * - only on 75x/76x
190 */
191#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
192 * or (IO7)
193 * - only on 75x/76x
194 */
195#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
196 * or (IO6)
197 * - only on 75x/76x
198 */
199#define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
200#define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
201 * - only on 75x/76x
202 */
203#define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
204 * - only on 75x/76x
205 */
206#define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
207 * - only on 75x/76x
208 */
209#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
210
211/*
212 * TCR register bits
213 * TCR trigger levels are available from 0 to 60 characters with a granularity
214 * of four.
215 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
216 * no built-in hardware check to make sure this condition is met. Also, the TCR
217 * must be programmed with this condition before auto RTS or software flow
218 * control is enabled to avoid spurious operation of the device.
219 */
220#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
221#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
222
223/*
224 * TLR register bits
225 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
226 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
227 * trigger levels. Trigger levels from 4 characters to 60 characters are
228 * available with a granularity of four.
229 *
230 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
231 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
232 * the trigger level defined in FCR is discarded. This applies to both transmit
233 * FIFO and receive FIFO trigger level setting.
234 *
235 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
236 * default state, that is, '00'.
237 */
238#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
239#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
240
241/* IOControl register bits (Only 750/760) */
242#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
243#define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
244#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
245
246/* EFCR register bits */
247#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
248 * mode (RS485) */
249#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
250#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
251#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
252#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
253#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
254 * 0 = rate upto 115.2 kbit/s
255 * - Only 750/760
256 * 1 = rate upto 1.152 Mbit/s
257 * - Only 760
258 */
259
260/* EFR register bits */
261#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
262#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
263#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
264#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
265 * and writing to IER[7:4],
266 * FCR[5:4], MCR[7:5]
267 */
268#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
269#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
270 *
271 * SWFLOW bits 3 & 2 table:
272 * 00 -> no transmitter flow
273 * control
274 * 01 -> transmitter generates
275 * XON2 and XOFF2
276 * 10 -> transmitter generates
277 * XON1 and XOFF1
278 * 11 -> transmitter generates
279 * XON1, XON2, XOFF1 and
280 * XOFF2
281 */
282#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
283#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
284 *
285 * SWFLOW bits 3 & 2 table:
286 * 00 -> no received flow
287 * control
288 * 01 -> receiver compares
289 * XON2 and XOFF2
290 * 10 -> receiver compares
291 * XON1 and XOFF1
292 * 11 -> receiver compares
293 * XON1, XON2, XOFF1 and
294 * XOFF2
295 */
296
297/* Misc definitions */
298#define SC16IS7XX_FIFO_SIZE (64)
299#define SC16IS7XX_REG_SHIFT 2
300
301struct sc16is7xx_devtype {
302 char name[10];
303 int nr_gpio;
304 int nr_uart;
305};
306
307#define SC16IS7XX_RECONF_MD (1 << 0)
308#define SC16IS7XX_RECONF_IER (1 << 1)
309#define SC16IS7XX_RECONF_RS485 (1 << 2)
310
311struct sc16is7xx_one_config {
312 unsigned int flags;
313 u8 ier_clear;
314};
315
316struct sc16is7xx_one {
317 struct uart_port port;
318 u8 line;
319 struct kthread_work tx_work;
320 struct kthread_work reg_work;
321 struct sc16is7xx_one_config config;
322};
323
324struct sc16is7xx_port {
325 const struct sc16is7xx_devtype *devtype;
326 struct regmap *regmap;
327 struct clk *clk;
328#ifdef CONFIG_GPIOLIB
329 struct gpio_chip gpio;
330#endif
331 unsigned char buf[SC16IS7XX_FIFO_SIZE];
332 struct kthread_worker kworker;
333 struct task_struct *kworker_task;
334 struct kthread_work irq_work;
335 struct sc16is7xx_one p[0];
336};
337
338static unsigned long sc16is7xx_lines;
339
340static struct uart_driver sc16is7xx_uart = {
341 .owner = THIS_MODULE,
342 .dev_name = "ttySC",
343 .nr = SC16IS7XX_MAX_DEVS,
344};
345
346#define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
347#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
348
349static int sc16is7xx_line(struct uart_port *port)
350{
351 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
352
353 return one->line;
354}
355
356static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
357{
358 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
359 unsigned int val = 0;
360 const u8 line = sc16is7xx_line(port);
361
362 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
363
364 return val;
365}
366
367static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
368{
369 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
370 const u8 line = sc16is7xx_line(port);
371
372 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
373}
374
375static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
376{
377 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
378 const u8 line = sc16is7xx_line(port);
379 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
380
381 regcache_cache_bypass(s->regmap, true);
382 regmap_raw_read(s->regmap, addr, s->buf, rxlen);
383 regcache_cache_bypass(s->regmap, false);
384}
385
386static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
387{
388 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
389 const u8 line = sc16is7xx_line(port);
390 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
391
392 /*
393 * Don't send zero-length data, at least on SPI it confuses the chip
394 * delivering wrong TXLVL data.
395 */
396 if (unlikely(!to_send))
397 return;
398
399 regcache_cache_bypass(s->regmap, true);
400 regmap_raw_write(s->regmap, addr, s->buf, to_send);
401 regcache_cache_bypass(s->regmap, false);
402}
403
404static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
405 u8 mask, u8 val)
406{
407 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
408 const u8 line = sc16is7xx_line(port);
409
410 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
411 mask, val);
412}
413
414static int sc16is7xx_alloc_line(void)
415{
416 int i;
417
418 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
419
420 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
421 if (!test_and_set_bit(i, &sc16is7xx_lines))
422 break;
423
424 return i;
425}
426
427static void sc16is7xx_power(struct uart_port *port, int on)
428{
429 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
430 SC16IS7XX_IER_SLEEP_BIT,
431 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
432}
433
434static const struct sc16is7xx_devtype sc16is74x_devtype = {
435 .name = "SC16IS74X",
436 .nr_gpio = 0,
437 .nr_uart = 1,
438};
439
440static const struct sc16is7xx_devtype sc16is750_devtype = {
441 .name = "SC16IS750",
442 .nr_gpio = 8,
443 .nr_uart = 1,
444};
445
446static const struct sc16is7xx_devtype sc16is752_devtype = {
447 .name = "SC16IS752",
448 .nr_gpio = 8,
449 .nr_uart = 2,
450};
451
452static const struct sc16is7xx_devtype sc16is760_devtype = {
453 .name = "SC16IS760",
454 .nr_gpio = 8,
455 .nr_uart = 1,
456};
457
458static const struct sc16is7xx_devtype sc16is762_devtype = {
459 .name = "SC16IS762",
460 .nr_gpio = 8,
461 .nr_uart = 2,
462};
463
464static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
465{
466 switch (reg >> SC16IS7XX_REG_SHIFT) {
467 case SC16IS7XX_RHR_REG:
468 case SC16IS7XX_IIR_REG:
469 case SC16IS7XX_LSR_REG:
470 case SC16IS7XX_MSR_REG:
471 case SC16IS7XX_TXLVL_REG:
472 case SC16IS7XX_RXLVL_REG:
473 case SC16IS7XX_IOSTATE_REG:
474 return true;
475 default:
476 break;
477 }
478
479 return false;
480}
481
482static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
483{
484 switch (reg >> SC16IS7XX_REG_SHIFT) {
485 case SC16IS7XX_RHR_REG:
486 return true;
487 default:
488 break;
489 }
490
491 return false;
492}
493
494static int sc16is7xx_set_baud(struct uart_port *port, int baud)
495{
496 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
497 u8 lcr;
498 u8 prescaler = 0;
499 unsigned long clk = port->uartclk, div = clk / 16 / baud;
500
501 if (div > 0xffff) {
502 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
503 div /= 4;
504 }
505
506 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
507
508 /* Open the LCR divisors for configuration */
509 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
510 SC16IS7XX_LCR_CONF_MODE_B);
511
512 /* Enable enhanced features */
513 regcache_cache_bypass(s->regmap, true);
514 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
515 SC16IS7XX_EFR_ENABLE_BIT);
516 regcache_cache_bypass(s->regmap, false);
517
518 /* Put LCR back to the normal mode */
519 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
520
521 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
522 SC16IS7XX_MCR_CLKSEL_BIT,
523 prescaler);
524
525 /* Open the LCR divisors for configuration */
526 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
527 SC16IS7XX_LCR_CONF_MODE_A);
528
529 /* Write the new divisor */
530 regcache_cache_bypass(s->regmap, true);
531 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
532 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
533 regcache_cache_bypass(s->regmap, false);
534
535 /* Put LCR back to the normal mode */
536 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
537
538 return DIV_ROUND_CLOSEST(clk / 16, div);
539}
540
541static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
542 unsigned int iir)
543{
544 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
545 unsigned int lsr = 0, ch, flag, bytes_read, i;
546 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
547
548 if (unlikely(rxlen >= sizeof(s->buf))) {
549 dev_warn_ratelimited(port->dev,
550 "ttySC%i: Possible RX FIFO overrun: %d\n",
551 port->line, rxlen);
552 port->icount.buf_overrun++;
553 /* Ensure sanity of RX level */
554 rxlen = sizeof(s->buf);
555 }
556
557 while (rxlen) {
558 /* Only read lsr if there are possible errors in FIFO */
559 if (read_lsr) {
560 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
561 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
562 read_lsr = false; /* No errors left in FIFO */
563 } else
564 lsr = 0;
565
566 if (read_lsr) {
567 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
568 bytes_read = 1;
569 } else {
570 sc16is7xx_fifo_read(port, rxlen);
571 bytes_read = rxlen;
572 }
573
574 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
575
576 port->icount.rx++;
577 flag = TTY_NORMAL;
578
579 if (unlikely(lsr)) {
580 if (lsr & SC16IS7XX_LSR_BI_BIT) {
581 port->icount.brk++;
582 if (uart_handle_break(port))
583 continue;
584 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
585 port->icount.parity++;
586 else if (lsr & SC16IS7XX_LSR_FE_BIT)
587 port->icount.frame++;
588 else if (lsr & SC16IS7XX_LSR_OE_BIT)
589 port->icount.overrun++;
590
591 lsr &= port->read_status_mask;
592 if (lsr & SC16IS7XX_LSR_BI_BIT)
593 flag = TTY_BREAK;
594 else if (lsr & SC16IS7XX_LSR_PE_BIT)
595 flag = TTY_PARITY;
596 else if (lsr & SC16IS7XX_LSR_FE_BIT)
597 flag = TTY_FRAME;
598 else if (lsr & SC16IS7XX_LSR_OE_BIT)
599 flag = TTY_OVERRUN;
600 }
601
602 for (i = 0; i < bytes_read; ++i) {
603 ch = s->buf[i];
604 if (uart_handle_sysrq_char(port, ch))
605 continue;
606
607 if (lsr & port->ignore_status_mask)
608 continue;
609
610 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
611 flag);
612 }
613 rxlen -= bytes_read;
614 }
615
616 tty_flip_buffer_push(&port->state->port);
617}
618
619static void sc16is7xx_handle_tx(struct uart_port *port)
620{
621 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
622 struct circ_buf *xmit = &port->state->xmit;
623 unsigned int txlen, to_send, i;
624
625 if (unlikely(port->x_char)) {
626 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
627 port->icount.tx++;
628 port->x_char = 0;
629 return;
630 }
631
632 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
633 return;
634
635 /* Get length of data pending in circular buffer */
636 to_send = uart_circ_chars_pending(xmit);
637 if (likely(to_send)) {
638 /* Limit to size of TX FIFO */
639 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
640 if (txlen > SC16IS7XX_FIFO_SIZE) {
641 dev_err_ratelimited(port->dev,
642 "chip reports %d free bytes in TX fifo, but it only has %d",
643 txlen, SC16IS7XX_FIFO_SIZE);
644 txlen = 0;
645 }
646 to_send = (to_send > txlen) ? txlen : to_send;
647
648 /* Add data to send */
649 port->icount.tx += to_send;
650
651 /* Convert to linear buffer */
652 for (i = 0; i < to_send; ++i) {
653 s->buf[i] = xmit->buf[xmit->tail];
654 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
655 }
656
657 sc16is7xx_fifo_write(port, to_send);
658 }
659
660 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
661 uart_write_wakeup(port);
662}
663
664static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
665{
666 struct uart_port *port = &s->p[portno].port;
667
668 do {
669 unsigned int iir, msr, rxlen;
670
671 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
672 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
673 break;
674
675 iir &= SC16IS7XX_IIR_ID_MASK;
676
677 switch (iir) {
678 case SC16IS7XX_IIR_RDI_SRC:
679 case SC16IS7XX_IIR_RLSE_SRC:
680 case SC16IS7XX_IIR_RTOI_SRC:
681 case SC16IS7XX_IIR_XOFFI_SRC:
682 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
683 if (rxlen)
684 sc16is7xx_handle_rx(port, rxlen, iir);
685 break;
686
687 case SC16IS7XX_IIR_CTSRTS_SRC:
688 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
689 uart_handle_cts_change(port,
690 !!(msr & SC16IS7XX_MSR_DCTS_BIT));
691 break;
692 case SC16IS7XX_IIR_THRI_SRC:
693 sc16is7xx_handle_tx(port);
694 break;
695 default:
696 dev_err_ratelimited(port->dev,
697 "ttySC%i: Unexpected interrupt: %x",
698 port->line, iir);
699 break;
700 }
701 } while (1);
702}
703
704static void sc16is7xx_ist(struct kthread_work *ws)
705{
706 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work);
707 int i;
708
709 for (i = 0; i < s->devtype->nr_uart; ++i)
710 sc16is7xx_port_irq(s, i);
711}
712
713static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
714{
715 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
716
717 queue_kthread_work(&s->kworker, &s->irq_work);
718
719 return IRQ_HANDLED;
720}
721
722static void sc16is7xx_tx_proc(struct kthread_work *ws)
723{
724 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
725
726 if ((port->rs485.flags & SER_RS485_ENABLED) &&
727 (port->rs485.delay_rts_before_send > 0))
728 msleep(port->rs485.delay_rts_before_send);
729
730 sc16is7xx_handle_tx(port);
731}
732
733static void sc16is7xx_reconf_rs485(struct uart_port *port)
734{
735 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
736 SC16IS7XX_EFCR_RTS_INVERT_BIT;
737 u32 efcr = 0;
738 struct serial_rs485 *rs485 = &port->rs485;
739 unsigned long irqflags;
740
741 spin_lock_irqsave(&port->lock, irqflags);
742 if (rs485->flags & SER_RS485_ENABLED) {
743 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
744
745 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
746 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
747 }
748 spin_unlock_irqrestore(&port->lock, irqflags);
749
750 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
751}
752
753static void sc16is7xx_reg_proc(struct kthread_work *ws)
754{
755 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
756 struct sc16is7xx_one_config config;
757 unsigned long irqflags;
758
759 spin_lock_irqsave(&one->port.lock, irqflags);
760 config = one->config;
761 memset(&one->config, 0, sizeof(one->config));
762 spin_unlock_irqrestore(&one->port.lock, irqflags);
763
764 if (config.flags & SC16IS7XX_RECONF_MD) {
765 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
766 SC16IS7XX_MCR_LOOP_BIT,
767 (one->port.mctrl & TIOCM_LOOP) ?
768 SC16IS7XX_MCR_LOOP_BIT : 0);
769 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
770 SC16IS7XX_MCR_RTS_BIT,
771 (one->port.mctrl & TIOCM_RTS) ?
772 SC16IS7XX_MCR_RTS_BIT : 0);
773 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
774 SC16IS7XX_MCR_DTR_BIT,
775 (one->port.mctrl & TIOCM_DTR) ?
776 SC16IS7XX_MCR_DTR_BIT : 0);
777 }
778 if (config.flags & SC16IS7XX_RECONF_IER)
779 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
780 config.ier_clear, 0);
781
782 if (config.flags & SC16IS7XX_RECONF_RS485)
783 sc16is7xx_reconf_rs485(&one->port);
784}
785
786static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
787{
788 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
789 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
790
791 one->config.flags |= SC16IS7XX_RECONF_IER;
792 one->config.ier_clear |= bit;
793 queue_kthread_work(&s->kworker, &one->reg_work);
794}
795
796static void sc16is7xx_stop_tx(struct uart_port *port)
797{
798 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
799}
800
801static void sc16is7xx_stop_rx(struct uart_port *port)
802{
803 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
804}
805
806static void sc16is7xx_start_tx(struct uart_port *port)
807{
808 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
809 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
810
811 queue_kthread_work(&s->kworker, &one->tx_work);
812}
813
814static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
815{
816 unsigned int lsr;
817
818 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
819
820 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
821}
822
823static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
824{
825 /* DCD and DSR are not wired and CTS/RTS is handled automatically
826 * so just indicate DSR and CAR asserted
827 */
828 return TIOCM_DSR | TIOCM_CAR;
829}
830
831static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
832{
833 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
834 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
835
836 one->config.flags |= SC16IS7XX_RECONF_MD;
837 queue_kthread_work(&s->kworker, &one->reg_work);
838}
839
840static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
841{
842 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
843 SC16IS7XX_LCR_TXBREAK_BIT,
844 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
845}
846
847static void sc16is7xx_set_termios(struct uart_port *port,
848 struct ktermios *termios,
849 struct ktermios *old)
850{
851 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
852 unsigned int lcr, flow = 0;
853 int baud;
854
855 /* Mask termios capabilities we don't support */
856 termios->c_cflag &= ~CMSPAR;
857
858 /* Word size */
859 switch (termios->c_cflag & CSIZE) {
860 case CS5:
861 lcr = SC16IS7XX_LCR_WORD_LEN_5;
862 break;
863 case CS6:
864 lcr = SC16IS7XX_LCR_WORD_LEN_6;
865 break;
866 case CS7:
867 lcr = SC16IS7XX_LCR_WORD_LEN_7;
868 break;
869 case CS8:
870 lcr = SC16IS7XX_LCR_WORD_LEN_8;
871 break;
872 default:
873 lcr = SC16IS7XX_LCR_WORD_LEN_8;
874 termios->c_cflag &= ~CSIZE;
875 termios->c_cflag |= CS8;
876 break;
877 }
878
879 /* Parity */
880 if (termios->c_cflag & PARENB) {
881 lcr |= SC16IS7XX_LCR_PARITY_BIT;
882 if (!(termios->c_cflag & PARODD))
883 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
884 }
885
886 /* Stop bits */
887 if (termios->c_cflag & CSTOPB)
888 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
889
890 /* Set read status mask */
891 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
892 if (termios->c_iflag & INPCK)
893 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
894 SC16IS7XX_LSR_FE_BIT;
895 if (termios->c_iflag & (BRKINT | PARMRK))
896 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
897
898 /* Set status ignore mask */
899 port->ignore_status_mask = 0;
900 if (termios->c_iflag & IGNBRK)
901 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
902 if (!(termios->c_cflag & CREAD))
903 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
904
905 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
906 SC16IS7XX_LCR_CONF_MODE_B);
907
908 /* Configure flow control */
909 regcache_cache_bypass(s->regmap, true);
910 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
911 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
912 if (termios->c_cflag & CRTSCTS)
913 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
914 SC16IS7XX_EFR_AUTORTS_BIT;
915 if (termios->c_iflag & IXON)
916 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
917 if (termios->c_iflag & IXOFF)
918 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
919
920 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
921 regcache_cache_bypass(s->regmap, false);
922
923 /* Update LCR register */
924 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
925
926 /* Get baud rate generator configuration */
927 baud = uart_get_baud_rate(port, termios, old,
928 port->uartclk / 16 / 4 / 0xffff,
929 port->uartclk / 16);
930
931 /* Setup baudrate generator */
932 baud = sc16is7xx_set_baud(port, baud);
933
934 /* Update timeout according to new baud rate */
935 uart_update_timeout(port, termios->c_cflag, baud);
936}
937
938static int sc16is7xx_config_rs485(struct uart_port *port,
939 struct serial_rs485 *rs485)
940{
941 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
942 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
943
944 if (rs485->flags & SER_RS485_ENABLED) {
945 bool rts_during_rx, rts_during_tx;
946
947 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
948 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
949
950 if (rts_during_rx == rts_during_tx)
951 dev_err(port->dev,
952 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
953 rts_during_tx, rts_during_rx);
954
955 /*
956 * RTS signal is handled by HW, it's timing can't be influenced.
957 * However, it's sometimes useful to delay TX even without RTS
958 * control therefore we try to handle .delay_rts_before_send.
959 */
960 if (rs485->delay_rts_after_send)
961 return -EINVAL;
962 }
963
964 port->rs485 = *rs485;
965 one->config.flags |= SC16IS7XX_RECONF_RS485;
966 queue_kthread_work(&s->kworker, &one->reg_work);
967
968 return 0;
969}
970
971static int sc16is7xx_startup(struct uart_port *port)
972{
973 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
974 unsigned int val;
975
976 sc16is7xx_power(port, 1);
977
978 /* Reset FIFOs*/
979 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
980 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
981 udelay(5);
982 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
983 SC16IS7XX_FCR_FIFO_BIT);
984
985 /* Enable EFR */
986 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
987 SC16IS7XX_LCR_CONF_MODE_B);
988
989 regcache_cache_bypass(s->regmap, true);
990
991 /* Enable write access to enhanced features and internal clock div */
992 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
993 SC16IS7XX_EFR_ENABLE_BIT);
994
995 /* Enable TCR/TLR */
996 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
997 SC16IS7XX_MCR_TCRTLR_BIT,
998 SC16IS7XX_MCR_TCRTLR_BIT);
999
1000 /* Configure flow control levels */
1001 /* Flow control halt level 48, resume level 24 */
1002 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1003 SC16IS7XX_TCR_RX_RESUME(24) |
1004 SC16IS7XX_TCR_RX_HALT(48));
1005
1006 regcache_cache_bypass(s->regmap, false);
1007
1008 /* Now, initialize the UART */
1009 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1010
1011 /* Enable the Rx and Tx FIFO */
1012 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1013 SC16IS7XX_EFCR_RXDISABLE_BIT |
1014 SC16IS7XX_EFCR_TXDISABLE_BIT,
1015 0);
1016
1017 /* Enable RX, TX, CTS change interrupts */
1018 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT |
1019 SC16IS7XX_IER_CTSI_BIT;
1020 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1021
1022 return 0;
1023}
1024
1025static void sc16is7xx_shutdown(struct uart_port *port)
1026{
1027 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1028
1029 /* Disable all interrupts */
1030 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1031 /* Disable TX/RX */
1032 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1033 SC16IS7XX_EFCR_RXDISABLE_BIT |
1034 SC16IS7XX_EFCR_TXDISABLE_BIT,
1035 SC16IS7XX_EFCR_RXDISABLE_BIT |
1036 SC16IS7XX_EFCR_TXDISABLE_BIT);
1037
1038 sc16is7xx_power(port, 0);
1039
1040 flush_kthread_worker(&s->kworker);
1041}
1042
1043static const char *sc16is7xx_type(struct uart_port *port)
1044{
1045 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1046
1047 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1048}
1049
1050static int sc16is7xx_request_port(struct uart_port *port)
1051{
1052 /* Do nothing */
1053 return 0;
1054}
1055
1056static void sc16is7xx_config_port(struct uart_port *port, int flags)
1057{
1058 if (flags & UART_CONFIG_TYPE)
1059 port->type = PORT_SC16IS7XX;
1060}
1061
1062static int sc16is7xx_verify_port(struct uart_port *port,
1063 struct serial_struct *s)
1064{
1065 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1066 return -EINVAL;
1067 if (s->irq != port->irq)
1068 return -EINVAL;
1069
1070 return 0;
1071}
1072
1073static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1074 unsigned int oldstate)
1075{
1076 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1077}
1078
1079static void sc16is7xx_null_void(struct uart_port *port)
1080{
1081 /* Do nothing */
1082}
1083
1084static const struct uart_ops sc16is7xx_ops = {
1085 .tx_empty = sc16is7xx_tx_empty,
1086 .set_mctrl = sc16is7xx_set_mctrl,
1087 .get_mctrl = sc16is7xx_get_mctrl,
1088 .stop_tx = sc16is7xx_stop_tx,
1089 .start_tx = sc16is7xx_start_tx,
1090 .stop_rx = sc16is7xx_stop_rx,
1091 .break_ctl = sc16is7xx_break_ctl,
1092 .startup = sc16is7xx_startup,
1093 .shutdown = sc16is7xx_shutdown,
1094 .set_termios = sc16is7xx_set_termios,
1095 .type = sc16is7xx_type,
1096 .request_port = sc16is7xx_request_port,
1097 .release_port = sc16is7xx_null_void,
1098 .config_port = sc16is7xx_config_port,
1099 .verify_port = sc16is7xx_verify_port,
1100 .pm = sc16is7xx_pm,
1101};
1102
1103#ifdef CONFIG_GPIOLIB
1104static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1105{
1106 unsigned int val;
1107 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1108 gpio);
1109 struct uart_port *port = &s->p[0].port;
1110
1111 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1112
1113 return !!(val & BIT(offset));
1114}
1115
1116static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1117{
1118 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1119 gpio);
1120 struct uart_port *port = &s->p[0].port;
1121
1122 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1123 val ? BIT(offset) : 0);
1124}
1125
1126static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1127 unsigned offset)
1128{
1129 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1130 gpio);
1131 struct uart_port *port = &s->p[0].port;
1132
1133 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1134
1135 return 0;
1136}
1137
1138static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1139 unsigned offset, int val)
1140{
1141 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1142 gpio);
1143 struct uart_port *port = &s->p[0].port;
1144
1145 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1146 val ? BIT(offset) : 0);
1147 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1148 BIT(offset));
1149
1150 return 0;
1151}
1152#endif
1153
1154static int sc16is7xx_probe(struct device *dev,
1155 const struct sc16is7xx_devtype *devtype,
1156 struct regmap *regmap, int irq, unsigned long flags)
1157{
1158 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 };
1159 unsigned long freq, *pfreq = dev_get_platdata(dev);
1160 int i, ret;
1161 struct sc16is7xx_port *s;
1162
1163 if (IS_ERR(regmap))
1164 return PTR_ERR(regmap);
1165
1166 /* Alloc port structure */
1167 s = devm_kzalloc(dev, sizeof(*s) +
1168 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1169 GFP_KERNEL);
1170 if (!s) {
1171 dev_err(dev, "Error allocating port structure\n");
1172 return -ENOMEM;
1173 }
1174
1175 s->clk = devm_clk_get(dev, NULL);
1176 if (IS_ERR(s->clk)) {
1177 if (pfreq)
1178 freq = *pfreq;
1179 else
1180 return PTR_ERR(s->clk);
1181 } else {
1182 clk_prepare_enable(s->clk);
1183 freq = clk_get_rate(s->clk);
1184 }
1185
1186 s->regmap = regmap;
1187 s->devtype = devtype;
1188 dev_set_drvdata(dev, s);
1189
1190 init_kthread_worker(&s->kworker);
1191 init_kthread_work(&s->irq_work, sc16is7xx_ist);
1192 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1193 "sc16is7xx");
1194 if (IS_ERR(s->kworker_task)) {
1195 ret = PTR_ERR(s->kworker_task);
1196 goto out_clk;
1197 }
1198 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param);
1199
1200#ifdef CONFIG_GPIOLIB
1201 if (devtype->nr_gpio) {
1202 /* Setup GPIO cotroller */
1203 s->gpio.owner = THIS_MODULE;
1204 s->gpio.parent = dev;
1205 s->gpio.label = dev_name(dev);
1206 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1207 s->gpio.get = sc16is7xx_gpio_get;
1208 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1209 s->gpio.set = sc16is7xx_gpio_set;
1210 s->gpio.base = -1;
1211 s->gpio.ngpio = devtype->nr_gpio;
1212 s->gpio.can_sleep = 1;
1213 ret = gpiochip_add(&s->gpio);
1214 if (ret)
1215 goto out_thread;
1216 }
1217#endif
1218
1219 for (i = 0; i < devtype->nr_uart; ++i) {
1220 s->p[i].line = i;
1221 /* Initialize port data */
1222 s->p[i].port.dev = dev;
1223 s->p[i].port.irq = irq;
1224 s->p[i].port.type = PORT_SC16IS7XX;
1225 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1226 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1227 s->p[i].port.iotype = UPIO_PORT;
1228 s->p[i].port.uartclk = freq;
1229 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1230 s->p[i].port.ops = &sc16is7xx_ops;
1231 s->p[i].port.line = sc16is7xx_alloc_line();
1232 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1233 ret = -ENOMEM;
1234 goto out_ports;
1235 }
1236
1237 /* Disable all interrupts */
1238 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1239 /* Disable TX/RX */
1240 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1241 SC16IS7XX_EFCR_RXDISABLE_BIT |
1242 SC16IS7XX_EFCR_TXDISABLE_BIT);
1243 /* Initialize kthread work structs */
1244 init_kthread_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1245 init_kthread_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1246 /* Register port */
1247 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1248 /* Go to suspend mode */
1249 sc16is7xx_power(&s->p[i].port, 0);
1250 }
1251
1252 /* Setup interrupt */
1253 ret = devm_request_irq(dev, irq, sc16is7xx_irq,
1254 IRQF_ONESHOT | flags, dev_name(dev), s);
1255 if (!ret)
1256 return 0;
1257
1258out_ports:
1259 for (i--; i >= 0; i--) {
1260 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1261 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1262 }
1263
1264#ifdef CONFIG_GPIOLIB
1265 if (devtype->nr_gpio)
1266 gpiochip_remove(&s->gpio);
1267
1268out_thread:
1269#endif
1270 kthread_stop(s->kworker_task);
1271
1272out_clk:
1273 if (!IS_ERR(s->clk))
1274 clk_disable_unprepare(s->clk);
1275
1276 return ret;
1277}
1278
1279static int sc16is7xx_remove(struct device *dev)
1280{
1281 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1282 int i;
1283
1284#ifdef CONFIG_GPIOLIB
1285 if (s->devtype->nr_gpio)
1286 gpiochip_remove(&s->gpio);
1287#endif
1288
1289 for (i = 0; i < s->devtype->nr_uart; i++) {
1290 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1291 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1292 sc16is7xx_power(&s->p[i].port, 0);
1293 }
1294
1295 flush_kthread_worker(&s->kworker);
1296 kthread_stop(s->kworker_task);
1297
1298 if (!IS_ERR(s->clk))
1299 clk_disable_unprepare(s->clk);
1300
1301 return 0;
1302}
1303
1304static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1305 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1306 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1307 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1308 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1309 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1310 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1311 { }
1312};
1313MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1314
1315static struct regmap_config regcfg = {
1316 .reg_bits = 7,
1317 .pad_bits = 1,
1318 .val_bits = 8,
1319 .cache_type = REGCACHE_RBTREE,
1320 .volatile_reg = sc16is7xx_regmap_volatile,
1321 .precious_reg = sc16is7xx_regmap_precious,
1322};
1323
1324#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1325static int sc16is7xx_spi_probe(struct spi_device *spi)
1326{
1327 const struct sc16is7xx_devtype *devtype;
1328 unsigned long flags = 0;
1329 struct regmap *regmap;
1330 int ret;
1331
1332 /* Setup SPI bus */
1333 spi->bits_per_word = 8;
1334 /* only supports mode 0 on SC16IS762 */
1335 spi->mode = spi->mode ? : SPI_MODE_0;
1336 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1337 ret = spi_setup(spi);
1338 if (ret)
1339 return ret;
1340
1341 if (spi->dev.of_node) {
1342 const struct of_device_id *of_id =
1343 of_match_device(sc16is7xx_dt_ids, &spi->dev);
1344
1345 if (!of_id)
1346 return -ENODEV;
1347
1348 devtype = (struct sc16is7xx_devtype *)of_id->data;
1349 } else {
1350 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1351
1352 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1353 flags = IRQF_TRIGGER_FALLING;
1354 }
1355
1356 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1357 (devtype->nr_uart - 1);
1358 regmap = devm_regmap_init_spi(spi, ®cfg);
1359
1360 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1361}
1362
1363static int sc16is7xx_spi_remove(struct spi_device *spi)
1364{
1365 return sc16is7xx_remove(&spi->dev);
1366}
1367
1368static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1369 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1370 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1371 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1372 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1373 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1374 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1375 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1376 { }
1377};
1378
1379MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1380
1381static struct spi_driver sc16is7xx_spi_uart_driver = {
1382 .driver = {
1383 .name = SC16IS7XX_NAME,
1384 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1385 },
1386 .probe = sc16is7xx_spi_probe,
1387 .remove = sc16is7xx_spi_remove,
1388 .id_table = sc16is7xx_spi_id_table,
1389};
1390
1391MODULE_ALIAS("spi:sc16is7xx");
1392#endif
1393
1394#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1395static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1396 const struct i2c_device_id *id)
1397{
1398 const struct sc16is7xx_devtype *devtype;
1399 unsigned long flags = 0;
1400 struct regmap *regmap;
1401
1402 if (i2c->dev.of_node) {
1403 const struct of_device_id *of_id =
1404 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1405
1406 if (!of_id)
1407 return -ENODEV;
1408
1409 devtype = (struct sc16is7xx_devtype *)of_id->data;
1410 } else {
1411 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1412 flags = IRQF_TRIGGER_FALLING;
1413 }
1414
1415 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1416 (devtype->nr_uart - 1);
1417 regmap = devm_regmap_init_i2c(i2c, ®cfg);
1418
1419 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1420}
1421
1422static int sc16is7xx_i2c_remove(struct i2c_client *client)
1423{
1424 return sc16is7xx_remove(&client->dev);
1425}
1426
1427static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1428 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1429 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1430 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1431 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1432 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1433 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1434 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1435 { }
1436};
1437MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1438
1439static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1440 .driver = {
1441 .name = SC16IS7XX_NAME,
1442 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1443 },
1444 .probe = sc16is7xx_i2c_probe,
1445 .remove = sc16is7xx_i2c_remove,
1446 .id_table = sc16is7xx_i2c_id_table,
1447};
1448
1449#endif
1450
1451static int __init sc16is7xx_init(void)
1452{
1453 int ret;
1454
1455 ret = uart_register_driver(&sc16is7xx_uart);
1456 if (ret) {
1457 pr_err("Registering UART driver failed\n");
1458 return ret;
1459 }
1460
1461#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1462 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1463 if (ret < 0) {
1464 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1465 return ret;
1466 }
1467#endif
1468
1469#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1470 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1471 if (ret < 0) {
1472 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1473 return ret;
1474 }
1475#endif
1476 return ret;
1477}
1478module_init(sc16is7xx_init);
1479
1480static void __exit sc16is7xx_exit(void)
1481{
1482#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1483 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1484#endif
1485
1486#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1487 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1488#endif
1489 uart_unregister_driver(&sc16is7xx_uart);
1490}
1491module_exit(sc16is7xx_exit);
1492
1493MODULE_LICENSE("GPL");
1494MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1495MODULE_DESCRIPTION("SC16IS7XX serial driver");