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1/*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/gpio.h>
16#include <linux/slab.h>
17#include <linux/io.h>
18#include <linux/ioport.h>
19#include <linux/irq.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23#include <linux/dma-mapping.h>
24#include <linux/spi/spi.h>
25#include <linux/workqueue.h>
26
27#include <asm/dma.h>
28#include <asm/portmux.h>
29#include <asm/bfin5xx_spi.h>
30#include <asm/cacheflush.h>
31
32#define DRV_NAME "bfin-spi"
33#define DRV_AUTHOR "Bryan Wu, Luke Yang"
34#define DRV_DESC "Blackfin on-chip SPI Controller Driver"
35#define DRV_VERSION "1.0"
36
37MODULE_AUTHOR(DRV_AUTHOR);
38MODULE_DESCRIPTION(DRV_DESC);
39MODULE_LICENSE("GPL");
40
41#define START_STATE ((void *)0)
42#define RUNNING_STATE ((void *)1)
43#define DONE_STATE ((void *)2)
44#define ERROR_STATE ((void *)-1)
45
46struct bfin_spi_master_data;
47
48struct bfin_spi_transfer_ops {
49 void (*write) (struct bfin_spi_master_data *);
50 void (*read) (struct bfin_spi_master_data *);
51 void (*duplex) (struct bfin_spi_master_data *);
52};
53
54struct bfin_spi_master_data {
55 /* Driver model hookup */
56 struct platform_device *pdev;
57
58 /* SPI framework hookup */
59 struct spi_master *master;
60
61 /* Regs base of SPI controller */
62 struct bfin_spi_regs __iomem *regs;
63
64 /* Pin request list */
65 u16 *pin_req;
66
67 /* BFIN hookup */
68 struct bfin5xx_spi_master *master_info;
69
70 /* Driver message queue */
71 struct workqueue_struct *workqueue;
72 struct work_struct pump_messages;
73 spinlock_t lock;
74 struct list_head queue;
75 int busy;
76 bool running;
77
78 /* Message Transfer pump */
79 struct tasklet_struct pump_transfers;
80
81 /* Current message transfer state info */
82 struct spi_message *cur_msg;
83 struct spi_transfer *cur_transfer;
84 struct bfin_spi_slave_data *cur_chip;
85 size_t len_in_bytes;
86 size_t len;
87 void *tx;
88 void *tx_end;
89 void *rx;
90 void *rx_end;
91
92 /* DMA stuffs */
93 int dma_channel;
94 int dma_mapped;
95 int dma_requested;
96 dma_addr_t rx_dma;
97 dma_addr_t tx_dma;
98
99 int irq_requested;
100 int spi_irq;
101
102 size_t rx_map_len;
103 size_t tx_map_len;
104 u8 n_bytes;
105 u16 ctrl_reg;
106 u16 flag_reg;
107
108 int cs_change;
109 const struct bfin_spi_transfer_ops *ops;
110};
111
112struct bfin_spi_slave_data {
113 u16 ctl_reg;
114 u16 baud;
115 u16 flag;
116
117 u8 chip_select_num;
118 u8 enable_dma;
119 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
120 u32 cs_gpio;
121 u16 idle_tx_val;
122 u8 pio_interrupt; /* use spi data irq */
123 const struct bfin_spi_transfer_ops *ops;
124};
125
126static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
127{
128 bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE);
129}
130
131static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
132{
133 bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE);
134}
135
136/* Caculate the SPI_BAUD register value based on input HZ */
137static u16 hz_to_spi_baud(u32 speed_hz)
138{
139 u_long sclk = get_sclk();
140 u16 spi_baud = (sclk / (2 * speed_hz));
141
142 if ((sclk % (2 * speed_hz)) > 0)
143 spi_baud++;
144
145 if (spi_baud < MIN_SPI_BAUD_VAL)
146 spi_baud = MIN_SPI_BAUD_VAL;
147
148 return spi_baud;
149}
150
151static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
152{
153 unsigned long limit = loops_per_jiffy << 1;
154
155 /* wait for stop and clear stat */
156 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit)
157 cpu_relax();
158
159 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
160
161 return limit;
162}
163
164/* Chip select operation functions for cs_change flag */
165static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
166{
167 if (likely(chip->chip_select_num < MAX_CTRL_CS))
168 bfin_write_and(&drv_data->regs->flg, ~chip->flag);
169 else
170 gpio_set_value(chip->cs_gpio, 0);
171}
172
173static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
174 struct bfin_spi_slave_data *chip)
175{
176 if (likely(chip->chip_select_num < MAX_CTRL_CS))
177 bfin_write_or(&drv_data->regs->flg, chip->flag);
178 else
179 gpio_set_value(chip->cs_gpio, 1);
180
181 /* Move delay here for consistency */
182 if (chip->cs_chg_udelay)
183 udelay(chip->cs_chg_udelay);
184}
185
186/* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
187static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
188 struct bfin_spi_slave_data *chip)
189{
190 if (chip->chip_select_num < MAX_CTRL_CS)
191 bfin_write_or(&drv_data->regs->flg, chip->flag >> 8);
192}
193
194static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
195 struct bfin_spi_slave_data *chip)
196{
197 if (chip->chip_select_num < MAX_CTRL_CS)
198 bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8));
199}
200
201/* stop controller and re-config current chip*/
202static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
203{
204 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
205
206 /* Clear status and disable clock */
207 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
208 bfin_spi_disable(drv_data);
209 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
210
211 SSYNC();
212
213 /* Load the registers */
214 bfin_write(&drv_data->regs->ctl, chip->ctl_reg);
215 bfin_write(&drv_data->regs->baud, chip->baud);
216
217 bfin_spi_enable(drv_data);
218 bfin_spi_cs_active(drv_data, chip);
219}
220
221/* used to kick off transfer in rx mode and read unwanted RX data */
222static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
223{
224 (void) bfin_read(&drv_data->regs->rdbr);
225}
226
227static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
228{
229 /* clear RXS (we check for RXS inside the loop) */
230 bfin_spi_dummy_read(drv_data);
231
232 while (drv_data->tx < drv_data->tx_end) {
233 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
234 /* wait until transfer finished.
235 checking SPIF or TXS may not guarantee transfer completion */
236 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
237 cpu_relax();
238 /* discard RX data and clear RXS */
239 bfin_spi_dummy_read(drv_data);
240 }
241}
242
243static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
244{
245 u16 tx_val = drv_data->cur_chip->idle_tx_val;
246
247 /* discard old RX data and clear RXS */
248 bfin_spi_dummy_read(drv_data);
249
250 while (drv_data->rx < drv_data->rx_end) {
251 bfin_write(&drv_data->regs->tdbr, tx_val);
252 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
253 cpu_relax();
254 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
255 }
256}
257
258static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
259{
260 /* discard old RX data and clear RXS */
261 bfin_spi_dummy_read(drv_data);
262
263 while (drv_data->rx < drv_data->rx_end) {
264 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
265 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
266 cpu_relax();
267 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
268 }
269}
270
271static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
272 .write = bfin_spi_u8_writer,
273 .read = bfin_spi_u8_reader,
274 .duplex = bfin_spi_u8_duplex,
275};
276
277static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
278{
279 /* clear RXS (we check for RXS inside the loop) */
280 bfin_spi_dummy_read(drv_data);
281
282 while (drv_data->tx < drv_data->tx_end) {
283 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
284 drv_data->tx += 2;
285 /* wait until transfer finished.
286 checking SPIF or TXS may not guarantee transfer completion */
287 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
288 cpu_relax();
289 /* discard RX data and clear RXS */
290 bfin_spi_dummy_read(drv_data);
291 }
292}
293
294static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
295{
296 u16 tx_val = drv_data->cur_chip->idle_tx_val;
297
298 /* discard old RX data and clear RXS */
299 bfin_spi_dummy_read(drv_data);
300
301 while (drv_data->rx < drv_data->rx_end) {
302 bfin_write(&drv_data->regs->tdbr, tx_val);
303 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
304 cpu_relax();
305 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
306 drv_data->rx += 2;
307 }
308}
309
310static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
311{
312 /* discard old RX data and clear RXS */
313 bfin_spi_dummy_read(drv_data);
314
315 while (drv_data->rx < drv_data->rx_end) {
316 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
317 drv_data->tx += 2;
318 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
319 cpu_relax();
320 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
321 drv_data->rx += 2;
322 }
323}
324
325static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
326 .write = bfin_spi_u16_writer,
327 .read = bfin_spi_u16_reader,
328 .duplex = bfin_spi_u16_duplex,
329};
330
331/* test if there is more transfer to be done */
332static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
333{
334 struct spi_message *msg = drv_data->cur_msg;
335 struct spi_transfer *trans = drv_data->cur_transfer;
336
337 /* Move to next transfer */
338 if (trans->transfer_list.next != &msg->transfers) {
339 drv_data->cur_transfer =
340 list_entry(trans->transfer_list.next,
341 struct spi_transfer, transfer_list);
342 return RUNNING_STATE;
343 } else
344 return DONE_STATE;
345}
346
347/*
348 * caller already set message->status;
349 * dma and pio irqs are blocked give finished message back
350 */
351static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
352{
353 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
354 unsigned long flags;
355 struct spi_message *msg;
356
357 spin_lock_irqsave(&drv_data->lock, flags);
358 msg = drv_data->cur_msg;
359 drv_data->cur_msg = NULL;
360 drv_data->cur_transfer = NULL;
361 drv_data->cur_chip = NULL;
362 queue_work(drv_data->workqueue, &drv_data->pump_messages);
363 spin_unlock_irqrestore(&drv_data->lock, flags);
364
365 msg->state = NULL;
366
367 if (!drv_data->cs_change)
368 bfin_spi_cs_deactive(drv_data, chip);
369
370 /* Not stop spi in autobuffer mode */
371 if (drv_data->tx_dma != 0xFFFF)
372 bfin_spi_disable(drv_data);
373
374 if (msg->complete)
375 msg->complete(msg->context);
376}
377
378/* spi data irq handler */
379static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
380{
381 struct bfin_spi_master_data *drv_data = dev_id;
382 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
383 struct spi_message *msg = drv_data->cur_msg;
384 int n_bytes = drv_data->n_bytes;
385 int loop = 0;
386
387 /* wait until transfer finished. */
388 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
389 cpu_relax();
390
391 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
392 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
393 /* last read */
394 if (drv_data->rx) {
395 dev_dbg(&drv_data->pdev->dev, "last read\n");
396 if (!(n_bytes % 2)) {
397 u16 *buf = (u16 *)drv_data->rx;
398 for (loop = 0; loop < n_bytes / 2; loop++)
399 *buf++ = bfin_read(&drv_data->regs->rdbr);
400 } else {
401 u8 *buf = (u8 *)drv_data->rx;
402 for (loop = 0; loop < n_bytes; loop++)
403 *buf++ = bfin_read(&drv_data->regs->rdbr);
404 }
405 drv_data->rx += n_bytes;
406 }
407
408 msg->actual_length += drv_data->len_in_bytes;
409 if (drv_data->cs_change)
410 bfin_spi_cs_deactive(drv_data, chip);
411 /* Move to next transfer */
412 msg->state = bfin_spi_next_transfer(drv_data);
413
414 disable_irq_nosync(drv_data->spi_irq);
415
416 /* Schedule transfer tasklet */
417 tasklet_schedule(&drv_data->pump_transfers);
418 return IRQ_HANDLED;
419 }
420
421 if (drv_data->rx && drv_data->tx) {
422 /* duplex */
423 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
424 if (!(n_bytes % 2)) {
425 u16 *buf = (u16 *)drv_data->rx;
426 u16 *buf2 = (u16 *)drv_data->tx;
427 for (loop = 0; loop < n_bytes / 2; loop++) {
428 *buf++ = bfin_read(&drv_data->regs->rdbr);
429 bfin_write(&drv_data->regs->tdbr, *buf2++);
430 }
431 } else {
432 u8 *buf = (u8 *)drv_data->rx;
433 u8 *buf2 = (u8 *)drv_data->tx;
434 for (loop = 0; loop < n_bytes; loop++) {
435 *buf++ = bfin_read(&drv_data->regs->rdbr);
436 bfin_write(&drv_data->regs->tdbr, *buf2++);
437 }
438 }
439 } else if (drv_data->rx) {
440 /* read */
441 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
442 if (!(n_bytes % 2)) {
443 u16 *buf = (u16 *)drv_data->rx;
444 for (loop = 0; loop < n_bytes / 2; loop++) {
445 *buf++ = bfin_read(&drv_data->regs->rdbr);
446 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
447 }
448 } else {
449 u8 *buf = (u8 *)drv_data->rx;
450 for (loop = 0; loop < n_bytes; loop++) {
451 *buf++ = bfin_read(&drv_data->regs->rdbr);
452 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
453 }
454 }
455 } else if (drv_data->tx) {
456 /* write */
457 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
458 if (!(n_bytes % 2)) {
459 u16 *buf = (u16 *)drv_data->tx;
460 for (loop = 0; loop < n_bytes / 2; loop++) {
461 bfin_read(&drv_data->regs->rdbr);
462 bfin_write(&drv_data->regs->tdbr, *buf++);
463 }
464 } else {
465 u8 *buf = (u8 *)drv_data->tx;
466 for (loop = 0; loop < n_bytes; loop++) {
467 bfin_read(&drv_data->regs->rdbr);
468 bfin_write(&drv_data->regs->tdbr, *buf++);
469 }
470 }
471 }
472
473 if (drv_data->tx)
474 drv_data->tx += n_bytes;
475 if (drv_data->rx)
476 drv_data->rx += n_bytes;
477
478 return IRQ_HANDLED;
479}
480
481static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
482{
483 struct bfin_spi_master_data *drv_data = dev_id;
484 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
485 struct spi_message *msg = drv_data->cur_msg;
486 unsigned long timeout;
487 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
488 u16 spistat = bfin_read(&drv_data->regs->stat);
489
490 dev_dbg(&drv_data->pdev->dev,
491 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
492 dmastat, spistat);
493
494 if (drv_data->rx != NULL) {
495 u16 cr = bfin_read(&drv_data->regs->ctl);
496 /* discard old RX data and clear RXS */
497 bfin_spi_dummy_read(drv_data);
498 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
499 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */
500 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */
501 }
502
503 clear_dma_irqstat(drv_data->dma_channel);
504
505 /*
506 * wait for the last transaction shifted out. HRM states:
507 * at this point there may still be data in the SPI DMA FIFO waiting
508 * to be transmitted ... software needs to poll TXS in the SPI_STAT
509 * register until it goes low for 2 successive reads
510 */
511 if (drv_data->tx != NULL) {
512 while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) ||
513 (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS))
514 cpu_relax();
515 }
516
517 dev_dbg(&drv_data->pdev->dev,
518 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
519 dmastat, bfin_read(&drv_data->regs->stat));
520
521 timeout = jiffies + HZ;
522 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
523 if (!time_before(jiffies, timeout)) {
524 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF\n");
525 break;
526 } else
527 cpu_relax();
528
529 if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
530 msg->state = ERROR_STATE;
531 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
532 } else {
533 msg->actual_length += drv_data->len_in_bytes;
534
535 if (drv_data->cs_change)
536 bfin_spi_cs_deactive(drv_data, chip);
537
538 /* Move to next transfer */
539 msg->state = bfin_spi_next_transfer(drv_data);
540 }
541
542 /* Schedule transfer tasklet */
543 tasklet_schedule(&drv_data->pump_transfers);
544
545 /* free the irq handler before next transfer */
546 dev_dbg(&drv_data->pdev->dev,
547 "disable dma channel irq%d\n",
548 drv_data->dma_channel);
549 dma_disable_irq_nosync(drv_data->dma_channel);
550
551 return IRQ_HANDLED;
552}
553
554static void bfin_spi_pump_transfers(unsigned long data)
555{
556 struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
557 struct spi_message *message = NULL;
558 struct spi_transfer *transfer = NULL;
559 struct spi_transfer *previous = NULL;
560 struct bfin_spi_slave_data *chip = NULL;
561 unsigned int bits_per_word;
562 u16 cr, cr_width = 0, dma_width, dma_config;
563 u32 tranf_success = 1;
564 u8 full_duplex = 0;
565
566 /* Get current state information */
567 message = drv_data->cur_msg;
568 transfer = drv_data->cur_transfer;
569 chip = drv_data->cur_chip;
570
571 /*
572 * if msg is error or done, report it back using complete() callback
573 */
574
575 /* Handle for abort */
576 if (message->state == ERROR_STATE) {
577 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
578 message->status = -EIO;
579 bfin_spi_giveback(drv_data);
580 return;
581 }
582
583 /* Handle end of message */
584 if (message->state == DONE_STATE) {
585 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
586 message->status = 0;
587 bfin_spi_flush(drv_data);
588 bfin_spi_giveback(drv_data);
589 return;
590 }
591
592 /* Delay if requested at end of transfer */
593 if (message->state == RUNNING_STATE) {
594 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
595 previous = list_entry(transfer->transfer_list.prev,
596 struct spi_transfer, transfer_list);
597 if (previous->delay_usecs)
598 udelay(previous->delay_usecs);
599 }
600
601 /* Flush any existing transfers that may be sitting in the hardware */
602 if (bfin_spi_flush(drv_data) == 0) {
603 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
604 message->status = -EIO;
605 bfin_spi_giveback(drv_data);
606 return;
607 }
608
609 if (transfer->len == 0) {
610 /* Move to next transfer of this msg */
611 message->state = bfin_spi_next_transfer(drv_data);
612 /* Schedule next transfer tasklet */
613 tasklet_schedule(&drv_data->pump_transfers);
614 return;
615 }
616
617 if (transfer->tx_buf != NULL) {
618 drv_data->tx = (void *)transfer->tx_buf;
619 drv_data->tx_end = drv_data->tx + transfer->len;
620 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
621 transfer->tx_buf, drv_data->tx_end);
622 } else {
623 drv_data->tx = NULL;
624 }
625
626 if (transfer->rx_buf != NULL) {
627 full_duplex = transfer->tx_buf != NULL;
628 drv_data->rx = transfer->rx_buf;
629 drv_data->rx_end = drv_data->rx + transfer->len;
630 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
631 transfer->rx_buf, drv_data->rx_end);
632 } else {
633 drv_data->rx = NULL;
634 }
635
636 drv_data->rx_dma = transfer->rx_dma;
637 drv_data->tx_dma = transfer->tx_dma;
638 drv_data->len_in_bytes = transfer->len;
639 drv_data->cs_change = transfer->cs_change;
640
641 /* Bits per word setup */
642 bits_per_word = transfer->bits_per_word;
643 if (bits_per_word == 16) {
644 drv_data->n_bytes = bits_per_word/8;
645 drv_data->len = (transfer->len) >> 1;
646 cr_width = BIT_CTL_WORDSIZE;
647 drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
648 } else if (bits_per_word == 8) {
649 drv_data->n_bytes = bits_per_word/8;
650 drv_data->len = transfer->len;
651 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
652 }
653 cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
654 cr |= cr_width;
655 bfin_write(&drv_data->regs->ctl, cr);
656
657 dev_dbg(&drv_data->pdev->dev,
658 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
659 drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
660
661 message->state = RUNNING_STATE;
662 dma_config = 0;
663
664 bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz));
665
666 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
667 bfin_spi_cs_active(drv_data, chip);
668
669 dev_dbg(&drv_data->pdev->dev,
670 "now pumping a transfer: width is %d, len is %d\n",
671 cr_width, transfer->len);
672
673 /*
674 * Try to map dma buffer and do a dma transfer. If successful use,
675 * different way to r/w according to the enable_dma settings and if
676 * we are not doing a full duplex transfer (since the hardware does
677 * not support full duplex DMA transfers).
678 */
679 if (!full_duplex && drv_data->cur_chip->enable_dma
680 && drv_data->len > 6) {
681
682 unsigned long dma_start_addr, flags;
683
684 disable_dma(drv_data->dma_channel);
685 clear_dma_irqstat(drv_data->dma_channel);
686
687 /* config dma channel */
688 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
689 set_dma_x_count(drv_data->dma_channel, drv_data->len);
690 if (cr_width == BIT_CTL_WORDSIZE) {
691 set_dma_x_modify(drv_data->dma_channel, 2);
692 dma_width = WDSIZE_16;
693 } else {
694 set_dma_x_modify(drv_data->dma_channel, 1);
695 dma_width = WDSIZE_8;
696 }
697
698 /* poll for SPI completion before start */
699 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
700 cpu_relax();
701
702 /* dirty hack for autobuffer DMA mode */
703 if (drv_data->tx_dma == 0xFFFF) {
704 dev_dbg(&drv_data->pdev->dev,
705 "doing autobuffer DMA out.\n");
706
707 /* no irq in autobuffer mode */
708 dma_config =
709 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
710 set_dma_config(drv_data->dma_channel, dma_config);
711 set_dma_start_addr(drv_data->dma_channel,
712 (unsigned long)drv_data->tx);
713 enable_dma(drv_data->dma_channel);
714
715 /* start SPI transfer */
716 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX);
717
718 /* just return here, there can only be one transfer
719 * in this mode
720 */
721 message->status = 0;
722 bfin_spi_giveback(drv_data);
723 return;
724 }
725
726 /* In dma mode, rx or tx must be NULL in one transfer */
727 dma_config = (RESTART | dma_width | DI_EN);
728 if (drv_data->rx != NULL) {
729 /* set transfer mode, and enable SPI */
730 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
731 drv_data->rx, drv_data->len_in_bytes);
732
733 /* invalidate caches, if needed */
734 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
735 invalidate_dcache_range((unsigned long) drv_data->rx,
736 (unsigned long) (drv_data->rx +
737 drv_data->len_in_bytes));
738
739 dma_config |= WNR;
740 dma_start_addr = (unsigned long)drv_data->rx;
741 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
742
743 } else if (drv_data->tx != NULL) {
744 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
745
746 /* flush caches, if needed */
747 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
748 flush_dcache_range((unsigned long) drv_data->tx,
749 (unsigned long) (drv_data->tx +
750 drv_data->len_in_bytes));
751
752 dma_start_addr = (unsigned long)drv_data->tx;
753 cr |= BIT_CTL_TIMOD_DMA_TX;
754
755 } else
756 BUG();
757
758 /* oh man, here there be monsters ... and i dont mean the
759 * fluffy cute ones from pixar, i mean the kind that'll eat
760 * your data, kick your dog, and love it all. do *not* try
761 * and change these lines unless you (1) heavily test DMA
762 * with SPI flashes on a loaded system (e.g. ping floods),
763 * (2) know just how broken the DMA engine interaction with
764 * the SPI peripheral is, and (3) have someone else to blame
765 * when you screw it all up anyways.
766 */
767 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
768 set_dma_config(drv_data->dma_channel, dma_config);
769 local_irq_save(flags);
770 SSYNC();
771 bfin_write(&drv_data->regs->ctl, cr);
772 enable_dma(drv_data->dma_channel);
773 dma_enable_irq(drv_data->dma_channel);
774 local_irq_restore(flags);
775
776 return;
777 }
778
779 /*
780 * We always use SPI_WRITE mode (transfer starts with TDBR write).
781 * SPI_READ mode (transfer starts with RDBR read) seems to have
782 * problems with setting up the output value in TDBR prior to the
783 * start of the transfer.
784 */
785 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD);
786
787 if (chip->pio_interrupt) {
788 /* SPI irq should have been disabled by now */
789
790 /* discard old RX data and clear RXS */
791 bfin_spi_dummy_read(drv_data);
792
793 /* start transfer */
794 if (drv_data->tx == NULL)
795 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
796 else {
797 int loop;
798 if (bits_per_word == 16) {
799 u16 *buf = (u16 *)drv_data->tx;
800 for (loop = 0; loop < bits_per_word / 16;
801 loop++) {
802 bfin_write(&drv_data->regs->tdbr, *buf++);
803 }
804 } else if (bits_per_word == 8) {
805 u8 *buf = (u8 *)drv_data->tx;
806 for (loop = 0; loop < bits_per_word / 8; loop++)
807 bfin_write(&drv_data->regs->tdbr, *buf++);
808 }
809
810 drv_data->tx += drv_data->n_bytes;
811 }
812
813 /* once TDBR is empty, interrupt is triggered */
814 enable_irq(drv_data->spi_irq);
815 return;
816 }
817
818 /* IO mode */
819 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
820
821 if (full_duplex) {
822 /* full duplex mode */
823 BUG_ON((drv_data->tx_end - drv_data->tx) !=
824 (drv_data->rx_end - drv_data->rx));
825 dev_dbg(&drv_data->pdev->dev,
826 "IO duplex: cr is 0x%x\n", cr);
827
828 drv_data->ops->duplex(drv_data);
829
830 if (drv_data->tx != drv_data->tx_end)
831 tranf_success = 0;
832 } else if (drv_data->tx != NULL) {
833 /* write only half duplex */
834 dev_dbg(&drv_data->pdev->dev,
835 "IO write: cr is 0x%x\n", cr);
836
837 drv_data->ops->write(drv_data);
838
839 if (drv_data->tx != drv_data->tx_end)
840 tranf_success = 0;
841 } else if (drv_data->rx != NULL) {
842 /* read only half duplex */
843 dev_dbg(&drv_data->pdev->dev,
844 "IO read: cr is 0x%x\n", cr);
845
846 drv_data->ops->read(drv_data);
847 if (drv_data->rx != drv_data->rx_end)
848 tranf_success = 0;
849 }
850
851 if (!tranf_success) {
852 dev_dbg(&drv_data->pdev->dev,
853 "IO write error!\n");
854 message->state = ERROR_STATE;
855 } else {
856 /* Update total byte transferred */
857 message->actual_length += drv_data->len_in_bytes;
858 /* Move to next transfer of this msg */
859 message->state = bfin_spi_next_transfer(drv_data);
860 if (drv_data->cs_change && message->state != DONE_STATE) {
861 bfin_spi_flush(drv_data);
862 bfin_spi_cs_deactive(drv_data, chip);
863 }
864 }
865
866 /* Schedule next transfer tasklet */
867 tasklet_schedule(&drv_data->pump_transfers);
868}
869
870/* pop a msg from queue and kick off real transfer */
871static void bfin_spi_pump_messages(struct work_struct *work)
872{
873 struct bfin_spi_master_data *drv_data;
874 unsigned long flags;
875
876 drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
877
878 /* Lock queue and check for queue work */
879 spin_lock_irqsave(&drv_data->lock, flags);
880 if (list_empty(&drv_data->queue) || !drv_data->running) {
881 /* pumper kicked off but no work to do */
882 drv_data->busy = 0;
883 spin_unlock_irqrestore(&drv_data->lock, flags);
884 return;
885 }
886
887 /* Make sure we are not already running a message */
888 if (drv_data->cur_msg) {
889 spin_unlock_irqrestore(&drv_data->lock, flags);
890 return;
891 }
892
893 /* Extract head of queue */
894 drv_data->cur_msg = list_entry(drv_data->queue.next,
895 struct spi_message, queue);
896
897 /* Setup the SSP using the per chip configuration */
898 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
899 bfin_spi_restore_state(drv_data);
900
901 list_del_init(&drv_data->cur_msg->queue);
902
903 /* Initial message state */
904 drv_data->cur_msg->state = START_STATE;
905 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
906 struct spi_transfer, transfer_list);
907
908 dev_dbg(&drv_data->pdev->dev,
909 "got a message to pump, state is set to: baud "
910 "%d, flag 0x%x, ctl 0x%x\n",
911 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
912 drv_data->cur_chip->ctl_reg);
913
914 dev_dbg(&drv_data->pdev->dev,
915 "the first transfer len is %d\n",
916 drv_data->cur_transfer->len);
917
918 /* Mark as busy and launch transfers */
919 tasklet_schedule(&drv_data->pump_transfers);
920
921 drv_data->busy = 1;
922 spin_unlock_irqrestore(&drv_data->lock, flags);
923}
924
925/*
926 * got a msg to transfer, queue it in drv_data->queue.
927 * And kick off message pumper
928 */
929static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
930{
931 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
932 unsigned long flags;
933
934 spin_lock_irqsave(&drv_data->lock, flags);
935
936 if (!drv_data->running) {
937 spin_unlock_irqrestore(&drv_data->lock, flags);
938 return -ESHUTDOWN;
939 }
940
941 msg->actual_length = 0;
942 msg->status = -EINPROGRESS;
943 msg->state = START_STATE;
944
945 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
946 list_add_tail(&msg->queue, &drv_data->queue);
947
948 if (drv_data->running && !drv_data->busy)
949 queue_work(drv_data->workqueue, &drv_data->pump_messages);
950
951 spin_unlock_irqrestore(&drv_data->lock, flags);
952
953 return 0;
954}
955
956#define MAX_SPI_SSEL 7
957
958static const u16 ssel[][MAX_SPI_SSEL] = {
959 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
960 P_SPI0_SSEL4, P_SPI0_SSEL5,
961 P_SPI0_SSEL6, P_SPI0_SSEL7},
962
963 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
964 P_SPI1_SSEL4, P_SPI1_SSEL5,
965 P_SPI1_SSEL6, P_SPI1_SSEL7},
966
967 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
968 P_SPI2_SSEL4, P_SPI2_SSEL5,
969 P_SPI2_SSEL6, P_SPI2_SSEL7},
970};
971
972/* setup for devices (may be called multiple times -- not just first setup) */
973static int bfin_spi_setup(struct spi_device *spi)
974{
975 struct bfin5xx_spi_chip *chip_info;
976 struct bfin_spi_slave_data *chip = NULL;
977 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
978 u16 bfin_ctl_reg;
979 int ret = -EINVAL;
980
981 /* Only alloc (or use chip_info) on first setup */
982 chip_info = NULL;
983 chip = spi_get_ctldata(spi);
984 if (chip == NULL) {
985 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
986 if (!chip) {
987 dev_err(&spi->dev, "cannot allocate chip data\n");
988 ret = -ENOMEM;
989 goto error;
990 }
991
992 chip->enable_dma = 0;
993 chip_info = spi->controller_data;
994 }
995
996 /* Let people set non-standard bits directly */
997 bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
998 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
999
1000 /* chip_info isn't always needed */
1001 if (chip_info) {
1002 /* Make sure people stop trying to set fields via ctl_reg
1003 * when they should actually be using common SPI framework.
1004 * Currently we let through: WOM EMISO PSSE GM SZ.
1005 * Not sure if a user actually needs/uses any of these,
1006 * but let's assume (for now) they do.
1007 */
1008 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1009 dev_err(&spi->dev,
1010 "do not set bits in ctl_reg that the SPI framework manages\n");
1011 goto error;
1012 }
1013 chip->enable_dma = chip_info->enable_dma != 0
1014 && drv_data->master_info->enable_dma;
1015 chip->ctl_reg = chip_info->ctl_reg;
1016 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1017 chip->idle_tx_val = chip_info->idle_tx_val;
1018 chip->pio_interrupt = chip_info->pio_interrupt;
1019 } else {
1020 /* force a default base state */
1021 chip->ctl_reg &= bfin_ctl_reg;
1022 }
1023
1024 /* translate common spi framework into our register */
1025 if (spi->mode & SPI_CPOL)
1026 chip->ctl_reg |= BIT_CTL_CPOL;
1027 if (spi->mode & SPI_CPHA)
1028 chip->ctl_reg |= BIT_CTL_CPHA;
1029 if (spi->mode & SPI_LSB_FIRST)
1030 chip->ctl_reg |= BIT_CTL_LSBF;
1031 /* we dont support running in slave mode (yet?) */
1032 chip->ctl_reg |= BIT_CTL_MASTER;
1033
1034 /*
1035 * Notice: for blackfin, the speed_hz is the value of register
1036 * SPI_BAUD, not the real baudrate
1037 */
1038 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1039 chip->chip_select_num = spi->chip_select;
1040 if (chip->chip_select_num < MAX_CTRL_CS) {
1041 if (!(spi->mode & SPI_CPHA))
1042 dev_warn(&spi->dev,
1043 "Warning: SPI CPHA not set: Slave Select not under software control!\n"
1044 "See Documentation/blackfin/bfin-spi-notes.txt\n");
1045
1046 chip->flag = (1 << spi->chip_select) << 8;
1047 } else
1048 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1049
1050 if (chip->enable_dma && chip->pio_interrupt) {
1051 dev_err(&spi->dev,
1052 "enable_dma is set, do not set pio_interrupt\n");
1053 goto error;
1054 }
1055 /*
1056 * if any one SPI chip is registered and wants DMA, request the
1057 * DMA channel for it
1058 */
1059 if (chip->enable_dma && !drv_data->dma_requested) {
1060 /* register dma irq handler */
1061 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1062 if (ret) {
1063 dev_err(&spi->dev,
1064 "Unable to request BlackFin SPI DMA channel\n");
1065 goto error;
1066 }
1067 drv_data->dma_requested = 1;
1068
1069 ret = set_dma_callback(drv_data->dma_channel,
1070 bfin_spi_dma_irq_handler, drv_data);
1071 if (ret) {
1072 dev_err(&spi->dev, "Unable to set dma callback\n");
1073 goto error;
1074 }
1075 dma_disable_irq(drv_data->dma_channel);
1076 }
1077
1078 if (chip->pio_interrupt && !drv_data->irq_requested) {
1079 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1080 0, "BFIN_SPI", drv_data);
1081 if (ret) {
1082 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1083 goto error;
1084 }
1085 drv_data->irq_requested = 1;
1086 /* we use write mode, spi irq has to be disabled here */
1087 disable_irq(drv_data->spi_irq);
1088 }
1089
1090 if (chip->chip_select_num >= MAX_CTRL_CS) {
1091 /* Only request on first setup */
1092 if (spi_get_ctldata(spi) == NULL) {
1093 ret = gpio_request(chip->cs_gpio, spi->modalias);
1094 if (ret) {
1095 dev_err(&spi->dev, "gpio_request() error\n");
1096 goto pin_error;
1097 }
1098 gpio_direction_output(chip->cs_gpio, 1);
1099 }
1100 }
1101
1102 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1103 spi->modalias, spi->bits_per_word, chip->enable_dma);
1104 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1105 chip->ctl_reg, chip->flag);
1106
1107 spi_set_ctldata(spi, chip);
1108
1109 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1110 if (chip->chip_select_num < MAX_CTRL_CS) {
1111 ret = peripheral_request(ssel[spi->master->bus_num]
1112 [chip->chip_select_num-1], spi->modalias);
1113 if (ret) {
1114 dev_err(&spi->dev, "peripheral_request() error\n");
1115 goto pin_error;
1116 }
1117 }
1118
1119 bfin_spi_cs_enable(drv_data, chip);
1120 bfin_spi_cs_deactive(drv_data, chip);
1121
1122 return 0;
1123
1124 pin_error:
1125 if (chip->chip_select_num >= MAX_CTRL_CS)
1126 gpio_free(chip->cs_gpio);
1127 else
1128 peripheral_free(ssel[spi->master->bus_num]
1129 [chip->chip_select_num - 1]);
1130 error:
1131 if (chip) {
1132 if (drv_data->dma_requested)
1133 free_dma(drv_data->dma_channel);
1134 drv_data->dma_requested = 0;
1135
1136 kfree(chip);
1137 /* prevent free 'chip' twice */
1138 spi_set_ctldata(spi, NULL);
1139 }
1140
1141 return ret;
1142}
1143
1144/*
1145 * callback for spi framework.
1146 * clean driver specific data
1147 */
1148static void bfin_spi_cleanup(struct spi_device *spi)
1149{
1150 struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
1151 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1152
1153 if (!chip)
1154 return;
1155
1156 if (chip->chip_select_num < MAX_CTRL_CS) {
1157 peripheral_free(ssel[spi->master->bus_num]
1158 [chip->chip_select_num-1]);
1159 bfin_spi_cs_disable(drv_data, chip);
1160 } else
1161 gpio_free(chip->cs_gpio);
1162
1163 kfree(chip);
1164 /* prevent free 'chip' twice */
1165 spi_set_ctldata(spi, NULL);
1166}
1167
1168static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
1169{
1170 INIT_LIST_HEAD(&drv_data->queue);
1171 spin_lock_init(&drv_data->lock);
1172
1173 drv_data->running = false;
1174 drv_data->busy = 0;
1175
1176 /* init transfer tasklet */
1177 tasklet_init(&drv_data->pump_transfers,
1178 bfin_spi_pump_transfers, (unsigned long)drv_data);
1179
1180 /* init messages workqueue */
1181 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1182 drv_data->workqueue = create_singlethread_workqueue(
1183 dev_name(drv_data->master->dev.parent));
1184 if (drv_data->workqueue == NULL)
1185 return -EBUSY;
1186
1187 return 0;
1188}
1189
1190static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
1191{
1192 unsigned long flags;
1193
1194 spin_lock_irqsave(&drv_data->lock, flags);
1195
1196 if (drv_data->running || drv_data->busy) {
1197 spin_unlock_irqrestore(&drv_data->lock, flags);
1198 return -EBUSY;
1199 }
1200
1201 drv_data->running = true;
1202 drv_data->cur_msg = NULL;
1203 drv_data->cur_transfer = NULL;
1204 drv_data->cur_chip = NULL;
1205 spin_unlock_irqrestore(&drv_data->lock, flags);
1206
1207 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1208
1209 return 0;
1210}
1211
1212static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
1213{
1214 unsigned long flags;
1215 unsigned limit = 500;
1216 int status = 0;
1217
1218 spin_lock_irqsave(&drv_data->lock, flags);
1219
1220 /*
1221 * This is a bit lame, but is optimized for the common execution path.
1222 * A wait_queue on the drv_data->busy could be used, but then the common
1223 * execution path (pump_messages) would be required to call wake_up or
1224 * friends on every SPI message. Do this instead
1225 */
1226 drv_data->running = false;
1227 while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
1228 spin_unlock_irqrestore(&drv_data->lock, flags);
1229 msleep(10);
1230 spin_lock_irqsave(&drv_data->lock, flags);
1231 }
1232
1233 if (!list_empty(&drv_data->queue) || drv_data->busy)
1234 status = -EBUSY;
1235
1236 spin_unlock_irqrestore(&drv_data->lock, flags);
1237
1238 return status;
1239}
1240
1241static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
1242{
1243 int status;
1244
1245 status = bfin_spi_stop_queue(drv_data);
1246 if (status != 0)
1247 return status;
1248
1249 destroy_workqueue(drv_data->workqueue);
1250
1251 return 0;
1252}
1253
1254static int bfin_spi_probe(struct platform_device *pdev)
1255{
1256 struct device *dev = &pdev->dev;
1257 struct bfin5xx_spi_master *platform_info;
1258 struct spi_master *master;
1259 struct bfin_spi_master_data *drv_data;
1260 struct resource *res;
1261 int status = 0;
1262
1263 platform_info = dev_get_platdata(dev);
1264
1265 /* Allocate master with space for drv_data */
1266 master = spi_alloc_master(dev, sizeof(*drv_data));
1267 if (!master) {
1268 dev_err(&pdev->dev, "can not alloc spi_master\n");
1269 return -ENOMEM;
1270 }
1271
1272 drv_data = spi_master_get_devdata(master);
1273 drv_data->master = master;
1274 drv_data->master_info = platform_info;
1275 drv_data->pdev = pdev;
1276 drv_data->pin_req = platform_info->pin_req;
1277
1278 /* the spi->mode bits supported by this driver: */
1279 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1280 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1281 master->bus_num = pdev->id;
1282 master->num_chipselect = platform_info->num_chipselect;
1283 master->cleanup = bfin_spi_cleanup;
1284 master->setup = bfin_spi_setup;
1285 master->transfer = bfin_spi_transfer;
1286
1287 /* Find and map our resources */
1288 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1289 if (res == NULL) {
1290 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1291 status = -ENOENT;
1292 goto out_error_get_res;
1293 }
1294
1295 drv_data->regs = ioremap(res->start, resource_size(res));
1296 if (drv_data->regs == NULL) {
1297 dev_err(dev, "Cannot map IO\n");
1298 status = -ENXIO;
1299 goto out_error_ioremap;
1300 }
1301
1302 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1303 if (res == NULL) {
1304 dev_err(dev, "No DMA channel specified\n");
1305 status = -ENOENT;
1306 goto out_error_free_io;
1307 }
1308 drv_data->dma_channel = res->start;
1309
1310 drv_data->spi_irq = platform_get_irq(pdev, 0);
1311 if (drv_data->spi_irq < 0) {
1312 dev_err(dev, "No spi pio irq specified\n");
1313 status = -ENOENT;
1314 goto out_error_free_io;
1315 }
1316
1317 /* Initial and start queue */
1318 status = bfin_spi_init_queue(drv_data);
1319 if (status != 0) {
1320 dev_err(dev, "problem initializing queue\n");
1321 goto out_error_queue_alloc;
1322 }
1323
1324 status = bfin_spi_start_queue(drv_data);
1325 if (status != 0) {
1326 dev_err(dev, "problem starting queue\n");
1327 goto out_error_queue_alloc;
1328 }
1329
1330 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1331 if (status != 0) {
1332 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1333 goto out_error_queue_alloc;
1334 }
1335
1336 /* Reset SPI registers. If these registers were used by the boot loader,
1337 * the sky may fall on your head if you enable the dma controller.
1338 */
1339 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1340 bfin_write(&drv_data->regs->flg, 0xFF00);
1341
1342 /* Register with the SPI framework */
1343 platform_set_drvdata(pdev, drv_data);
1344 status = spi_register_master(master);
1345 if (status != 0) {
1346 dev_err(dev, "problem registering spi master\n");
1347 goto out_error_queue_alloc;
1348 }
1349
1350 dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n",
1351 DRV_DESC, DRV_VERSION, drv_data->regs,
1352 drv_data->dma_channel);
1353 return status;
1354
1355out_error_queue_alloc:
1356 bfin_spi_destroy_queue(drv_data);
1357out_error_free_io:
1358 iounmap(drv_data->regs);
1359out_error_ioremap:
1360out_error_get_res:
1361 spi_master_put(master);
1362
1363 return status;
1364}
1365
1366/* stop hardware and remove the driver */
1367static int bfin_spi_remove(struct platform_device *pdev)
1368{
1369 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1370 int status = 0;
1371
1372 if (!drv_data)
1373 return 0;
1374
1375 /* Remove the queue */
1376 status = bfin_spi_destroy_queue(drv_data);
1377 if (status != 0)
1378 return status;
1379
1380 /* Disable the SSP at the peripheral and SOC level */
1381 bfin_spi_disable(drv_data);
1382
1383 /* Release DMA */
1384 if (drv_data->master_info->enable_dma) {
1385 if (dma_channel_active(drv_data->dma_channel))
1386 free_dma(drv_data->dma_channel);
1387 }
1388
1389 if (drv_data->irq_requested) {
1390 free_irq(drv_data->spi_irq, drv_data);
1391 drv_data->irq_requested = 0;
1392 }
1393
1394 /* Disconnect from the SPI framework */
1395 spi_unregister_master(drv_data->master);
1396
1397 peripheral_free_list(drv_data->pin_req);
1398
1399 return 0;
1400}
1401
1402#ifdef CONFIG_PM_SLEEP
1403static int bfin_spi_suspend(struct device *dev)
1404{
1405 struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev);
1406 int status = 0;
1407
1408 status = bfin_spi_stop_queue(drv_data);
1409 if (status != 0)
1410 return status;
1411
1412 drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl);
1413 drv_data->flag_reg = bfin_read(&drv_data->regs->flg);
1414
1415 /*
1416 * reset SPI_CTL and SPI_FLG registers
1417 */
1418 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1419 bfin_write(&drv_data->regs->flg, 0xFF00);
1420
1421 return 0;
1422}
1423
1424static int bfin_spi_resume(struct device *dev)
1425{
1426 struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev);
1427 int status = 0;
1428
1429 bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg);
1430 bfin_write(&drv_data->regs->flg, drv_data->flag_reg);
1431
1432 /* Start the queue running */
1433 status = bfin_spi_start_queue(drv_data);
1434 if (status != 0) {
1435 dev_err(dev, "problem starting queue (%d)\n", status);
1436 return status;
1437 }
1438
1439 return 0;
1440}
1441
1442static SIMPLE_DEV_PM_OPS(bfin_spi_pm_ops, bfin_spi_suspend, bfin_spi_resume);
1443
1444#define BFIN_SPI_PM_OPS (&bfin_spi_pm_ops)
1445#else
1446#define BFIN_SPI_PM_OPS NULL
1447#endif
1448
1449MODULE_ALIAS("platform:bfin-spi");
1450static struct platform_driver bfin_spi_driver = {
1451 .driver = {
1452 .name = DRV_NAME,
1453 .pm = BFIN_SPI_PM_OPS,
1454 },
1455 .probe = bfin_spi_probe,
1456 .remove = bfin_spi_remove,
1457};
1458
1459static int __init bfin_spi_init(void)
1460{
1461 return platform_driver_register(&bfin_spi_driver);
1462}
1463subsys_initcall(bfin_spi_init);
1464
1465static void __exit bfin_spi_exit(void)
1466{
1467 platform_driver_unregister(&bfin_spi_driver);
1468}
1469module_exit(bfin_spi_exit);