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1/*
2 * Driver for NEC VR4100 series Real Time Clock unit.
3 *
4 * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/err.h>
21#include <linux/fs.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/interrupt.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/rtc.h>
29#include <linux/spinlock.h>
30#include <linux/types.h>
31#include <linux/uaccess.h>
32#include <linux/log2.h>
33
34#include <asm/div64.h>
35
36MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
37MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
38MODULE_LICENSE("GPL v2");
39
40/* RTC 1 registers */
41#define ETIMELREG 0x00
42#define ETIMEMREG 0x02
43#define ETIMEHREG 0x04
44/* RFU */
45#define ECMPLREG 0x08
46#define ECMPMREG 0x0a
47#define ECMPHREG 0x0c
48/* RFU */
49#define RTCL1LREG 0x10
50#define RTCL1HREG 0x12
51#define RTCL1CNTLREG 0x14
52#define RTCL1CNTHREG 0x16
53#define RTCL2LREG 0x18
54#define RTCL2HREG 0x1a
55#define RTCL2CNTLREG 0x1c
56#define RTCL2CNTHREG 0x1e
57
58/* RTC 2 registers */
59#define TCLKLREG 0x00
60#define TCLKHREG 0x02
61#define TCLKCNTLREG 0x04
62#define TCLKCNTHREG 0x06
63/* RFU */
64#define RTCINTREG 0x1e
65 #define TCLOCK_INT 0x08
66 #define RTCLONG2_INT 0x04
67 #define RTCLONG1_INT 0x02
68 #define ELAPSEDTIME_INT 0x01
69
70#define RTC_FREQUENCY 32768
71#define MAX_PERIODIC_RATE 6553
72
73static void __iomem *rtc1_base;
74static void __iomem *rtc2_base;
75
76#define rtc1_read(offset) readw(rtc1_base + (offset))
77#define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
78
79#define rtc2_read(offset) readw(rtc2_base + (offset))
80#define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
81
82static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
83
84static DEFINE_SPINLOCK(rtc_lock);
85static char rtc_name[] = "RTC";
86static unsigned long periodic_count;
87static unsigned int alarm_enabled;
88static int aie_irq;
89static int pie_irq;
90
91static inline unsigned long read_elapsed_second(void)
92{
93
94 unsigned long first_low, first_mid, first_high;
95
96 unsigned long second_low, second_mid, second_high;
97
98 do {
99 first_low = rtc1_read(ETIMELREG);
100 first_mid = rtc1_read(ETIMEMREG);
101 first_high = rtc1_read(ETIMEHREG);
102 second_low = rtc1_read(ETIMELREG);
103 second_mid = rtc1_read(ETIMEMREG);
104 second_high = rtc1_read(ETIMEHREG);
105 } while (first_low != second_low || first_mid != second_mid ||
106 first_high != second_high);
107
108 return (first_high << 17) | (first_mid << 1) | (first_low >> 15);
109}
110
111static inline void write_elapsed_second(unsigned long sec)
112{
113 spin_lock_irq(&rtc_lock);
114
115 rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
116 rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
117 rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
118
119 spin_unlock_irq(&rtc_lock);
120}
121
122static void vr41xx_rtc_release(struct device *dev)
123{
124
125 spin_lock_irq(&rtc_lock);
126
127 rtc1_write(ECMPLREG, 0);
128 rtc1_write(ECMPMREG, 0);
129 rtc1_write(ECMPHREG, 0);
130 rtc1_write(RTCL1LREG, 0);
131 rtc1_write(RTCL1HREG, 0);
132
133 spin_unlock_irq(&rtc_lock);
134
135 disable_irq(aie_irq);
136 disable_irq(pie_irq);
137}
138
139static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
140{
141 unsigned long epoch_sec, elapsed_sec;
142
143 epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
144 elapsed_sec = read_elapsed_second();
145
146 rtc_time_to_tm(epoch_sec + elapsed_sec, time);
147
148 return 0;
149}
150
151static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
152{
153 unsigned long epoch_sec, current_sec;
154
155 epoch_sec = mktime(epoch, 1, 1, 0, 0, 0);
156 current_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
157 time->tm_hour, time->tm_min, time->tm_sec);
158
159 write_elapsed_second(current_sec - epoch_sec);
160
161 return 0;
162}
163
164static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
165{
166 unsigned long low, mid, high;
167 struct rtc_time *time = &wkalrm->time;
168
169 spin_lock_irq(&rtc_lock);
170
171 low = rtc1_read(ECMPLREG);
172 mid = rtc1_read(ECMPMREG);
173 high = rtc1_read(ECMPHREG);
174 wkalrm->enabled = alarm_enabled;
175
176 spin_unlock_irq(&rtc_lock);
177
178 rtc_time_to_tm((high << 17) | (mid << 1) | (low >> 15), time);
179
180 return 0;
181}
182
183static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
184{
185 unsigned long alarm_sec;
186 struct rtc_time *time = &wkalrm->time;
187
188 alarm_sec = mktime(time->tm_year + 1900, time->tm_mon + 1, time->tm_mday,
189 time->tm_hour, time->tm_min, time->tm_sec);
190
191 spin_lock_irq(&rtc_lock);
192
193 if (alarm_enabled)
194 disable_irq(aie_irq);
195
196 rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
197 rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
198 rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
199
200 if (wkalrm->enabled)
201 enable_irq(aie_irq);
202
203 alarm_enabled = wkalrm->enabled;
204
205 spin_unlock_irq(&rtc_lock);
206
207 return 0;
208}
209
210static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
211{
212 switch (cmd) {
213 case RTC_EPOCH_READ:
214 return put_user(epoch, (unsigned long __user *)arg);
215 case RTC_EPOCH_SET:
216 /* Doesn't support before 1900 */
217 if (arg < 1900)
218 return -EINVAL;
219 epoch = arg;
220 break;
221 default:
222 return -ENOIOCTLCMD;
223 }
224
225 return 0;
226}
227
228static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
229{
230 spin_lock_irq(&rtc_lock);
231 if (enabled) {
232 if (!alarm_enabled) {
233 enable_irq(aie_irq);
234 alarm_enabled = 1;
235 }
236 } else {
237 if (alarm_enabled) {
238 disable_irq(aie_irq);
239 alarm_enabled = 0;
240 }
241 }
242 spin_unlock_irq(&rtc_lock);
243 return 0;
244}
245
246static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
247{
248 struct platform_device *pdev = (struct platform_device *)dev_id;
249 struct rtc_device *rtc = platform_get_drvdata(pdev);
250
251 rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
252
253 rtc_update_irq(rtc, 1, RTC_AF);
254
255 return IRQ_HANDLED;
256}
257
258static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
259{
260 struct platform_device *pdev = (struct platform_device *)dev_id;
261 struct rtc_device *rtc = platform_get_drvdata(pdev);
262 unsigned long count = periodic_count;
263
264 rtc2_write(RTCINTREG, RTCLONG1_INT);
265
266 rtc1_write(RTCL1LREG, count);
267 rtc1_write(RTCL1HREG, count >> 16);
268
269 rtc_update_irq(rtc, 1, RTC_PF);
270
271 return IRQ_HANDLED;
272}
273
274static const struct rtc_class_ops vr41xx_rtc_ops = {
275 .release = vr41xx_rtc_release,
276 .ioctl = vr41xx_rtc_ioctl,
277 .read_time = vr41xx_rtc_read_time,
278 .set_time = vr41xx_rtc_set_time,
279 .read_alarm = vr41xx_rtc_read_alarm,
280 .set_alarm = vr41xx_rtc_set_alarm,
281 .alarm_irq_enable = vr41xx_rtc_alarm_irq_enable,
282};
283
284static int rtc_probe(struct platform_device *pdev)
285{
286 struct resource *res;
287 struct rtc_device *rtc;
288 int retval;
289
290 if (pdev->num_resources != 4)
291 return -EBUSY;
292
293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
294 if (!res)
295 return -EBUSY;
296
297 rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
298 if (!rtc1_base)
299 return -EBUSY;
300
301 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
302 if (!res) {
303 retval = -EBUSY;
304 goto err_rtc1_iounmap;
305 }
306
307 rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
308 if (!rtc2_base) {
309 retval = -EBUSY;
310 goto err_rtc1_iounmap;
311 }
312
313 rtc = devm_rtc_device_register(&pdev->dev, rtc_name, &vr41xx_rtc_ops,
314 THIS_MODULE);
315 if (IS_ERR(rtc)) {
316 retval = PTR_ERR(rtc);
317 goto err_iounmap_all;
318 }
319
320 rtc->max_user_freq = MAX_PERIODIC_RATE;
321
322 spin_lock_irq(&rtc_lock);
323
324 rtc1_write(ECMPLREG, 0);
325 rtc1_write(ECMPMREG, 0);
326 rtc1_write(ECMPHREG, 0);
327 rtc1_write(RTCL1LREG, 0);
328 rtc1_write(RTCL1HREG, 0);
329
330 spin_unlock_irq(&rtc_lock);
331
332 aie_irq = platform_get_irq(pdev, 0);
333 if (aie_irq <= 0) {
334 retval = -EBUSY;
335 goto err_iounmap_all;
336 }
337
338 retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
339 "elapsed_time", pdev);
340 if (retval < 0)
341 goto err_iounmap_all;
342
343 pie_irq = platform_get_irq(pdev, 1);
344 if (pie_irq <= 0) {
345 retval = -EBUSY;
346 goto err_iounmap_all;
347 }
348
349 retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
350 "rtclong1", pdev);
351 if (retval < 0)
352 goto err_iounmap_all;
353
354 platform_set_drvdata(pdev, rtc);
355
356 disable_irq(aie_irq);
357 disable_irq(pie_irq);
358
359 dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");
360
361 return 0;
362
363err_iounmap_all:
364 rtc2_base = NULL;
365
366err_rtc1_iounmap:
367 rtc1_base = NULL;
368
369 return retval;
370}
371
372/* work with hotplug and coldplug */
373MODULE_ALIAS("platform:RTC");
374
375static struct platform_driver rtc_platform_driver = {
376 .probe = rtc_probe,
377 .driver = {
378 .name = rtc_name,
379 },
380};
381
382module_platform_driver(rtc_platform_driver);