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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI detection and setup code
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/msi.h>
11#include <linux/of_device.h>
12#include <linux/of_pci.h>
13#include <linux/pci_hotplug.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/cpumask.h>
17#include <linux/aer.h>
18#include <linux/acpi.h>
19#include <linux/hypervisor.h>
20#include <linux/irqdomain.h>
21#include <linux/pm_runtime.h>
22#include <linux/bitfield.h>
23#include "pci.h"
24
25#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
26#define CARDBUS_RESERVE_BUSNR 3
27
28static struct resource busn_resource = {
29 .name = "PCI busn",
30 .start = 0,
31 .end = 255,
32 .flags = IORESOURCE_BUS,
33};
34
35/* Ugh. Need to stop exporting this to modules. */
36LIST_HEAD(pci_root_buses);
37EXPORT_SYMBOL(pci_root_buses);
38
39static LIST_HEAD(pci_domain_busn_res_list);
40
41struct pci_domain_busn_res {
42 struct list_head list;
43 struct resource res;
44 int domain_nr;
45};
46
47static struct resource *get_pci_domain_busn_res(int domain_nr)
48{
49 struct pci_domain_busn_res *r;
50
51 list_for_each_entry(r, &pci_domain_busn_res_list, list)
52 if (r->domain_nr == domain_nr)
53 return &r->res;
54
55 r = kzalloc(sizeof(*r), GFP_KERNEL);
56 if (!r)
57 return NULL;
58
59 r->domain_nr = domain_nr;
60 r->res.start = 0;
61 r->res.end = 0xff;
62 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
63
64 list_add_tail(&r->list, &pci_domain_busn_res_list);
65
66 return &r->res;
67}
68
69/*
70 * Some device drivers need know if PCI is initiated.
71 * Basically, we think PCI is not initiated when there
72 * is no device to be found on the pci_bus_type.
73 */
74int no_pci_devices(void)
75{
76 struct device *dev;
77 int no_devices;
78
79 dev = bus_find_next_device(&pci_bus_type, NULL);
80 no_devices = (dev == NULL);
81 put_device(dev);
82 return no_devices;
83}
84EXPORT_SYMBOL(no_pci_devices);
85
86/*
87 * PCI Bus Class
88 */
89static void release_pcibus_dev(struct device *dev)
90{
91 struct pci_bus *pci_bus = to_pci_bus(dev);
92
93 put_device(pci_bus->bridge);
94 pci_bus_remove_resources(pci_bus);
95 pci_release_bus_of_node(pci_bus);
96 kfree(pci_bus);
97}
98
99static struct class pcibus_class = {
100 .name = "pci_bus",
101 .dev_release = &release_pcibus_dev,
102 .dev_groups = pcibus_groups,
103};
104
105static int __init pcibus_class_init(void)
106{
107 return class_register(&pcibus_class);
108}
109postcore_initcall(pcibus_class_init);
110
111static u64 pci_size(u64 base, u64 maxbase, u64 mask)
112{
113 u64 size = mask & maxbase; /* Find the significant bits */
114 if (!size)
115 return 0;
116
117 /*
118 * Get the lowest of them to find the decode size, and from that
119 * the extent.
120 */
121 size = size & ~(size-1);
122
123 /*
124 * base == maxbase can be valid only if the BAR has already been
125 * programmed with all 1s.
126 */
127 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
128 return 0;
129
130 return size;
131}
132
133static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
134{
135 u32 mem_type;
136 unsigned long flags;
137
138 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
139 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
140 flags |= IORESOURCE_IO;
141 return flags;
142 }
143
144 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
145 flags |= IORESOURCE_MEM;
146 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
147 flags |= IORESOURCE_PREFETCH;
148
149 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
150 switch (mem_type) {
151 case PCI_BASE_ADDRESS_MEM_TYPE_32:
152 break;
153 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
154 /* 1M mem BAR treated as 32-bit BAR */
155 break;
156 case PCI_BASE_ADDRESS_MEM_TYPE_64:
157 flags |= IORESOURCE_MEM_64;
158 break;
159 default:
160 /* mem unknown type treated as 32-bit BAR */
161 break;
162 }
163 return flags;
164}
165
166#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
167
168/**
169 * __pci_read_base - Read a PCI BAR
170 * @dev: the PCI device
171 * @type: type of the BAR
172 * @res: resource buffer to be filled in
173 * @pos: BAR position in the config space
174 *
175 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
176 */
177int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
178 struct resource *res, unsigned int pos)
179{
180 u32 l = 0, sz = 0, mask;
181 u64 l64, sz64, mask64;
182 u16 orig_cmd;
183 struct pci_bus_region region, inverted_region;
184
185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
186
187 /* No printks while decoding is disabled! */
188 if (!dev->mmio_always_on) {
189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
191 pci_write_config_word(dev, PCI_COMMAND,
192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
193 }
194 }
195
196 res->name = pci_name(dev);
197
198 pci_read_config_dword(dev, pos, &l);
199 pci_write_config_dword(dev, pos, l | mask);
200 pci_read_config_dword(dev, pos, &sz);
201 pci_write_config_dword(dev, pos, l);
202
203 /*
204 * All bits set in sz means the device isn't working properly.
205 * If the BAR isn't implemented, all bits must be 0. If it's a
206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 * 1 must be clear.
208 */
209 if (PCI_POSSIBLE_ERROR(sz))
210 sz = 0;
211
212 /*
213 * I don't know how l can have all bits set. Copied from old code.
214 * Maybe it fixes a bug on some ancient platform.
215 */
216 if (PCI_POSSIBLE_ERROR(l))
217 l = 0;
218
219 if (type == pci_bar_unknown) {
220 res->flags = decode_bar(dev, l);
221 res->flags |= IORESOURCE_SIZEALIGN;
222 if (res->flags & IORESOURCE_IO) {
223 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
226 } else {
227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 }
231 } else {
232 if (l & PCI_ROM_ADDRESS_ENABLE)
233 res->flags |= IORESOURCE_ROM_ENABLE;
234 l64 = l & PCI_ROM_ADDRESS_MASK;
235 sz64 = sz & PCI_ROM_ADDRESS_MASK;
236 mask64 = PCI_ROM_ADDRESS_MASK;
237 }
238
239 if (res->flags & IORESOURCE_MEM_64) {
240 pci_read_config_dword(dev, pos + 4, &l);
241 pci_write_config_dword(dev, pos + 4, ~0);
242 pci_read_config_dword(dev, pos + 4, &sz);
243 pci_write_config_dword(dev, pos + 4, l);
244
245 l64 |= ((u64)l << 32);
246 sz64 |= ((u64)sz << 32);
247 mask64 |= ((u64)~0 << 32);
248 }
249
250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
252
253 if (!sz64)
254 goto fail;
255
256 sz64 = pci_size(l64, sz64, mask64);
257 if (!sz64) {
258 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
259 pos);
260 goto fail;
261 }
262
263 if (res->flags & IORESOURCE_MEM_64) {
264 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
265 && sz64 > 0x100000000ULL) {
266 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
267 res->start = 0;
268 res->end = 0;
269 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
270 pos, (unsigned long long)sz64);
271 goto out;
272 }
273
274 if ((sizeof(pci_bus_addr_t) < 8) && l) {
275 /* Above 32-bit boundary; try to reallocate */
276 res->flags |= IORESOURCE_UNSET;
277 res->start = 0;
278 res->end = sz64 - 1;
279 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
280 pos, (unsigned long long)l64);
281 goto out;
282 }
283 }
284
285 region.start = l64;
286 region.end = l64 + sz64 - 1;
287
288 pcibios_bus_to_resource(dev->bus, res, ®ion);
289 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
290
291 /*
292 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
293 * the corresponding resource address (the physical address used by
294 * the CPU. Converting that resource address back to a bus address
295 * should yield the original BAR value:
296 *
297 * resource_to_bus(bus_to_resource(A)) == A
298 *
299 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
300 * be claimed by the device.
301 */
302 if (inverted_region.start != region.start) {
303 res->flags |= IORESOURCE_UNSET;
304 res->start = 0;
305 res->end = region.end - region.start;
306 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
307 pos, (unsigned long long)region.start);
308 }
309
310 goto out;
311
312
313fail:
314 res->flags = 0;
315out:
316 if (res->flags)
317 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
318
319 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
320}
321
322static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
323{
324 unsigned int pos, reg;
325
326 if (dev->non_compliant_bars)
327 return;
328
329 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
330 if (dev->is_virtfn)
331 return;
332
333 for (pos = 0; pos < howmany; pos++) {
334 struct resource *res = &dev->resource[pos];
335 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
336 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
337 }
338
339 if (rom) {
340 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
341 dev->rom_base_reg = rom;
342 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
343 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
344 __pci_read_base(dev, pci_bar_mem32, res, rom);
345 }
346}
347
348static void pci_read_bridge_windows(struct pci_dev *bridge)
349{
350 u16 io;
351 u32 pmem, tmp;
352
353 pci_read_config_word(bridge, PCI_IO_BASE, &io);
354 if (!io) {
355 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
356 pci_read_config_word(bridge, PCI_IO_BASE, &io);
357 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
358 }
359 if (io)
360 bridge->io_window = 1;
361
362 /*
363 * DECchip 21050 pass 2 errata: the bridge may miss an address
364 * disconnect boundary by one PCI data phase. Workaround: do not
365 * use prefetching on this device.
366 */
367 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
368 return;
369
370 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
371 if (!pmem) {
372 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
373 0xffe0fff0);
374 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
375 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
376 }
377 if (!pmem)
378 return;
379
380 bridge->pref_window = 1;
381
382 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
383
384 /*
385 * Bridge claims to have a 64-bit prefetchable memory
386 * window; verify that the upper bits are actually
387 * writable.
388 */
389 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
390 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
391 0xffffffff);
392 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
393 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
394 if (tmp)
395 bridge->pref_64_window = 1;
396 }
397}
398
399static void pci_read_bridge_io(struct pci_bus *child)
400{
401 struct pci_dev *dev = child->self;
402 u8 io_base_lo, io_limit_lo;
403 unsigned long io_mask, io_granularity, base, limit;
404 struct pci_bus_region region;
405 struct resource *res;
406
407 io_mask = PCI_IO_RANGE_MASK;
408 io_granularity = 0x1000;
409 if (dev->io_window_1k) {
410 /* Support 1K I/O space granularity */
411 io_mask = PCI_IO_1K_RANGE_MASK;
412 io_granularity = 0x400;
413 }
414
415 res = child->resource[0];
416 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
417 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
418 base = (io_base_lo & io_mask) << 8;
419 limit = (io_limit_lo & io_mask) << 8;
420
421 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
422 u16 io_base_hi, io_limit_hi;
423
424 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
425 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
426 base |= ((unsigned long) io_base_hi << 16);
427 limit |= ((unsigned long) io_limit_hi << 16);
428 }
429
430 if (base <= limit) {
431 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
432 region.start = base;
433 region.end = limit + io_granularity - 1;
434 pcibios_bus_to_resource(dev->bus, res, ®ion);
435 pci_info(dev, " bridge window %pR\n", res);
436 }
437}
438
439static void pci_read_bridge_mmio(struct pci_bus *child)
440{
441 struct pci_dev *dev = child->self;
442 u16 mem_base_lo, mem_limit_lo;
443 unsigned long base, limit;
444 struct pci_bus_region region;
445 struct resource *res;
446
447 res = child->resource[1];
448 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
449 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
450 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
451 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
452 if (base <= limit) {
453 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
454 region.start = base;
455 region.end = limit + 0xfffff;
456 pcibios_bus_to_resource(dev->bus, res, ®ion);
457 pci_info(dev, " bridge window %pR\n", res);
458 }
459}
460
461static void pci_read_bridge_mmio_pref(struct pci_bus *child)
462{
463 struct pci_dev *dev = child->self;
464 u16 mem_base_lo, mem_limit_lo;
465 u64 base64, limit64;
466 pci_bus_addr_t base, limit;
467 struct pci_bus_region region;
468 struct resource *res;
469
470 res = child->resource[2];
471 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
472 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
473 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
474 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
475
476 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
477 u32 mem_base_hi, mem_limit_hi;
478
479 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
480 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
481
482 /*
483 * Some bridges set the base > limit by default, and some
484 * (broken) BIOSes do not initialize them. If we find
485 * this, just assume they are not being used.
486 */
487 if (mem_base_hi <= mem_limit_hi) {
488 base64 |= (u64) mem_base_hi << 32;
489 limit64 |= (u64) mem_limit_hi << 32;
490 }
491 }
492
493 base = (pci_bus_addr_t) base64;
494 limit = (pci_bus_addr_t) limit64;
495
496 if (base != base64) {
497 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
498 (unsigned long long) base64);
499 return;
500 }
501
502 if (base <= limit) {
503 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
504 IORESOURCE_MEM | IORESOURCE_PREFETCH;
505 if (res->flags & PCI_PREF_RANGE_TYPE_64)
506 res->flags |= IORESOURCE_MEM_64;
507 region.start = base;
508 region.end = limit + 0xfffff;
509 pcibios_bus_to_resource(dev->bus, res, ®ion);
510 pci_info(dev, " bridge window %pR\n", res);
511 }
512}
513
514void pci_read_bridge_bases(struct pci_bus *child)
515{
516 struct pci_dev *dev = child->self;
517 struct resource *res;
518 int i;
519
520 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
521 return;
522
523 pci_info(dev, "PCI bridge to %pR%s\n",
524 &child->busn_res,
525 dev->transparent ? " (subtractive decode)" : "");
526
527 pci_bus_remove_resources(child);
528 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
529 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
530
531 pci_read_bridge_io(child);
532 pci_read_bridge_mmio(child);
533 pci_read_bridge_mmio_pref(child);
534
535 if (dev->transparent) {
536 pci_bus_for_each_resource(child->parent, res, i) {
537 if (res && res->flags) {
538 pci_bus_add_resource(child, res,
539 PCI_SUBTRACTIVE_DECODE);
540 pci_info(dev, " bridge window %pR (subtractive decode)\n",
541 res);
542 }
543 }
544 }
545}
546
547static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
548{
549 struct pci_bus *b;
550
551 b = kzalloc(sizeof(*b), GFP_KERNEL);
552 if (!b)
553 return NULL;
554
555 INIT_LIST_HEAD(&b->node);
556 INIT_LIST_HEAD(&b->children);
557 INIT_LIST_HEAD(&b->devices);
558 INIT_LIST_HEAD(&b->slots);
559 INIT_LIST_HEAD(&b->resources);
560 b->max_bus_speed = PCI_SPEED_UNKNOWN;
561 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
562#ifdef CONFIG_PCI_DOMAINS_GENERIC
563 if (parent)
564 b->domain_nr = parent->domain_nr;
565#endif
566 return b;
567}
568
569static void pci_release_host_bridge_dev(struct device *dev)
570{
571 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
572
573 if (bridge->release_fn)
574 bridge->release_fn(bridge);
575
576 pci_free_resource_list(&bridge->windows);
577 pci_free_resource_list(&bridge->dma_ranges);
578 kfree(bridge);
579}
580
581static void pci_init_host_bridge(struct pci_host_bridge *bridge)
582{
583 INIT_LIST_HEAD(&bridge->windows);
584 INIT_LIST_HEAD(&bridge->dma_ranges);
585
586 /*
587 * We assume we can manage these PCIe features. Some systems may
588 * reserve these for use by the platform itself, e.g., an ACPI BIOS
589 * may implement its own AER handling and use _OSC to prevent the
590 * OS from interfering.
591 */
592 bridge->native_aer = 1;
593 bridge->native_pcie_hotplug = 1;
594 bridge->native_shpc_hotplug = 1;
595 bridge->native_pme = 1;
596 bridge->native_ltr = 1;
597 bridge->native_dpc = 1;
598 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
599
600 device_initialize(&bridge->dev);
601}
602
603struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
604{
605 struct pci_host_bridge *bridge;
606
607 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
608 if (!bridge)
609 return NULL;
610
611 pci_init_host_bridge(bridge);
612 bridge->dev.release = pci_release_host_bridge_dev;
613
614 return bridge;
615}
616EXPORT_SYMBOL(pci_alloc_host_bridge);
617
618static void devm_pci_alloc_host_bridge_release(void *data)
619{
620 pci_free_host_bridge(data);
621}
622
623struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
624 size_t priv)
625{
626 int ret;
627 struct pci_host_bridge *bridge;
628
629 bridge = pci_alloc_host_bridge(priv);
630 if (!bridge)
631 return NULL;
632
633 bridge->dev.parent = dev;
634
635 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
636 bridge);
637 if (ret)
638 return NULL;
639
640 ret = devm_of_pci_bridge_init(dev, bridge);
641 if (ret)
642 return NULL;
643
644 return bridge;
645}
646EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
647
648void pci_free_host_bridge(struct pci_host_bridge *bridge)
649{
650 put_device(&bridge->dev);
651}
652EXPORT_SYMBOL(pci_free_host_bridge);
653
654/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
655static const unsigned char pcix_bus_speed[] = {
656 PCI_SPEED_UNKNOWN, /* 0 */
657 PCI_SPEED_66MHz_PCIX, /* 1 */
658 PCI_SPEED_100MHz_PCIX, /* 2 */
659 PCI_SPEED_133MHz_PCIX, /* 3 */
660 PCI_SPEED_UNKNOWN, /* 4 */
661 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
662 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
663 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
664 PCI_SPEED_UNKNOWN, /* 8 */
665 PCI_SPEED_66MHz_PCIX_266, /* 9 */
666 PCI_SPEED_100MHz_PCIX_266, /* A */
667 PCI_SPEED_133MHz_PCIX_266, /* B */
668 PCI_SPEED_UNKNOWN, /* C */
669 PCI_SPEED_66MHz_PCIX_533, /* D */
670 PCI_SPEED_100MHz_PCIX_533, /* E */
671 PCI_SPEED_133MHz_PCIX_533 /* F */
672};
673
674/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
675const unsigned char pcie_link_speed[] = {
676 PCI_SPEED_UNKNOWN, /* 0 */
677 PCIE_SPEED_2_5GT, /* 1 */
678 PCIE_SPEED_5_0GT, /* 2 */
679 PCIE_SPEED_8_0GT, /* 3 */
680 PCIE_SPEED_16_0GT, /* 4 */
681 PCIE_SPEED_32_0GT, /* 5 */
682 PCIE_SPEED_64_0GT, /* 6 */
683 PCI_SPEED_UNKNOWN, /* 7 */
684 PCI_SPEED_UNKNOWN, /* 8 */
685 PCI_SPEED_UNKNOWN, /* 9 */
686 PCI_SPEED_UNKNOWN, /* A */
687 PCI_SPEED_UNKNOWN, /* B */
688 PCI_SPEED_UNKNOWN, /* C */
689 PCI_SPEED_UNKNOWN, /* D */
690 PCI_SPEED_UNKNOWN, /* E */
691 PCI_SPEED_UNKNOWN /* F */
692};
693EXPORT_SYMBOL_GPL(pcie_link_speed);
694
695const char *pci_speed_string(enum pci_bus_speed speed)
696{
697 /* Indexed by the pci_bus_speed enum */
698 static const char *speed_strings[] = {
699 "33 MHz PCI", /* 0x00 */
700 "66 MHz PCI", /* 0x01 */
701 "66 MHz PCI-X", /* 0x02 */
702 "100 MHz PCI-X", /* 0x03 */
703 "133 MHz PCI-X", /* 0x04 */
704 NULL, /* 0x05 */
705 NULL, /* 0x06 */
706 NULL, /* 0x07 */
707 NULL, /* 0x08 */
708 "66 MHz PCI-X 266", /* 0x09 */
709 "100 MHz PCI-X 266", /* 0x0a */
710 "133 MHz PCI-X 266", /* 0x0b */
711 "Unknown AGP", /* 0x0c */
712 "1x AGP", /* 0x0d */
713 "2x AGP", /* 0x0e */
714 "4x AGP", /* 0x0f */
715 "8x AGP", /* 0x10 */
716 "66 MHz PCI-X 533", /* 0x11 */
717 "100 MHz PCI-X 533", /* 0x12 */
718 "133 MHz PCI-X 533", /* 0x13 */
719 "2.5 GT/s PCIe", /* 0x14 */
720 "5.0 GT/s PCIe", /* 0x15 */
721 "8.0 GT/s PCIe", /* 0x16 */
722 "16.0 GT/s PCIe", /* 0x17 */
723 "32.0 GT/s PCIe", /* 0x18 */
724 "64.0 GT/s PCIe", /* 0x19 */
725 };
726
727 if (speed < ARRAY_SIZE(speed_strings))
728 return speed_strings[speed];
729 return "Unknown";
730}
731EXPORT_SYMBOL_GPL(pci_speed_string);
732
733void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
734{
735 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
736}
737EXPORT_SYMBOL_GPL(pcie_update_link_speed);
738
739static unsigned char agp_speeds[] = {
740 AGP_UNKNOWN,
741 AGP_1X,
742 AGP_2X,
743 AGP_4X,
744 AGP_8X
745};
746
747static enum pci_bus_speed agp_speed(int agp3, int agpstat)
748{
749 int index = 0;
750
751 if (agpstat & 4)
752 index = 3;
753 else if (agpstat & 2)
754 index = 2;
755 else if (agpstat & 1)
756 index = 1;
757 else
758 goto out;
759
760 if (agp3) {
761 index += 2;
762 if (index == 5)
763 index = 0;
764 }
765
766 out:
767 return agp_speeds[index];
768}
769
770static void pci_set_bus_speed(struct pci_bus *bus)
771{
772 struct pci_dev *bridge = bus->self;
773 int pos;
774
775 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
776 if (!pos)
777 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
778 if (pos) {
779 u32 agpstat, agpcmd;
780
781 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
782 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
783
784 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
785 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
786 }
787
788 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
789 if (pos) {
790 u16 status;
791 enum pci_bus_speed max;
792
793 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
794 &status);
795
796 if (status & PCI_X_SSTATUS_533MHZ) {
797 max = PCI_SPEED_133MHz_PCIX_533;
798 } else if (status & PCI_X_SSTATUS_266MHZ) {
799 max = PCI_SPEED_133MHz_PCIX_266;
800 } else if (status & PCI_X_SSTATUS_133MHZ) {
801 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
802 max = PCI_SPEED_133MHz_PCIX_ECC;
803 else
804 max = PCI_SPEED_133MHz_PCIX;
805 } else {
806 max = PCI_SPEED_66MHz_PCIX;
807 }
808
809 bus->max_bus_speed = max;
810 bus->cur_bus_speed = pcix_bus_speed[
811 (status & PCI_X_SSTATUS_FREQ) >> 6];
812
813 return;
814 }
815
816 if (pci_is_pcie(bridge)) {
817 u32 linkcap;
818 u16 linksta;
819
820 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
821 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
822 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
823
824 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
825 pcie_update_link_speed(bus, linksta);
826 }
827}
828
829static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
830{
831 struct irq_domain *d;
832
833 /* If the host bridge driver sets a MSI domain of the bridge, use it */
834 d = dev_get_msi_domain(bus->bridge);
835
836 /*
837 * Any firmware interface that can resolve the msi_domain
838 * should be called from here.
839 */
840 if (!d)
841 d = pci_host_bridge_of_msi_domain(bus);
842 if (!d)
843 d = pci_host_bridge_acpi_msi_domain(bus);
844
845 /*
846 * If no IRQ domain was found via the OF tree, try looking it up
847 * directly through the fwnode_handle.
848 */
849 if (!d) {
850 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
851
852 if (fwnode)
853 d = irq_find_matching_fwnode(fwnode,
854 DOMAIN_BUS_PCI_MSI);
855 }
856
857 return d;
858}
859
860static void pci_set_bus_msi_domain(struct pci_bus *bus)
861{
862 struct irq_domain *d;
863 struct pci_bus *b;
864
865 /*
866 * The bus can be a root bus, a subordinate bus, or a virtual bus
867 * created by an SR-IOV device. Walk up to the first bridge device
868 * found or derive the domain from the host bridge.
869 */
870 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
871 if (b->self)
872 d = dev_get_msi_domain(&b->self->dev);
873 }
874
875 if (!d)
876 d = pci_host_bridge_msi_domain(b);
877
878 dev_set_msi_domain(&bus->dev, d);
879}
880
881static int pci_register_host_bridge(struct pci_host_bridge *bridge)
882{
883 struct device *parent = bridge->dev.parent;
884 struct resource_entry *window, *next, *n;
885 struct pci_bus *bus, *b;
886 resource_size_t offset, next_offset;
887 LIST_HEAD(resources);
888 struct resource *res, *next_res;
889 char addr[64], *fmt;
890 const char *name;
891 int err;
892
893 bus = pci_alloc_bus(NULL);
894 if (!bus)
895 return -ENOMEM;
896
897 bridge->bus = bus;
898
899 bus->sysdata = bridge->sysdata;
900 bus->ops = bridge->ops;
901 bus->number = bus->busn_res.start = bridge->busnr;
902#ifdef CONFIG_PCI_DOMAINS_GENERIC
903 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)
904 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
905 else
906 bus->domain_nr = bridge->domain_nr;
907 if (bus->domain_nr < 0) {
908 err = bus->domain_nr;
909 goto free;
910 }
911#endif
912
913 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
914 if (b) {
915 /* Ignore it if we already got here via a different bridge */
916 dev_dbg(&b->dev, "bus already known\n");
917 err = -EEXIST;
918 goto free;
919 }
920
921 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
922 bridge->busnr);
923
924 err = pcibios_root_bridge_prepare(bridge);
925 if (err)
926 goto free;
927
928 /* Temporarily move resources off the list */
929 list_splice_init(&bridge->windows, &resources);
930 err = device_add(&bridge->dev);
931 if (err) {
932 put_device(&bridge->dev);
933 goto free;
934 }
935 bus->bridge = get_device(&bridge->dev);
936 device_enable_async_suspend(bus->bridge);
937 pci_set_bus_of_node(bus);
938 pci_set_bus_msi_domain(bus);
939 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&
940 !pci_host_of_has_msi_map(parent))
941 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
942
943 if (!parent)
944 set_dev_node(bus->bridge, pcibus_to_node(bus));
945
946 bus->dev.class = &pcibus_class;
947 bus->dev.parent = bus->bridge;
948
949 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
950 name = dev_name(&bus->dev);
951
952 err = device_register(&bus->dev);
953 if (err)
954 goto unregister;
955
956 pcibios_add_bus(bus);
957
958 if (bus->ops->add_bus) {
959 err = bus->ops->add_bus(bus);
960 if (WARN_ON(err < 0))
961 dev_err(&bus->dev, "failed to add bus: %d\n", err);
962 }
963
964 /* Create legacy_io and legacy_mem files for this bus */
965 pci_create_legacy_files(bus);
966
967 if (parent)
968 dev_info(parent, "PCI host bridge to bus %s\n", name);
969 else
970 pr_info("PCI host bridge to bus %s\n", name);
971
972 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
973 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
974
975 /* Coalesce contiguous windows */
976 resource_list_for_each_entry_safe(window, n, &resources) {
977 if (list_is_last(&window->node, &resources))
978 break;
979
980 next = list_next_entry(window, node);
981 offset = window->offset;
982 res = window->res;
983 next_offset = next->offset;
984 next_res = next->res;
985
986 if (res->flags != next_res->flags || offset != next_offset)
987 continue;
988
989 if (res->end + 1 == next_res->start) {
990 next_res->start = res->start;
991 res->flags = res->start = res->end = 0;
992 }
993 }
994
995 /* Add initial resources to the bus */
996 resource_list_for_each_entry_safe(window, n, &resources) {
997 offset = window->offset;
998 res = window->res;
999 if (!res->end)
1000 continue;
1001
1002 list_move_tail(&window->node, &bridge->windows);
1003
1004 if (res->flags & IORESOURCE_BUS)
1005 pci_bus_insert_busn_res(bus, bus->number, res->end);
1006 else
1007 pci_bus_add_resource(bus, res, 0);
1008
1009 if (offset) {
1010 if (resource_type(res) == IORESOURCE_IO)
1011 fmt = " (bus address [%#06llx-%#06llx])";
1012 else
1013 fmt = " (bus address [%#010llx-%#010llx])";
1014
1015 snprintf(addr, sizeof(addr), fmt,
1016 (unsigned long long)(res->start - offset),
1017 (unsigned long long)(res->end - offset));
1018 } else
1019 addr[0] = '\0';
1020
1021 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
1022 }
1023
1024 down_write(&pci_bus_sem);
1025 list_add_tail(&bus->node, &pci_root_buses);
1026 up_write(&pci_bus_sem);
1027
1028 return 0;
1029
1030unregister:
1031 put_device(&bridge->dev);
1032 device_del(&bridge->dev);
1033
1034free:
1035#ifdef CONFIG_PCI_DOMAINS_GENERIC
1036 pci_bus_release_domain_nr(bus, parent);
1037#endif
1038 kfree(bus);
1039 return err;
1040}
1041
1042static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
1043{
1044 int pos;
1045 u32 status;
1046
1047 /*
1048 * If extended config space isn't accessible on a bridge's primary
1049 * bus, we certainly can't access it on the secondary bus.
1050 */
1051 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1052 return false;
1053
1054 /*
1055 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1056 * extended config space is accessible on the primary, it's also
1057 * accessible on the secondary.
1058 */
1059 if (pci_is_pcie(bridge) &&
1060 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1061 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1062 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1063 return true;
1064
1065 /*
1066 * For the other bridge types:
1067 * - PCI-to-PCI bridges
1068 * - PCIe-to-PCI/PCI-X forward bridges
1069 * - PCI/PCI-X-to-PCIe reverse bridges
1070 * extended config space on the secondary side is only accessible
1071 * if the bridge supports PCI-X Mode 2.
1072 */
1073 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1074 if (!pos)
1075 return false;
1076
1077 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1078 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1079}
1080
1081static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1082 struct pci_dev *bridge, int busnr)
1083{
1084 struct pci_bus *child;
1085 struct pci_host_bridge *host;
1086 int i;
1087 int ret;
1088
1089 /* Allocate a new bus and inherit stuff from the parent */
1090 child = pci_alloc_bus(parent);
1091 if (!child)
1092 return NULL;
1093
1094 child->parent = parent;
1095 child->sysdata = parent->sysdata;
1096 child->bus_flags = parent->bus_flags;
1097
1098 host = pci_find_host_bridge(parent);
1099 if (host->child_ops)
1100 child->ops = host->child_ops;
1101 else
1102 child->ops = parent->ops;
1103
1104 /*
1105 * Initialize some portions of the bus device, but don't register
1106 * it now as the parent is not properly set up yet.
1107 */
1108 child->dev.class = &pcibus_class;
1109 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1110
1111 /* Set up the primary, secondary and subordinate bus numbers */
1112 child->number = child->busn_res.start = busnr;
1113 child->primary = parent->busn_res.start;
1114 child->busn_res.end = 0xff;
1115
1116 if (!bridge) {
1117 child->dev.parent = parent->bridge;
1118 goto add_dev;
1119 }
1120
1121 child->self = bridge;
1122 child->bridge = get_device(&bridge->dev);
1123 child->dev.parent = child->bridge;
1124 pci_set_bus_of_node(child);
1125 pci_set_bus_speed(child);
1126
1127 /*
1128 * Check whether extended config space is accessible on the child
1129 * bus. Note that we currently assume it is always accessible on
1130 * the root bus.
1131 */
1132 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1133 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1134 pci_info(child, "extended config space not accessible\n");
1135 }
1136
1137 /* Set up default resource pointers and names */
1138 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1139 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1140 child->resource[i]->name = child->name;
1141 }
1142 bridge->subordinate = child;
1143
1144add_dev:
1145 pci_set_bus_msi_domain(child);
1146 ret = device_register(&child->dev);
1147 WARN_ON(ret < 0);
1148
1149 pcibios_add_bus(child);
1150
1151 if (child->ops->add_bus) {
1152 ret = child->ops->add_bus(child);
1153 if (WARN_ON(ret < 0))
1154 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1155 }
1156
1157 /* Create legacy_io and legacy_mem files for this bus */
1158 pci_create_legacy_files(child);
1159
1160 return child;
1161}
1162
1163struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1164 int busnr)
1165{
1166 struct pci_bus *child;
1167
1168 child = pci_alloc_child_bus(parent, dev, busnr);
1169 if (child) {
1170 down_write(&pci_bus_sem);
1171 list_add_tail(&child->node, &parent->children);
1172 up_write(&pci_bus_sem);
1173 }
1174 return child;
1175}
1176EXPORT_SYMBOL(pci_add_new_bus);
1177
1178static void pci_enable_crs(struct pci_dev *pdev)
1179{
1180 u16 root_cap = 0;
1181
1182 /* Enable CRS Software Visibility if supported */
1183 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1184 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1185 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1186 PCI_EXP_RTCTL_CRSSVE);
1187}
1188
1189static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1190 unsigned int available_buses);
1191/**
1192 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1193 * numbers from EA capability.
1194 * @dev: Bridge
1195 * @sec: updated with secondary bus number from EA
1196 * @sub: updated with subordinate bus number from EA
1197 *
1198 * If @dev is a bridge with EA capability that specifies valid secondary
1199 * and subordinate bus numbers, return true with the bus numbers in @sec
1200 * and @sub. Otherwise return false.
1201 */
1202static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1203{
1204 int ea, offset;
1205 u32 dw;
1206 u8 ea_sec, ea_sub;
1207
1208 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1209 return false;
1210
1211 /* find PCI EA capability in list */
1212 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1213 if (!ea)
1214 return false;
1215
1216 offset = ea + PCI_EA_FIRST_ENT;
1217 pci_read_config_dword(dev, offset, &dw);
1218 ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1219 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1220 if (ea_sec == 0 || ea_sub < ea_sec)
1221 return false;
1222
1223 *sec = ea_sec;
1224 *sub = ea_sub;
1225 return true;
1226}
1227
1228/*
1229 * pci_scan_bridge_extend() - Scan buses behind a bridge
1230 * @bus: Parent bus the bridge is on
1231 * @dev: Bridge itself
1232 * @max: Starting subordinate number of buses behind this bridge
1233 * @available_buses: Total number of buses available for this bridge and
1234 * the devices below. After the minimal bus space has
1235 * been allocated the remaining buses will be
1236 * distributed equally between hotplug-capable bridges.
1237 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1238 * that need to be reconfigured.
1239 *
1240 * If it's a bridge, configure it and scan the bus behind it.
1241 * For CardBus bridges, we don't scan behind as the devices will
1242 * be handled by the bridge driver itself.
1243 *
1244 * We need to process bridges in two passes -- first we scan those
1245 * already configured by the BIOS and after we are done with all of
1246 * them, we proceed to assigning numbers to the remaining buses in
1247 * order to avoid overlaps between old and new bus numbers.
1248 *
1249 * Return: New subordinate number covering all buses behind this bridge.
1250 */
1251static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1252 int max, unsigned int available_buses,
1253 int pass)
1254{
1255 struct pci_bus *child;
1256 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1257 u32 buses, i, j = 0;
1258 u16 bctl;
1259 u8 primary, secondary, subordinate;
1260 int broken = 0;
1261 bool fixed_buses;
1262 u8 fixed_sec, fixed_sub;
1263 int next_busnr;
1264
1265 /*
1266 * Make sure the bridge is powered on to be able to access config
1267 * space of devices below it.
1268 */
1269 pm_runtime_get_sync(&dev->dev);
1270
1271 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1272 primary = buses & 0xFF;
1273 secondary = (buses >> 8) & 0xFF;
1274 subordinate = (buses >> 16) & 0xFF;
1275
1276 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1277 secondary, subordinate, pass);
1278
1279 if (!primary && (primary != bus->number) && secondary && subordinate) {
1280 pci_warn(dev, "Primary bus is hard wired to 0\n");
1281 primary = bus->number;
1282 }
1283
1284 /* Check if setup is sensible at all */
1285 if (!pass &&
1286 (primary != bus->number || secondary <= bus->number ||
1287 secondary > subordinate)) {
1288 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1289 secondary, subordinate);
1290 broken = 1;
1291 }
1292
1293 /*
1294 * Disable Master-Abort Mode during probing to avoid reporting of
1295 * bus errors in some architectures.
1296 */
1297 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1298 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1299 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1300
1301 pci_enable_crs(dev);
1302
1303 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1304 !is_cardbus && !broken) {
1305 unsigned int cmax, buses;
1306
1307 /*
1308 * Bus already configured by firmware, process it in the
1309 * first pass and just note the configuration.
1310 */
1311 if (pass)
1312 goto out;
1313
1314 /*
1315 * The bus might already exist for two reasons: Either we
1316 * are rescanning the bus or the bus is reachable through
1317 * more than one bridge. The second case can happen with
1318 * the i450NX chipset.
1319 */
1320 child = pci_find_bus(pci_domain_nr(bus), secondary);
1321 if (!child) {
1322 child = pci_add_new_bus(bus, dev, secondary);
1323 if (!child)
1324 goto out;
1325 child->primary = primary;
1326 pci_bus_insert_busn_res(child, secondary, subordinate);
1327 child->bridge_ctl = bctl;
1328 }
1329
1330 buses = subordinate - secondary;
1331 cmax = pci_scan_child_bus_extend(child, buses);
1332 if (cmax > subordinate)
1333 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1334 subordinate, cmax);
1335
1336 /* Subordinate should equal child->busn_res.end */
1337 if (subordinate > max)
1338 max = subordinate;
1339 } else {
1340
1341 /*
1342 * We need to assign a number to this bus which we always
1343 * do in the second pass.
1344 */
1345 if (!pass) {
1346 if (pcibios_assign_all_busses() || broken || is_cardbus)
1347
1348 /*
1349 * Temporarily disable forwarding of the
1350 * configuration cycles on all bridges in
1351 * this bus segment to avoid possible
1352 * conflicts in the second pass between two
1353 * bridges programmed with overlapping bus
1354 * ranges.
1355 */
1356 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1357 buses & ~0xffffff);
1358 goto out;
1359 }
1360
1361 /* Clear errors */
1362 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1363
1364 /* Read bus numbers from EA Capability (if present) */
1365 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1366 if (fixed_buses)
1367 next_busnr = fixed_sec;
1368 else
1369 next_busnr = max + 1;
1370
1371 /*
1372 * Prevent assigning a bus number that already exists.
1373 * This can happen when a bridge is hot-plugged, so in this
1374 * case we only re-scan this bus.
1375 */
1376 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1377 if (!child) {
1378 child = pci_add_new_bus(bus, dev, next_busnr);
1379 if (!child)
1380 goto out;
1381 pci_bus_insert_busn_res(child, next_busnr,
1382 bus->busn_res.end);
1383 }
1384 max++;
1385 if (available_buses)
1386 available_buses--;
1387
1388 buses = (buses & 0xff000000)
1389 | ((unsigned int)(child->primary) << 0)
1390 | ((unsigned int)(child->busn_res.start) << 8)
1391 | ((unsigned int)(child->busn_res.end) << 16);
1392
1393 /*
1394 * yenta.c forces a secondary latency timer of 176.
1395 * Copy that behaviour here.
1396 */
1397 if (is_cardbus) {
1398 buses &= ~0xff000000;
1399 buses |= CARDBUS_LATENCY_TIMER << 24;
1400 }
1401
1402 /* We need to blast all three values with a single write */
1403 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1404
1405 if (!is_cardbus) {
1406 child->bridge_ctl = bctl;
1407 max = pci_scan_child_bus_extend(child, available_buses);
1408 } else {
1409
1410 /*
1411 * For CardBus bridges, we leave 4 bus numbers as
1412 * cards with a PCI-to-PCI bridge can be inserted
1413 * later.
1414 */
1415 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1416 struct pci_bus *parent = bus;
1417 if (pci_find_bus(pci_domain_nr(bus),
1418 max+i+1))
1419 break;
1420 while (parent->parent) {
1421 if ((!pcibios_assign_all_busses()) &&
1422 (parent->busn_res.end > max) &&
1423 (parent->busn_res.end <= max+i)) {
1424 j = 1;
1425 }
1426 parent = parent->parent;
1427 }
1428 if (j) {
1429
1430 /*
1431 * Often, there are two CardBus
1432 * bridges -- try to leave one
1433 * valid bus number for each one.
1434 */
1435 i /= 2;
1436 break;
1437 }
1438 }
1439 max += i;
1440 }
1441
1442 /*
1443 * Set subordinate bus number to its real value.
1444 * If fixed subordinate bus number exists from EA
1445 * capability then use it.
1446 */
1447 if (fixed_buses)
1448 max = fixed_sub;
1449 pci_bus_update_busn_res_end(child, max);
1450 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1451 }
1452
1453 sprintf(child->name,
1454 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1455 pci_domain_nr(bus), child->number);
1456
1457 /* Check that all devices are accessible */
1458 while (bus->parent) {
1459 if ((child->busn_res.end > bus->busn_res.end) ||
1460 (child->number > bus->busn_res.end) ||
1461 (child->number < bus->number) ||
1462 (child->busn_res.end < bus->number)) {
1463 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1464 &child->busn_res);
1465 break;
1466 }
1467 bus = bus->parent;
1468 }
1469
1470out:
1471 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1472
1473 pm_runtime_put(&dev->dev);
1474
1475 return max;
1476}
1477
1478/*
1479 * pci_scan_bridge() - Scan buses behind a bridge
1480 * @bus: Parent bus the bridge is on
1481 * @dev: Bridge itself
1482 * @max: Starting subordinate number of buses behind this bridge
1483 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1484 * that need to be reconfigured.
1485 *
1486 * If it's a bridge, configure it and scan the bus behind it.
1487 * For CardBus bridges, we don't scan behind as the devices will
1488 * be handled by the bridge driver itself.
1489 *
1490 * We need to process bridges in two passes -- first we scan those
1491 * already configured by the BIOS and after we are done with all of
1492 * them, we proceed to assigning numbers to the remaining buses in
1493 * order to avoid overlaps between old and new bus numbers.
1494 *
1495 * Return: New subordinate number covering all buses behind this bridge.
1496 */
1497int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1498{
1499 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1500}
1501EXPORT_SYMBOL(pci_scan_bridge);
1502
1503/*
1504 * Read interrupt line and base address registers.
1505 * The architecture-dependent code can tweak these, of course.
1506 */
1507static void pci_read_irq(struct pci_dev *dev)
1508{
1509 unsigned char irq;
1510
1511 /* VFs are not allowed to use INTx, so skip the config reads */
1512 if (dev->is_virtfn) {
1513 dev->pin = 0;
1514 dev->irq = 0;
1515 return;
1516 }
1517
1518 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1519 dev->pin = irq;
1520 if (irq)
1521 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1522 dev->irq = irq;
1523}
1524
1525void set_pcie_port_type(struct pci_dev *pdev)
1526{
1527 int pos;
1528 u16 reg16;
1529 int type;
1530 struct pci_dev *parent;
1531
1532 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1533 if (!pos)
1534 return;
1535
1536 pdev->pcie_cap = pos;
1537 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1538 pdev->pcie_flags_reg = reg16;
1539 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
1540 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
1541
1542 parent = pci_upstream_bridge(pdev);
1543 if (!parent)
1544 return;
1545
1546 /*
1547 * Some systems do not identify their upstream/downstream ports
1548 * correctly so detect impossible configurations here and correct
1549 * the port type accordingly.
1550 */
1551 type = pci_pcie_type(pdev);
1552 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1553 /*
1554 * If pdev claims to be downstream port but the parent
1555 * device is also downstream port assume pdev is actually
1556 * upstream port.
1557 */
1558 if (pcie_downstream_port(parent)) {
1559 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1560 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1561 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1562 }
1563 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1564 /*
1565 * If pdev claims to be upstream port but the parent
1566 * device is also upstream port assume pdev is actually
1567 * downstream port.
1568 */
1569 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1570 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1571 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1572 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1573 }
1574 }
1575}
1576
1577void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1578{
1579 u32 reg32;
1580
1581 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1582 if (reg32 & PCI_EXP_SLTCAP_HPC)
1583 pdev->is_hotplug_bridge = 1;
1584}
1585
1586static void set_pcie_thunderbolt(struct pci_dev *dev)
1587{
1588 u16 vsec;
1589
1590 /* Is the device part of a Thunderbolt controller? */
1591 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT);
1592 if (vsec)
1593 dev->is_thunderbolt = 1;
1594}
1595
1596static void set_pcie_untrusted(struct pci_dev *dev)
1597{
1598 struct pci_dev *parent;
1599
1600 /*
1601 * If the upstream bridge is untrusted we treat this device
1602 * untrusted as well.
1603 */
1604 parent = pci_upstream_bridge(dev);
1605 if (parent && (parent->untrusted || parent->external_facing))
1606 dev->untrusted = true;
1607}
1608
1609static void pci_set_removable(struct pci_dev *dev)
1610{
1611 struct pci_dev *parent = pci_upstream_bridge(dev);
1612
1613 /*
1614 * We (only) consider everything downstream from an external_facing
1615 * device to be removable by the user. We're mainly concerned with
1616 * consumer platforms with user accessible thunderbolt ports that are
1617 * vulnerable to DMA attacks, and we expect those ports to be marked by
1618 * the firmware as external_facing. Devices in traditional hotplug
1619 * slots can technically be removed, but the expectation is that unless
1620 * the port is marked with external_facing, such devices are less
1621 * accessible to user / may not be removed by end user, and thus not
1622 * exposed as "removable" to userspace.
1623 */
1624 if (parent &&
1625 (parent->external_facing || dev_is_removable(&parent->dev)))
1626 dev_set_removable(&dev->dev, DEVICE_REMOVABLE);
1627}
1628
1629/**
1630 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1631 * @dev: PCI device
1632 *
1633 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1634 * when forwarding a type1 configuration request the bridge must check that
1635 * the extended register address field is zero. The bridge is not permitted
1636 * to forward the transactions and must handle it as an Unsupported Request.
1637 * Some bridges do not follow this rule and simply drop the extended register
1638 * bits, resulting in the standard config space being aliased, every 256
1639 * bytes across the entire configuration space. Test for this condition by
1640 * comparing the first dword of each potential alias to the vendor/device ID.
1641 * Known offenders:
1642 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1643 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1644 */
1645static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1646{
1647#ifdef CONFIG_PCI_QUIRKS
1648 int pos;
1649 u32 header, tmp;
1650
1651 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1652
1653 for (pos = PCI_CFG_SPACE_SIZE;
1654 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1655 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1656 || header != tmp)
1657 return false;
1658 }
1659
1660 return true;
1661#else
1662 return false;
1663#endif
1664}
1665
1666/**
1667 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1668 * @dev: PCI device
1669 *
1670 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1671 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1672 * access it. Maybe we don't have a way to generate extended config space
1673 * accesses, or the device is behind a reverse Express bridge. So we try
1674 * reading the dword at 0x100 which must either be 0 or a valid extended
1675 * capability header.
1676 */
1677static int pci_cfg_space_size_ext(struct pci_dev *dev)
1678{
1679 u32 status;
1680 int pos = PCI_CFG_SPACE_SIZE;
1681
1682 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1683 return PCI_CFG_SPACE_SIZE;
1684 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
1685 return PCI_CFG_SPACE_SIZE;
1686
1687 return PCI_CFG_SPACE_EXP_SIZE;
1688}
1689
1690int pci_cfg_space_size(struct pci_dev *dev)
1691{
1692 int pos;
1693 u32 status;
1694 u16 class;
1695
1696#ifdef CONFIG_PCI_IOV
1697 /*
1698 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1699 * implement a PCIe capability and therefore must implement extended
1700 * config space. We can skip the NO_EXTCFG test below and the
1701 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1702 * the fact that the SR-IOV capability on the PF resides in extended
1703 * config space and must be accessible and non-aliased to have enabled
1704 * support for this VF. This is a micro performance optimization for
1705 * systems supporting many VFs.
1706 */
1707 if (dev->is_virtfn)
1708 return PCI_CFG_SPACE_EXP_SIZE;
1709#endif
1710
1711 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1712 return PCI_CFG_SPACE_SIZE;
1713
1714 class = dev->class >> 8;
1715 if (class == PCI_CLASS_BRIDGE_HOST)
1716 return pci_cfg_space_size_ext(dev);
1717
1718 if (pci_is_pcie(dev))
1719 return pci_cfg_space_size_ext(dev);
1720
1721 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1722 if (!pos)
1723 return PCI_CFG_SPACE_SIZE;
1724
1725 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1726 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1727 return pci_cfg_space_size_ext(dev);
1728
1729 return PCI_CFG_SPACE_SIZE;
1730}
1731
1732static u32 pci_class(struct pci_dev *dev)
1733{
1734 u32 class;
1735
1736#ifdef CONFIG_PCI_IOV
1737 if (dev->is_virtfn)
1738 return dev->physfn->sriov->class;
1739#endif
1740 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1741 return class;
1742}
1743
1744static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1745{
1746#ifdef CONFIG_PCI_IOV
1747 if (dev->is_virtfn) {
1748 *vendor = dev->physfn->sriov->subsystem_vendor;
1749 *device = dev->physfn->sriov->subsystem_device;
1750 return;
1751 }
1752#endif
1753 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1754 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1755}
1756
1757static u8 pci_hdr_type(struct pci_dev *dev)
1758{
1759 u8 hdr_type;
1760
1761#ifdef CONFIG_PCI_IOV
1762 if (dev->is_virtfn)
1763 return dev->physfn->sriov->hdr_type;
1764#endif
1765 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1766 return hdr_type;
1767}
1768
1769#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1770
1771/**
1772 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1773 * @dev: PCI device
1774 *
1775 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1776 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1777 */
1778static int pci_intx_mask_broken(struct pci_dev *dev)
1779{
1780 u16 orig, toggle, new;
1781
1782 pci_read_config_word(dev, PCI_COMMAND, &orig);
1783 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1784 pci_write_config_word(dev, PCI_COMMAND, toggle);
1785 pci_read_config_word(dev, PCI_COMMAND, &new);
1786
1787 pci_write_config_word(dev, PCI_COMMAND, orig);
1788
1789 /*
1790 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1791 * r2.3, so strictly speaking, a device is not *broken* if it's not
1792 * writable. But we'll live with the misnomer for now.
1793 */
1794 if (new != toggle)
1795 return 1;
1796 return 0;
1797}
1798
1799static void early_dump_pci_device(struct pci_dev *pdev)
1800{
1801 u32 value[256 / 4];
1802 int i;
1803
1804 pci_info(pdev, "config space:\n");
1805
1806 for (i = 0; i < 256; i += 4)
1807 pci_read_config_dword(pdev, i, &value[i / 4]);
1808
1809 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1810 value, 256, false);
1811}
1812
1813/**
1814 * pci_setup_device - Fill in class and map information of a device
1815 * @dev: the device structure to fill
1816 *
1817 * Initialize the device structure with information about the device's
1818 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1819 * Called at initialisation of the PCI subsystem and by CardBus services.
1820 * Returns 0 on success and negative if unknown type of device (not normal,
1821 * bridge or CardBus).
1822 */
1823int pci_setup_device(struct pci_dev *dev)
1824{
1825 u32 class;
1826 u16 cmd;
1827 u8 hdr_type;
1828 int pos = 0;
1829 struct pci_bus_region region;
1830 struct resource *res;
1831
1832 hdr_type = pci_hdr_type(dev);
1833
1834 dev->sysdata = dev->bus->sysdata;
1835 dev->dev.parent = dev->bus->bridge;
1836 dev->dev.bus = &pci_bus_type;
1837 dev->hdr_type = hdr_type & 0x7f;
1838 dev->multifunction = !!(hdr_type & 0x80);
1839 dev->error_state = pci_channel_io_normal;
1840 set_pcie_port_type(dev);
1841
1842 pci_set_of_node(dev);
1843 pci_set_acpi_fwnode(dev);
1844
1845 pci_dev_assign_slot(dev);
1846
1847 /*
1848 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1849 * set this higher, assuming the system even supports it.
1850 */
1851 dev->dma_mask = 0xffffffff;
1852
1853 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1854 dev->bus->number, PCI_SLOT(dev->devfn),
1855 PCI_FUNC(dev->devfn));
1856
1857 class = pci_class(dev);
1858
1859 dev->revision = class & 0xff;
1860 dev->class = class >> 8; /* upper 3 bytes */
1861
1862 if (pci_early_dump)
1863 early_dump_pci_device(dev);
1864
1865 /* Need to have dev->class ready */
1866 dev->cfg_size = pci_cfg_space_size(dev);
1867
1868 /* Need to have dev->cfg_size ready */
1869 set_pcie_thunderbolt(dev);
1870
1871 set_pcie_untrusted(dev);
1872
1873 /* "Unknown power state" */
1874 dev->current_state = PCI_UNKNOWN;
1875
1876 /* Early fixups, before probing the BARs */
1877 pci_fixup_device(pci_fixup_early, dev);
1878
1879 pci_set_removable(dev);
1880
1881 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1882 dev->vendor, dev->device, dev->hdr_type, dev->class);
1883
1884 /* Device class may be changed after fixup */
1885 class = dev->class >> 8;
1886
1887 if (dev->non_compliant_bars && !dev->mmio_always_on) {
1888 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1889 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1890 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1891 cmd &= ~PCI_COMMAND_IO;
1892 cmd &= ~PCI_COMMAND_MEMORY;
1893 pci_write_config_word(dev, PCI_COMMAND, cmd);
1894 }
1895 }
1896
1897 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1898
1899 switch (dev->hdr_type) { /* header type */
1900 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1901 if (class == PCI_CLASS_BRIDGE_PCI)
1902 goto bad;
1903 pci_read_irq(dev);
1904 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1905
1906 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1907
1908 /*
1909 * Do the ugly legacy mode stuff here rather than broken chip
1910 * quirk code. Legacy mode ATA controllers have fixed
1911 * addresses. These are not always echoed in BAR0-3, and
1912 * BAR0-3 in a few cases contain junk!
1913 */
1914 if (class == PCI_CLASS_STORAGE_IDE) {
1915 u8 progif;
1916 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1917 if ((progif & 1) == 0) {
1918 region.start = 0x1F0;
1919 region.end = 0x1F7;
1920 res = &dev->resource[0];
1921 res->flags = LEGACY_IO_RESOURCE;
1922 pcibios_bus_to_resource(dev->bus, res, ®ion);
1923 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1924 res);
1925 region.start = 0x3F6;
1926 region.end = 0x3F6;
1927 res = &dev->resource[1];
1928 res->flags = LEGACY_IO_RESOURCE;
1929 pcibios_bus_to_resource(dev->bus, res, ®ion);
1930 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1931 res);
1932 }
1933 if ((progif & 4) == 0) {
1934 region.start = 0x170;
1935 region.end = 0x177;
1936 res = &dev->resource[2];
1937 res->flags = LEGACY_IO_RESOURCE;
1938 pcibios_bus_to_resource(dev->bus, res, ®ion);
1939 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1940 res);
1941 region.start = 0x376;
1942 region.end = 0x376;
1943 res = &dev->resource[3];
1944 res->flags = LEGACY_IO_RESOURCE;
1945 pcibios_bus_to_resource(dev->bus, res, ®ion);
1946 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1947 res);
1948 }
1949 }
1950 break;
1951
1952 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1953 /*
1954 * The PCI-to-PCI bridge spec requires that subtractive
1955 * decoding (i.e. transparent) bridge must have programming
1956 * interface code of 0x01.
1957 */
1958 pci_read_irq(dev);
1959 dev->transparent = ((dev->class & 0xff) == 1);
1960 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1961 pci_read_bridge_windows(dev);
1962 set_pcie_hotplug_bridge(dev);
1963 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1964 if (pos) {
1965 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1966 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1967 }
1968 break;
1969
1970 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1971 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1972 goto bad;
1973 pci_read_irq(dev);
1974 pci_read_bases(dev, 1, 0);
1975 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1976 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1977 break;
1978
1979 default: /* unknown header */
1980 pci_err(dev, "unknown header type %02x, ignoring device\n",
1981 dev->hdr_type);
1982 pci_release_of_node(dev);
1983 return -EIO;
1984
1985 bad:
1986 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1987 dev->class, dev->hdr_type);
1988 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1989 }
1990
1991 /* We found a fine healthy device, go go go... */
1992 return 0;
1993}
1994
1995static void pci_configure_mps(struct pci_dev *dev)
1996{
1997 struct pci_dev *bridge = pci_upstream_bridge(dev);
1998 int mps, mpss, p_mps, rc;
1999
2000 if (!pci_is_pcie(dev))
2001 return;
2002
2003 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
2004 if (dev->is_virtfn)
2005 return;
2006
2007 /*
2008 * For Root Complex Integrated Endpoints, program the maximum
2009 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
2010 */
2011 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
2012 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2013 mps = 128;
2014 else
2015 mps = 128 << dev->pcie_mpss;
2016 rc = pcie_set_mps(dev, mps);
2017 if (rc) {
2018 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2019 mps);
2020 }
2021 return;
2022 }
2023
2024 if (!bridge || !pci_is_pcie(bridge))
2025 return;
2026
2027 mps = pcie_get_mps(dev);
2028 p_mps = pcie_get_mps(bridge);
2029
2030 if (mps == p_mps)
2031 return;
2032
2033 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
2034 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2035 mps, pci_name(bridge), p_mps);
2036 return;
2037 }
2038
2039 /*
2040 * Fancier MPS configuration is done later by
2041 * pcie_bus_configure_settings()
2042 */
2043 if (pcie_bus_config != PCIE_BUS_DEFAULT)
2044 return;
2045
2046 mpss = 128 << dev->pcie_mpss;
2047 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
2048 pcie_set_mps(bridge, mpss);
2049 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
2050 mpss, p_mps, 128 << bridge->pcie_mpss);
2051 p_mps = pcie_get_mps(bridge);
2052 }
2053
2054 rc = pcie_set_mps(dev, p_mps);
2055 if (rc) {
2056 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2057 p_mps);
2058 return;
2059 }
2060
2061 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2062 p_mps, mps, mpss);
2063}
2064
2065int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2066{
2067 struct pci_host_bridge *host;
2068 u32 cap;
2069 u16 ctl;
2070 int ret;
2071
2072 if (!pci_is_pcie(dev))
2073 return 0;
2074
2075 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2076 if (ret)
2077 return 0;
2078
2079 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2080 return 0;
2081
2082 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2083 if (ret)
2084 return 0;
2085
2086 host = pci_find_host_bridge(dev->bus);
2087 if (!host)
2088 return 0;
2089
2090 /*
2091 * If some device in the hierarchy doesn't handle Extended Tags
2092 * correctly, make sure they're disabled.
2093 */
2094 if (host->no_ext_tags) {
2095 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2096 pci_info(dev, "disabling Extended Tags\n");
2097 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2098 PCI_EXP_DEVCTL_EXT_TAG);
2099 }
2100 return 0;
2101 }
2102
2103 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2104 pci_info(dev, "enabling Extended Tags\n");
2105 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2106 PCI_EXP_DEVCTL_EXT_TAG);
2107 }
2108 return 0;
2109}
2110
2111/**
2112 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2113 * @dev: PCI device to query
2114 *
2115 * Returns true if the device has enabled relaxed ordering attribute.
2116 */
2117bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2118{
2119 u16 v;
2120
2121 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2122
2123 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2124}
2125EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2126
2127static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2128{
2129 struct pci_dev *root;
2130
2131 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2132 if (dev->is_virtfn)
2133 return;
2134
2135 if (!pcie_relaxed_ordering_enabled(dev))
2136 return;
2137
2138 /*
2139 * For now, we only deal with Relaxed Ordering issues with Root
2140 * Ports. Peer-to-Peer DMA is another can of worms.
2141 */
2142 root = pcie_find_root_port(dev);
2143 if (!root)
2144 return;
2145
2146 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2147 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2148 PCI_EXP_DEVCTL_RELAX_EN);
2149 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2150 }
2151}
2152
2153static void pci_configure_ltr(struct pci_dev *dev)
2154{
2155#ifdef CONFIG_PCIEASPM
2156 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2157 struct pci_dev *bridge;
2158 u32 cap, ctl;
2159
2160 if (!pci_is_pcie(dev))
2161 return;
2162
2163 /* Read L1 PM substate capabilities */
2164 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
2165
2166 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2167 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2168 return;
2169
2170 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2171 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2172 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2173 dev->ltr_path = 1;
2174 return;
2175 }
2176
2177 bridge = pci_upstream_bridge(dev);
2178 if (bridge && bridge->ltr_path)
2179 dev->ltr_path = 1;
2180
2181 return;
2182 }
2183
2184 if (!host->native_ltr)
2185 return;
2186
2187 /*
2188 * Software must not enable LTR in an Endpoint unless the Root
2189 * Complex and all intermediate Switches indicate support for LTR.
2190 * PCIe r4.0, sec 6.18.
2191 */
2192 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2193 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2194 PCI_EXP_DEVCTL2_LTR_EN);
2195 dev->ltr_path = 1;
2196 return;
2197 }
2198
2199 /*
2200 * If we're configuring a hot-added device, LTR was likely
2201 * disabled in the upstream bridge, so re-enable it before enabling
2202 * it in the new device.
2203 */
2204 bridge = pci_upstream_bridge(dev);
2205 if (bridge && bridge->ltr_path) {
2206 pci_bridge_reconfigure_ltr(dev);
2207 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2208 PCI_EXP_DEVCTL2_LTR_EN);
2209 dev->ltr_path = 1;
2210 }
2211#endif
2212}
2213
2214static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2215{
2216#ifdef CONFIG_PCI_PASID
2217 struct pci_dev *bridge;
2218 int pcie_type;
2219 u32 cap;
2220
2221 if (!pci_is_pcie(dev))
2222 return;
2223
2224 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2225 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2226 return;
2227
2228 pcie_type = pci_pcie_type(dev);
2229 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2230 pcie_type == PCI_EXP_TYPE_RC_END)
2231 dev->eetlp_prefix_path = 1;
2232 else {
2233 bridge = pci_upstream_bridge(dev);
2234 if (bridge && bridge->eetlp_prefix_path)
2235 dev->eetlp_prefix_path = 1;
2236 }
2237#endif
2238}
2239
2240static void pci_configure_serr(struct pci_dev *dev)
2241{
2242 u16 control;
2243
2244 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2245
2246 /*
2247 * A bridge will not forward ERR_ messages coming from an
2248 * endpoint unless SERR# forwarding is enabled.
2249 */
2250 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2251 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2252 control |= PCI_BRIDGE_CTL_SERR;
2253 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2254 }
2255 }
2256}
2257
2258static void pci_configure_device(struct pci_dev *dev)
2259{
2260 pci_configure_mps(dev);
2261 pci_configure_extended_tags(dev, NULL);
2262 pci_configure_relaxed_ordering(dev);
2263 pci_configure_ltr(dev);
2264 pci_configure_eetlp_prefix(dev);
2265 pci_configure_serr(dev);
2266
2267 pci_acpi_program_hp_params(dev);
2268}
2269
2270static void pci_release_capabilities(struct pci_dev *dev)
2271{
2272 pci_aer_exit(dev);
2273 pci_rcec_exit(dev);
2274 pci_iov_release(dev);
2275 pci_free_cap_save_buffers(dev);
2276}
2277
2278/**
2279 * pci_release_dev - Free a PCI device structure when all users of it are
2280 * finished
2281 * @dev: device that's been disconnected
2282 *
2283 * Will be called only by the device core when all users of this PCI device are
2284 * done.
2285 */
2286static void pci_release_dev(struct device *dev)
2287{
2288 struct pci_dev *pci_dev;
2289
2290 pci_dev = to_pci_dev(dev);
2291 pci_release_capabilities(pci_dev);
2292 pci_release_of_node(pci_dev);
2293 pcibios_release_device(pci_dev);
2294 pci_bus_put(pci_dev->bus);
2295 kfree(pci_dev->driver_override);
2296 bitmap_free(pci_dev->dma_alias_mask);
2297 dev_dbg(dev, "device released\n");
2298 kfree(pci_dev);
2299}
2300
2301struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2302{
2303 struct pci_dev *dev;
2304
2305 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2306 if (!dev)
2307 return NULL;
2308
2309 INIT_LIST_HEAD(&dev->bus_list);
2310 dev->dev.type = &pci_dev_type;
2311 dev->bus = pci_bus_get(bus);
2312 dev->driver_exclusive_resource = (struct resource) {
2313 .name = "PCI Exclusive",
2314 .start = 0,
2315 .end = -1,
2316 };
2317
2318#ifdef CONFIG_PCI_MSI
2319 raw_spin_lock_init(&dev->msi_lock);
2320#endif
2321 return dev;
2322}
2323EXPORT_SYMBOL(pci_alloc_dev);
2324
2325static bool pci_bus_crs_vendor_id(u32 l)
2326{
2327 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
2328}
2329
2330static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2331 int timeout)
2332{
2333 int delay = 1;
2334
2335 if (!pci_bus_crs_vendor_id(*l))
2336 return true; /* not a CRS completion */
2337
2338 if (!timeout)
2339 return false; /* CRS, but caller doesn't want to wait */
2340
2341 /*
2342 * We got the reserved Vendor ID that indicates a completion with
2343 * Configuration Request Retry Status (CRS). Retry until we get a
2344 * valid Vendor ID or we time out.
2345 */
2346 while (pci_bus_crs_vendor_id(*l)) {
2347 if (delay > timeout) {
2348 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2349 pci_domain_nr(bus), bus->number,
2350 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2351
2352 return false;
2353 }
2354 if (delay >= 1000)
2355 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2356 pci_domain_nr(bus), bus->number,
2357 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2358
2359 msleep(delay);
2360 delay *= 2;
2361
2362 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2363 return false;
2364 }
2365
2366 if (delay >= 1000)
2367 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2368 pci_domain_nr(bus), bus->number,
2369 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2370
2371 return true;
2372}
2373
2374bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2375 int timeout)
2376{
2377 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2378 return false;
2379
2380 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
2381 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
2382 *l == 0x0000ffff || *l == 0xffff0000)
2383 return false;
2384
2385 if (pci_bus_crs_vendor_id(*l))
2386 return pci_bus_wait_crs(bus, devfn, l, timeout);
2387
2388 return true;
2389}
2390
2391bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2392 int timeout)
2393{
2394#ifdef CONFIG_PCI_QUIRKS
2395 struct pci_dev *bridge = bus->self;
2396
2397 /*
2398 * Certain IDT switches have an issue where they improperly trigger
2399 * ACS Source Validation errors on completions for config reads.
2400 */
2401 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2402 bridge->device == 0x80b5)
2403 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2404#endif
2405
2406 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2407}
2408EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2409
2410/*
2411 * Read the config data for a PCI device, sanity-check it,
2412 * and fill in the dev structure.
2413 */
2414static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2415{
2416 struct pci_dev *dev;
2417 u32 l;
2418
2419 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2420 return NULL;
2421
2422 dev = pci_alloc_dev(bus);
2423 if (!dev)
2424 return NULL;
2425
2426 dev->devfn = devfn;
2427 dev->vendor = l & 0xffff;
2428 dev->device = (l >> 16) & 0xffff;
2429
2430 if (pci_setup_device(dev)) {
2431 pci_bus_put(dev->bus);
2432 kfree(dev);
2433 return NULL;
2434 }
2435
2436 return dev;
2437}
2438
2439void pcie_report_downtraining(struct pci_dev *dev)
2440{
2441 if (!pci_is_pcie(dev))
2442 return;
2443
2444 /* Look from the device up to avoid downstream ports with no devices */
2445 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2446 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2447 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2448 return;
2449
2450 /* Multi-function PCIe devices share the same link/status */
2451 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2452 return;
2453
2454 /* Print link status only if the device is constrained by the fabric */
2455 __pcie_print_link_status(dev, false);
2456}
2457
2458static void pci_init_capabilities(struct pci_dev *dev)
2459{
2460 pci_ea_init(dev); /* Enhanced Allocation */
2461 pci_msi_init(dev); /* Disable MSI */
2462 pci_msix_init(dev); /* Disable MSI-X */
2463
2464 /* Buffers for saving PCIe and PCI-X capabilities */
2465 pci_allocate_cap_save_buffers(dev);
2466
2467 pci_pm_init(dev); /* Power Management */
2468 pci_vpd_init(dev); /* Vital Product Data */
2469 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
2470 pci_iov_init(dev); /* Single Root I/O Virtualization */
2471 pci_ats_init(dev); /* Address Translation Services */
2472 pci_pri_init(dev); /* Page Request Interface */
2473 pci_pasid_init(dev); /* Process Address Space ID */
2474 pci_acs_init(dev); /* Access Control Services */
2475 pci_ptm_init(dev); /* Precision Time Measurement */
2476 pci_aer_init(dev); /* Advanced Error Reporting */
2477 pci_dpc_init(dev); /* Downstream Port Containment */
2478 pci_rcec_init(dev); /* Root Complex Event Collector */
2479
2480 pcie_report_downtraining(dev);
2481 pci_init_reset_methods(dev);
2482}
2483
2484/*
2485 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2486 * devices. Firmware interfaces that can select the MSI domain on a
2487 * per-device basis should be called from here.
2488 */
2489static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2490{
2491 struct irq_domain *d;
2492
2493 /*
2494 * If a domain has been set through the pcibios_device_add()
2495 * callback, then this is the one (platform code knows best).
2496 */
2497 d = dev_get_msi_domain(&dev->dev);
2498 if (d)
2499 return d;
2500
2501 /*
2502 * Let's see if we have a firmware interface able to provide
2503 * the domain.
2504 */
2505 d = pci_msi_get_device_domain(dev);
2506 if (d)
2507 return d;
2508
2509 return NULL;
2510}
2511
2512static void pci_set_msi_domain(struct pci_dev *dev)
2513{
2514 struct irq_domain *d;
2515
2516 /*
2517 * If the platform or firmware interfaces cannot supply a
2518 * device-specific MSI domain, then inherit the default domain
2519 * from the host bridge itself.
2520 */
2521 d = pci_dev_msi_domain(dev);
2522 if (!d)
2523 d = dev_get_msi_domain(&dev->bus->dev);
2524
2525 dev_set_msi_domain(&dev->dev, d);
2526}
2527
2528void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2529{
2530 int ret;
2531
2532 pci_configure_device(dev);
2533
2534 device_initialize(&dev->dev);
2535 dev->dev.release = pci_release_dev;
2536
2537 set_dev_node(&dev->dev, pcibus_to_node(bus));
2538 dev->dev.dma_mask = &dev->dma_mask;
2539 dev->dev.dma_parms = &dev->dma_parms;
2540 dev->dev.coherent_dma_mask = 0xffffffffull;
2541
2542 dma_set_max_seg_size(&dev->dev, 65536);
2543 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2544
2545 /* Fix up broken headers */
2546 pci_fixup_device(pci_fixup_header, dev);
2547
2548 pci_reassigndev_resource_alignment(dev);
2549
2550 dev->state_saved = false;
2551
2552 pci_init_capabilities(dev);
2553
2554 /*
2555 * Add the device to our list of discovered devices
2556 * and the bus list for fixup functions, etc.
2557 */
2558 down_write(&pci_bus_sem);
2559 list_add_tail(&dev->bus_list, &bus->devices);
2560 up_write(&pci_bus_sem);
2561
2562 ret = pcibios_device_add(dev);
2563 WARN_ON(ret < 0);
2564
2565 /* Set up MSI IRQ domain */
2566 pci_set_msi_domain(dev);
2567
2568 /* Notifier could use PCI capabilities */
2569 dev->match_driver = false;
2570 ret = device_add(&dev->dev);
2571 WARN_ON(ret < 0);
2572}
2573
2574struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2575{
2576 struct pci_dev *dev;
2577
2578 dev = pci_get_slot(bus, devfn);
2579 if (dev) {
2580 pci_dev_put(dev);
2581 return dev;
2582 }
2583
2584 dev = pci_scan_device(bus, devfn);
2585 if (!dev)
2586 return NULL;
2587
2588 pci_device_add(dev, bus);
2589
2590 return dev;
2591}
2592EXPORT_SYMBOL(pci_scan_single_device);
2593
2594static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2595{
2596 int pos;
2597 u16 cap = 0;
2598 unsigned int next_fn;
2599
2600 if (!dev)
2601 return -ENODEV;
2602
2603 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2604 if (!pos)
2605 return -ENODEV;
2606
2607 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2608 next_fn = PCI_ARI_CAP_NFN(cap);
2609 if (next_fn <= fn)
2610 return -ENODEV; /* protect against malformed list */
2611
2612 return next_fn;
2613}
2614
2615static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2616{
2617 if (pci_ari_enabled(bus))
2618 return next_ari_fn(bus, dev, fn);
2619
2620 if (fn >= 7)
2621 return -ENODEV;
2622 /* only multifunction devices may have more functions */
2623 if (dev && !dev->multifunction)
2624 return -ENODEV;
2625
2626 return fn + 1;
2627}
2628
2629static int only_one_child(struct pci_bus *bus)
2630{
2631 struct pci_dev *bridge = bus->self;
2632
2633 /*
2634 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2635 * we scan for all possible devices, not just Device 0.
2636 */
2637 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2638 return 0;
2639
2640 /*
2641 * A PCIe Downstream Port normally leads to a Link with only Device
2642 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2643 * only for Device 0 in that situation.
2644 */
2645 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2646 return 1;
2647
2648 return 0;
2649}
2650
2651/**
2652 * pci_scan_slot - Scan a PCI slot on a bus for devices
2653 * @bus: PCI bus to scan
2654 * @devfn: slot number to scan (must have zero function)
2655 *
2656 * Scan a PCI slot on the specified PCI bus for devices, adding
2657 * discovered devices to the @bus->devices list. New devices
2658 * will not have is_added set.
2659 *
2660 * Returns the number of new devices found.
2661 */
2662int pci_scan_slot(struct pci_bus *bus, int devfn)
2663{
2664 struct pci_dev *dev;
2665 int fn = 0, nr = 0;
2666
2667 if (only_one_child(bus) && (devfn > 0))
2668 return 0; /* Already scanned the entire slot */
2669
2670 do {
2671 dev = pci_scan_single_device(bus, devfn + fn);
2672 if (dev) {
2673 if (!pci_dev_is_added(dev))
2674 nr++;
2675 if (fn > 0)
2676 dev->multifunction = 1;
2677 } else if (fn == 0) {
2678 /*
2679 * Function 0 is required unless we are running on
2680 * a hypervisor that passes through individual PCI
2681 * functions.
2682 */
2683 if (!hypervisor_isolated_pci_functions())
2684 break;
2685 }
2686 fn = next_fn(bus, dev, fn);
2687 } while (fn >= 0);
2688
2689 /* Only one slot has PCIe device */
2690 if (bus->self && nr)
2691 pcie_aspm_init_link_state(bus->self);
2692
2693 return nr;
2694}
2695EXPORT_SYMBOL(pci_scan_slot);
2696
2697static int pcie_find_smpss(struct pci_dev *dev, void *data)
2698{
2699 u8 *smpss = data;
2700
2701 if (!pci_is_pcie(dev))
2702 return 0;
2703
2704 /*
2705 * We don't have a way to change MPS settings on devices that have
2706 * drivers attached. A hot-added device might support only the minimum
2707 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2708 * where devices may be hot-added, we limit the fabric MPS to 128 so
2709 * hot-added devices will work correctly.
2710 *
2711 * However, if we hot-add a device to a slot directly below a Root
2712 * Port, it's impossible for there to be other existing devices below
2713 * the port. We don't limit the MPS in this case because we can
2714 * reconfigure MPS on both the Root Port and the hot-added device,
2715 * and there are no other devices involved.
2716 *
2717 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2718 */
2719 if (dev->is_hotplug_bridge &&
2720 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2721 *smpss = 0;
2722
2723 if (*smpss > dev->pcie_mpss)
2724 *smpss = dev->pcie_mpss;
2725
2726 return 0;
2727}
2728
2729static void pcie_write_mps(struct pci_dev *dev, int mps)
2730{
2731 int rc;
2732
2733 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2734 mps = 128 << dev->pcie_mpss;
2735
2736 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2737 dev->bus->self)
2738
2739 /*
2740 * For "Performance", the assumption is made that
2741 * downstream communication will never be larger than
2742 * the MRRS. So, the MPS only needs to be configured
2743 * for the upstream communication. This being the case,
2744 * walk from the top down and set the MPS of the child
2745 * to that of the parent bus.
2746 *
2747 * Configure the device MPS with the smaller of the
2748 * device MPSS or the bridge MPS (which is assumed to be
2749 * properly configured at this point to the largest
2750 * allowable MPS based on its parent bus).
2751 */
2752 mps = min(mps, pcie_get_mps(dev->bus->self));
2753 }
2754
2755 rc = pcie_set_mps(dev, mps);
2756 if (rc)
2757 pci_err(dev, "Failed attempting to set the MPS\n");
2758}
2759
2760static void pcie_write_mrrs(struct pci_dev *dev)
2761{
2762 int rc, mrrs;
2763
2764 /*
2765 * In the "safe" case, do not configure the MRRS. There appear to be
2766 * issues with setting MRRS to 0 on a number of devices.
2767 */
2768 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2769 return;
2770
2771 /*
2772 * For max performance, the MRRS must be set to the largest supported
2773 * value. However, it cannot be configured larger than the MPS the
2774 * device or the bus can support. This should already be properly
2775 * configured by a prior call to pcie_write_mps().
2776 */
2777 mrrs = pcie_get_mps(dev);
2778
2779 /*
2780 * MRRS is a R/W register. Invalid values can be written, but a
2781 * subsequent read will verify if the value is acceptable or not.
2782 * If the MRRS value provided is not acceptable (e.g., too large),
2783 * shrink the value until it is acceptable to the HW.
2784 */
2785 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2786 rc = pcie_set_readrq(dev, mrrs);
2787 if (!rc)
2788 break;
2789
2790 pci_warn(dev, "Failed attempting to set the MRRS\n");
2791 mrrs /= 2;
2792 }
2793
2794 if (mrrs < 128)
2795 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2796}
2797
2798static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2799{
2800 int mps, orig_mps;
2801
2802 if (!pci_is_pcie(dev))
2803 return 0;
2804
2805 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2806 pcie_bus_config == PCIE_BUS_DEFAULT)
2807 return 0;
2808
2809 mps = 128 << *(u8 *)data;
2810 orig_mps = pcie_get_mps(dev);
2811
2812 pcie_write_mps(dev, mps);
2813 pcie_write_mrrs(dev);
2814
2815 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2816 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2817 orig_mps, pcie_get_readrq(dev));
2818
2819 return 0;
2820}
2821
2822/*
2823 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2824 * parents then children fashion. If this changes, then this code will not
2825 * work as designed.
2826 */
2827void pcie_bus_configure_settings(struct pci_bus *bus)
2828{
2829 u8 smpss = 0;
2830
2831 if (!bus->self)
2832 return;
2833
2834 if (!pci_is_pcie(bus->self))
2835 return;
2836
2837 /*
2838 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2839 * to be aware of the MPS of the destination. To work around this,
2840 * simply force the MPS of the entire system to the smallest possible.
2841 */
2842 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2843 smpss = 0;
2844
2845 if (pcie_bus_config == PCIE_BUS_SAFE) {
2846 smpss = bus->self->pcie_mpss;
2847
2848 pcie_find_smpss(bus->self, &smpss);
2849 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2850 }
2851
2852 pcie_bus_configure_set(bus->self, &smpss);
2853 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2854}
2855EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2856
2857/*
2858 * Called after each bus is probed, but before its children are examined. This
2859 * is marked as __weak because multiple architectures define it.
2860 */
2861void __weak pcibios_fixup_bus(struct pci_bus *bus)
2862{
2863 /* nothing to do, expected to be removed in the future */
2864}
2865
2866/**
2867 * pci_scan_child_bus_extend() - Scan devices below a bus
2868 * @bus: Bus to scan for devices
2869 * @available_buses: Total number of buses available (%0 does not try to
2870 * extend beyond the minimal)
2871 *
2872 * Scans devices below @bus including subordinate buses. Returns new
2873 * subordinate number including all the found devices. Passing
2874 * @available_buses causes the remaining bus space to be distributed
2875 * equally between hotplug-capable bridges to allow future extension of the
2876 * hierarchy.
2877 */
2878static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2879 unsigned int available_buses)
2880{
2881 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2882 unsigned int start = bus->busn_res.start;
2883 unsigned int devfn, cmax, max = start;
2884 struct pci_dev *dev;
2885
2886 dev_dbg(&bus->dev, "scanning bus\n");
2887
2888 /* Go find them, Rover! */
2889 for (devfn = 0; devfn < 256; devfn += 8)
2890 pci_scan_slot(bus, devfn);
2891
2892 /* Reserve buses for SR-IOV capability */
2893 used_buses = pci_iov_bus_range(bus);
2894 max += used_buses;
2895
2896 /*
2897 * After performing arch-dependent fixup of the bus, look behind
2898 * all PCI-to-PCI bridges on this bus.
2899 */
2900 if (!bus->is_added) {
2901 dev_dbg(&bus->dev, "fixups for bus\n");
2902 pcibios_fixup_bus(bus);
2903 bus->is_added = 1;
2904 }
2905
2906 /*
2907 * Calculate how many hotplug bridges and normal bridges there
2908 * are on this bus. We will distribute the additional available
2909 * buses between hotplug bridges.
2910 */
2911 for_each_pci_bridge(dev, bus) {
2912 if (dev->is_hotplug_bridge)
2913 hotplug_bridges++;
2914 else
2915 normal_bridges++;
2916 }
2917
2918 /*
2919 * Scan bridges that are already configured. We don't touch them
2920 * unless they are misconfigured (which will be done in the second
2921 * scan below).
2922 */
2923 for_each_pci_bridge(dev, bus) {
2924 cmax = max;
2925 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2926
2927 /*
2928 * Reserve one bus for each bridge now to avoid extending
2929 * hotplug bridges too much during the second scan below.
2930 */
2931 used_buses++;
2932 if (max - cmax > 1)
2933 used_buses += max - cmax - 1;
2934 }
2935
2936 /* Scan bridges that need to be reconfigured */
2937 for_each_pci_bridge(dev, bus) {
2938 unsigned int buses = 0;
2939
2940 if (!hotplug_bridges && normal_bridges == 1) {
2941 /*
2942 * There is only one bridge on the bus (upstream
2943 * port) so it gets all available buses which it
2944 * can then distribute to the possible hotplug
2945 * bridges below.
2946 */
2947 buses = available_buses;
2948 } else if (dev->is_hotplug_bridge) {
2949 /*
2950 * Distribute the extra buses between hotplug
2951 * bridges if any.
2952 */
2953 buses = available_buses / hotplug_bridges;
2954 buses = min(buses, available_buses - used_buses + 1);
2955 }
2956
2957 cmax = max;
2958 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2959 /* One bus is already accounted so don't add it again */
2960 if (max - cmax > 1)
2961 used_buses += max - cmax - 1;
2962 }
2963
2964 /*
2965 * Make sure a hotplug bridge has at least the minimum requested
2966 * number of buses but allow it to grow up to the maximum available
2967 * bus number if there is room.
2968 */
2969 if (bus->self && bus->self->is_hotplug_bridge) {
2970 used_buses = max_t(unsigned int, available_buses,
2971 pci_hotplug_bus_size - 1);
2972 if (max - start < used_buses) {
2973 max = start + used_buses;
2974
2975 /* Do not allocate more buses than we have room left */
2976 if (max > bus->busn_res.end)
2977 max = bus->busn_res.end;
2978
2979 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2980 &bus->busn_res, max - start);
2981 }
2982 }
2983
2984 /*
2985 * We've scanned the bus and so we know all about what's on
2986 * the other side of any bridges that may be on this bus plus
2987 * any devices.
2988 *
2989 * Return how far we've got finding sub-buses.
2990 */
2991 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2992 return max;
2993}
2994
2995/**
2996 * pci_scan_child_bus() - Scan devices below a bus
2997 * @bus: Bus to scan for devices
2998 *
2999 * Scans devices below @bus including subordinate buses. Returns new
3000 * subordinate number including all the found devices.
3001 */
3002unsigned int pci_scan_child_bus(struct pci_bus *bus)
3003{
3004 return pci_scan_child_bus_extend(bus, 0);
3005}
3006EXPORT_SYMBOL_GPL(pci_scan_child_bus);
3007
3008/**
3009 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3010 * @bridge: Host bridge to set up
3011 *
3012 * Default empty implementation. Replace with an architecture-specific setup
3013 * routine, if necessary.
3014 */
3015int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
3016{
3017 return 0;
3018}
3019
3020void __weak pcibios_add_bus(struct pci_bus *bus)
3021{
3022}
3023
3024void __weak pcibios_remove_bus(struct pci_bus *bus)
3025{
3026}
3027
3028struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
3029 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3030{
3031 int error;
3032 struct pci_host_bridge *bridge;
3033
3034 bridge = pci_alloc_host_bridge(0);
3035 if (!bridge)
3036 return NULL;
3037
3038 bridge->dev.parent = parent;
3039
3040 list_splice_init(resources, &bridge->windows);
3041 bridge->sysdata = sysdata;
3042 bridge->busnr = bus;
3043 bridge->ops = ops;
3044
3045 error = pci_register_host_bridge(bridge);
3046 if (error < 0)
3047 goto err_out;
3048
3049 return bridge->bus;
3050
3051err_out:
3052 put_device(&bridge->dev);
3053 return NULL;
3054}
3055EXPORT_SYMBOL_GPL(pci_create_root_bus);
3056
3057int pci_host_probe(struct pci_host_bridge *bridge)
3058{
3059 struct pci_bus *bus, *child;
3060 int ret;
3061
3062 ret = pci_scan_root_bus_bridge(bridge);
3063 if (ret < 0) {
3064 dev_err(bridge->dev.parent, "Scanning root bridge failed");
3065 return ret;
3066 }
3067
3068 bus = bridge->bus;
3069
3070 /*
3071 * We insert PCI resources into the iomem_resource and
3072 * ioport_resource trees in either pci_bus_claim_resources()
3073 * or pci_bus_assign_resources().
3074 */
3075 if (pci_has_flag(PCI_PROBE_ONLY)) {
3076 pci_bus_claim_resources(bus);
3077 } else {
3078 pci_bus_size_bridges(bus);
3079 pci_bus_assign_resources(bus);
3080
3081 list_for_each_entry(child, &bus->children, node)
3082 pcie_bus_configure_settings(child);
3083 }
3084
3085 pci_bus_add_devices(bus);
3086 return 0;
3087}
3088EXPORT_SYMBOL_GPL(pci_host_probe);
3089
3090int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3091{
3092 struct resource *res = &b->busn_res;
3093 struct resource *parent_res, *conflict;
3094
3095 res->start = bus;
3096 res->end = bus_max;
3097 res->flags = IORESOURCE_BUS;
3098
3099 if (!pci_is_root_bus(b))
3100 parent_res = &b->parent->busn_res;
3101 else {
3102 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3103 res->flags |= IORESOURCE_PCI_FIXED;
3104 }
3105
3106 conflict = request_resource_conflict(parent_res, res);
3107
3108 if (conflict)
3109 dev_info(&b->dev,
3110 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3111 res, pci_is_root_bus(b) ? "domain " : "",
3112 parent_res, conflict->name, conflict);
3113
3114 return conflict == NULL;
3115}
3116
3117int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3118{
3119 struct resource *res = &b->busn_res;
3120 struct resource old_res = *res;
3121 resource_size_t size;
3122 int ret;
3123
3124 if (res->start > bus_max)
3125 return -EINVAL;
3126
3127 size = bus_max - res->start + 1;
3128 ret = adjust_resource(res, res->start, size);
3129 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3130 &old_res, ret ? "can not be" : "is", bus_max);
3131
3132 if (!ret && !res->parent)
3133 pci_bus_insert_busn_res(b, res->start, res->end);
3134
3135 return ret;
3136}
3137
3138void pci_bus_release_busn_res(struct pci_bus *b)
3139{
3140 struct resource *res = &b->busn_res;
3141 int ret;
3142
3143 if (!res->flags || !res->parent)
3144 return;
3145
3146 ret = release_resource(res);
3147 dev_info(&b->dev, "busn_res: %pR %s released\n",
3148 res, ret ? "can not be" : "is");
3149}
3150
3151int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3152{
3153 struct resource_entry *window;
3154 bool found = false;
3155 struct pci_bus *b;
3156 int max, bus, ret;
3157
3158 if (!bridge)
3159 return -EINVAL;
3160
3161 resource_list_for_each_entry(window, &bridge->windows)
3162 if (window->res->flags & IORESOURCE_BUS) {
3163 bridge->busnr = window->res->start;
3164 found = true;
3165 break;
3166 }
3167
3168 ret = pci_register_host_bridge(bridge);
3169 if (ret < 0)
3170 return ret;
3171
3172 b = bridge->bus;
3173 bus = bridge->busnr;
3174
3175 if (!found) {
3176 dev_info(&b->dev,
3177 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3178 bus);
3179 pci_bus_insert_busn_res(b, bus, 255);
3180 }
3181
3182 max = pci_scan_child_bus(b);
3183
3184 if (!found)
3185 pci_bus_update_busn_res_end(b, max);
3186
3187 return 0;
3188}
3189EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3190
3191struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3192 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3193{
3194 struct resource_entry *window;
3195 bool found = false;
3196 struct pci_bus *b;
3197 int max;
3198
3199 resource_list_for_each_entry(window, resources)
3200 if (window->res->flags & IORESOURCE_BUS) {
3201 found = true;
3202 break;
3203 }
3204
3205 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3206 if (!b)
3207 return NULL;
3208
3209 if (!found) {
3210 dev_info(&b->dev,
3211 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3212 bus);
3213 pci_bus_insert_busn_res(b, bus, 255);
3214 }
3215
3216 max = pci_scan_child_bus(b);
3217
3218 if (!found)
3219 pci_bus_update_busn_res_end(b, max);
3220
3221 return b;
3222}
3223EXPORT_SYMBOL(pci_scan_root_bus);
3224
3225struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3226 void *sysdata)
3227{
3228 LIST_HEAD(resources);
3229 struct pci_bus *b;
3230
3231 pci_add_resource(&resources, &ioport_resource);
3232 pci_add_resource(&resources, &iomem_resource);
3233 pci_add_resource(&resources, &busn_resource);
3234 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3235 if (b) {
3236 pci_scan_child_bus(b);
3237 } else {
3238 pci_free_resource_list(&resources);
3239 }
3240 return b;
3241}
3242EXPORT_SYMBOL(pci_scan_bus);
3243
3244/**
3245 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3246 * @bridge: PCI bridge for the bus to scan
3247 *
3248 * Scan a PCI bus and child buses for new devices, add them,
3249 * and enable them, resizing bridge mmio/io resource if necessary
3250 * and possible. The caller must ensure the child devices are already
3251 * removed for resizing to occur.
3252 *
3253 * Returns the max number of subordinate bus discovered.
3254 */
3255unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3256{
3257 unsigned int max;
3258 struct pci_bus *bus = bridge->subordinate;
3259
3260 max = pci_scan_child_bus(bus);
3261
3262 pci_assign_unassigned_bridge_resources(bridge);
3263
3264 pci_bus_add_devices(bus);
3265
3266 return max;
3267}
3268
3269/**
3270 * pci_rescan_bus - Scan a PCI bus for devices
3271 * @bus: PCI bus to scan
3272 *
3273 * Scan a PCI bus and child buses for new devices, add them,
3274 * and enable them.
3275 *
3276 * Returns the max number of subordinate bus discovered.
3277 */
3278unsigned int pci_rescan_bus(struct pci_bus *bus)
3279{
3280 unsigned int max;
3281
3282 max = pci_scan_child_bus(bus);
3283 pci_assign_unassigned_bus_resources(bus);
3284 pci_bus_add_devices(bus);
3285
3286 return max;
3287}
3288EXPORT_SYMBOL_GPL(pci_rescan_bus);
3289
3290/*
3291 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3292 * routines should always be executed under this mutex.
3293 */
3294static DEFINE_MUTEX(pci_rescan_remove_lock);
3295
3296void pci_lock_rescan_remove(void)
3297{
3298 mutex_lock(&pci_rescan_remove_lock);
3299}
3300EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3301
3302void pci_unlock_rescan_remove(void)
3303{
3304 mutex_unlock(&pci_rescan_remove_lock);
3305}
3306EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3307
3308static int __init pci_sort_bf_cmp(const struct device *d_a,
3309 const struct device *d_b)
3310{
3311 const struct pci_dev *a = to_pci_dev(d_a);
3312 const struct pci_dev *b = to_pci_dev(d_b);
3313
3314 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3315 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3316
3317 if (a->bus->number < b->bus->number) return -1;
3318 else if (a->bus->number > b->bus->number) return 1;
3319
3320 if (a->devfn < b->devfn) return -1;
3321 else if (a->devfn > b->devfn) return 1;
3322
3323 return 0;
3324}
3325
3326void __init pci_sort_breadthfirst(void)
3327{
3328 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3329}
3330
3331int pci_hp_add_bridge(struct pci_dev *dev)
3332{
3333 struct pci_bus *parent = dev->bus;
3334 int busnr, start = parent->busn_res.start;
3335 unsigned int available_buses = 0;
3336 int end = parent->busn_res.end;
3337
3338 for (busnr = start; busnr <= end; busnr++) {
3339 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3340 break;
3341 }
3342 if (busnr-- > end) {
3343 pci_err(dev, "No bus number available for hot-added bridge\n");
3344 return -1;
3345 }
3346
3347 /* Scan bridges that are already configured */
3348 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3349
3350 /*
3351 * Distribute the available bus numbers between hotplug-capable
3352 * bridges to make extending the chain later possible.
3353 */
3354 available_buses = end - busnr;
3355
3356 /* Scan bridges that need to be reconfigured */
3357 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3358
3359 if (!dev->subordinate)
3360 return -1;
3361
3362 return 0;
3363}
3364EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
1/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/of_device.h>
10#include <linux/of_pci.h>
11#include <linux/pci_hotplug.h>
12#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/cpumask.h>
15#include <linux/pci-aspm.h>
16#include <linux/aer.h>
17#include <linux/acpi.h>
18#include <linux/irqdomain.h>
19#include "pci.h"
20
21#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22#define CARDBUS_RESERVE_BUSNR 3
23
24static struct resource busn_resource = {
25 .name = "PCI busn",
26 .start = 0,
27 .end = 255,
28 .flags = IORESOURCE_BUS,
29};
30
31/* Ugh. Need to stop exporting this to modules. */
32LIST_HEAD(pci_root_buses);
33EXPORT_SYMBOL(pci_root_buses);
34
35static LIST_HEAD(pci_domain_busn_res_list);
36
37struct pci_domain_busn_res {
38 struct list_head list;
39 struct resource res;
40 int domain_nr;
41};
42
43static struct resource *get_pci_domain_busn_res(int domain_nr)
44{
45 struct pci_domain_busn_res *r;
46
47 list_for_each_entry(r, &pci_domain_busn_res_list, list)
48 if (r->domain_nr == domain_nr)
49 return &r->res;
50
51 r = kzalloc(sizeof(*r), GFP_KERNEL);
52 if (!r)
53 return NULL;
54
55 r->domain_nr = domain_nr;
56 r->res.start = 0;
57 r->res.end = 0xff;
58 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
59
60 list_add_tail(&r->list, &pci_domain_busn_res_list);
61
62 return &r->res;
63}
64
65static int find_anything(struct device *dev, void *data)
66{
67 return 1;
68}
69
70/*
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
73 * is no device to be found on the pci_bus_type.
74 */
75int no_pci_devices(void)
76{
77 struct device *dev;
78 int no_devices;
79
80 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
81 no_devices = (dev == NULL);
82 put_device(dev);
83 return no_devices;
84}
85EXPORT_SYMBOL(no_pci_devices);
86
87/*
88 * PCI Bus Class
89 */
90static void release_pcibus_dev(struct device *dev)
91{
92 struct pci_bus *pci_bus = to_pci_bus(dev);
93
94 put_device(pci_bus->bridge);
95 pci_bus_remove_resources(pci_bus);
96 pci_release_bus_of_node(pci_bus);
97 kfree(pci_bus);
98}
99
100static struct class pcibus_class = {
101 .name = "pci_bus",
102 .dev_release = &release_pcibus_dev,
103 .dev_groups = pcibus_groups,
104};
105
106static int __init pcibus_class_init(void)
107{
108 return class_register(&pcibus_class);
109}
110postcore_initcall(pcibus_class_init);
111
112static u64 pci_size(u64 base, u64 maxbase, u64 mask)
113{
114 u64 size = mask & maxbase; /* Find the significant bits */
115 if (!size)
116 return 0;
117
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size = (size & ~(size-1)) - 1;
121
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base == maxbase && ((base | size) & mask) != mask)
125 return 0;
126
127 return size;
128}
129
130static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
131{
132 u32 mem_type;
133 unsigned long flags;
134
135 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
137 flags |= IORESOURCE_IO;
138 return flags;
139 }
140
141 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
142 flags |= IORESOURCE_MEM;
143 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
144 flags |= IORESOURCE_PREFETCH;
145
146 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
147 switch (mem_type) {
148 case PCI_BASE_ADDRESS_MEM_TYPE_32:
149 break;
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
151 /* 1M mem BAR treated as 32-bit BAR */
152 break;
153 case PCI_BASE_ADDRESS_MEM_TYPE_64:
154 flags |= IORESOURCE_MEM_64;
155 break;
156 default:
157 /* mem unknown type treated as 32-bit BAR */
158 break;
159 }
160 return flags;
161}
162
163#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
164
165/**
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
171 *
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
173 */
174int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
175 struct resource *res, unsigned int pos)
176{
177 u32 l, sz, mask;
178 u64 l64, sz64, mask64;
179 u16 orig_cmd;
180 struct pci_bus_region region, inverted_region;
181
182 if (dev->non_compliant_bars)
183 return 0;
184
185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
186
187 /* No printks while decoding is disabled! */
188 if (!dev->mmio_always_on) {
189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
191 pci_write_config_word(dev, PCI_COMMAND,
192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
193 }
194 }
195
196 res->name = pci_name(dev);
197
198 pci_read_config_dword(dev, pos, &l);
199 pci_write_config_dword(dev, pos, l | mask);
200 pci_read_config_dword(dev, pos, &sz);
201 pci_write_config_dword(dev, pos, l);
202
203 /*
204 * All bits set in sz means the device isn't working properly.
205 * If the BAR isn't implemented, all bits must be 0. If it's a
206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 * 1 must be clear.
208 */
209 if (sz == 0xffffffff)
210 sz = 0;
211
212 /*
213 * I don't know how l can have all bits set. Copied from old code.
214 * Maybe it fixes a bug on some ancient platform.
215 */
216 if (l == 0xffffffff)
217 l = 0;
218
219 if (type == pci_bar_unknown) {
220 res->flags = decode_bar(dev, l);
221 res->flags |= IORESOURCE_SIZEALIGN;
222 if (res->flags & IORESOURCE_IO) {
223 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
226 } else {
227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 }
231 } else {
232 res->flags |= (l & IORESOURCE_ROM_ENABLE);
233 l64 = l & PCI_ROM_ADDRESS_MASK;
234 sz64 = sz & PCI_ROM_ADDRESS_MASK;
235 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
236 }
237
238 if (res->flags & IORESOURCE_MEM_64) {
239 pci_read_config_dword(dev, pos + 4, &l);
240 pci_write_config_dword(dev, pos + 4, ~0);
241 pci_read_config_dword(dev, pos + 4, &sz);
242 pci_write_config_dword(dev, pos + 4, l);
243
244 l64 |= ((u64)l << 32);
245 sz64 |= ((u64)sz << 32);
246 mask64 |= ((u64)~0 << 32);
247 }
248
249 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
250 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
251
252 if (!sz64)
253 goto fail;
254
255 sz64 = pci_size(l64, sz64, mask64);
256 if (!sz64) {
257 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
258 pos);
259 goto fail;
260 }
261
262 if (res->flags & IORESOURCE_MEM_64) {
263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
264 && sz64 > 0x100000000ULL) {
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266 res->start = 0;
267 res->end = 0;
268 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
269 pos, (unsigned long long)sz64);
270 goto out;
271 }
272
273 if ((sizeof(pci_bus_addr_t) < 8) && l) {
274 /* Above 32-bit boundary; try to reallocate */
275 res->flags |= IORESOURCE_UNSET;
276 res->start = 0;
277 res->end = sz64;
278 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
279 pos, (unsigned long long)l64);
280 goto out;
281 }
282 }
283
284 region.start = l64;
285 region.end = l64 + sz64;
286
287 pcibios_bus_to_resource(dev->bus, res, ®ion);
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
289
290 /*
291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
292 * the corresponding resource address (the physical address used by
293 * the CPU. Converting that resource address back to a bus address
294 * should yield the original BAR value:
295 *
296 * resource_to_bus(bus_to_resource(A)) == A
297 *
298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
299 * be claimed by the device.
300 */
301 if (inverted_region.start != region.start) {
302 res->flags |= IORESOURCE_UNSET;
303 res->start = 0;
304 res->end = region.end - region.start;
305 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
306 pos, (unsigned long long)region.start);
307 }
308
309 goto out;
310
311
312fail:
313 res->flags = 0;
314out:
315 if (res->flags)
316 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
317
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
319}
320
321static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
322{
323 unsigned int pos, reg;
324
325 for (pos = 0; pos < howmany; pos++) {
326 struct resource *res = &dev->resource[pos];
327 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
328 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
329 }
330
331 if (rom) {
332 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
333 dev->rom_base_reg = rom;
334 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
335 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
336 __pci_read_base(dev, pci_bar_mem32, res, rom);
337 }
338}
339
340static void pci_read_bridge_io(struct pci_bus *child)
341{
342 struct pci_dev *dev = child->self;
343 u8 io_base_lo, io_limit_lo;
344 unsigned long io_mask, io_granularity, base, limit;
345 struct pci_bus_region region;
346 struct resource *res;
347
348 io_mask = PCI_IO_RANGE_MASK;
349 io_granularity = 0x1000;
350 if (dev->io_window_1k) {
351 /* Support 1K I/O space granularity */
352 io_mask = PCI_IO_1K_RANGE_MASK;
353 io_granularity = 0x400;
354 }
355
356 res = child->resource[0];
357 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
358 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
359 base = (io_base_lo & io_mask) << 8;
360 limit = (io_limit_lo & io_mask) << 8;
361
362 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
363 u16 io_base_hi, io_limit_hi;
364
365 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
366 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
367 base |= ((unsigned long) io_base_hi << 16);
368 limit |= ((unsigned long) io_limit_hi << 16);
369 }
370
371 if (base <= limit) {
372 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
373 region.start = base;
374 region.end = limit + io_granularity - 1;
375 pcibios_bus_to_resource(dev->bus, res, ®ion);
376 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
377 }
378}
379
380static void pci_read_bridge_mmio(struct pci_bus *child)
381{
382 struct pci_dev *dev = child->self;
383 u16 mem_base_lo, mem_limit_lo;
384 unsigned long base, limit;
385 struct pci_bus_region region;
386 struct resource *res;
387
388 res = child->resource[1];
389 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
390 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
391 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
392 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
393 if (base <= limit) {
394 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
395 region.start = base;
396 region.end = limit + 0xfffff;
397 pcibios_bus_to_resource(dev->bus, res, ®ion);
398 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
399 }
400}
401
402static void pci_read_bridge_mmio_pref(struct pci_bus *child)
403{
404 struct pci_dev *dev = child->self;
405 u16 mem_base_lo, mem_limit_lo;
406 u64 base64, limit64;
407 pci_bus_addr_t base, limit;
408 struct pci_bus_region region;
409 struct resource *res;
410
411 res = child->resource[2];
412 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
413 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
414 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
415 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
416
417 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
418 u32 mem_base_hi, mem_limit_hi;
419
420 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
421 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
422
423 /*
424 * Some bridges set the base > limit by default, and some
425 * (broken) BIOSes do not initialize them. If we find
426 * this, just assume they are not being used.
427 */
428 if (mem_base_hi <= mem_limit_hi) {
429 base64 |= (u64) mem_base_hi << 32;
430 limit64 |= (u64) mem_limit_hi << 32;
431 }
432 }
433
434 base = (pci_bus_addr_t) base64;
435 limit = (pci_bus_addr_t) limit64;
436
437 if (base != base64) {
438 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
439 (unsigned long long) base64);
440 return;
441 }
442
443 if (base <= limit) {
444 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
445 IORESOURCE_MEM | IORESOURCE_PREFETCH;
446 if (res->flags & PCI_PREF_RANGE_TYPE_64)
447 res->flags |= IORESOURCE_MEM_64;
448 region.start = base;
449 region.end = limit + 0xfffff;
450 pcibios_bus_to_resource(dev->bus, res, ®ion);
451 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
452 }
453}
454
455void pci_read_bridge_bases(struct pci_bus *child)
456{
457 struct pci_dev *dev = child->self;
458 struct resource *res;
459 int i;
460
461 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
462 return;
463
464 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
465 &child->busn_res,
466 dev->transparent ? " (subtractive decode)" : "");
467
468 pci_bus_remove_resources(child);
469 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
470 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
471
472 pci_read_bridge_io(child);
473 pci_read_bridge_mmio(child);
474 pci_read_bridge_mmio_pref(child);
475
476 if (dev->transparent) {
477 pci_bus_for_each_resource(child->parent, res, i) {
478 if (res && res->flags) {
479 pci_bus_add_resource(child, res,
480 PCI_SUBTRACTIVE_DECODE);
481 dev_printk(KERN_DEBUG, &dev->dev,
482 " bridge window %pR (subtractive decode)\n",
483 res);
484 }
485 }
486 }
487}
488
489static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
490{
491 struct pci_bus *b;
492
493 b = kzalloc(sizeof(*b), GFP_KERNEL);
494 if (!b)
495 return NULL;
496
497 INIT_LIST_HEAD(&b->node);
498 INIT_LIST_HEAD(&b->children);
499 INIT_LIST_HEAD(&b->devices);
500 INIT_LIST_HEAD(&b->slots);
501 INIT_LIST_HEAD(&b->resources);
502 b->max_bus_speed = PCI_SPEED_UNKNOWN;
503 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
504#ifdef CONFIG_PCI_DOMAINS_GENERIC
505 if (parent)
506 b->domain_nr = parent->domain_nr;
507#endif
508 return b;
509}
510
511static void pci_release_host_bridge_dev(struct device *dev)
512{
513 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
514
515 if (bridge->release_fn)
516 bridge->release_fn(bridge);
517
518 pci_free_resource_list(&bridge->windows);
519
520 kfree(bridge);
521}
522
523static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
524{
525 struct pci_host_bridge *bridge;
526
527 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
528 if (!bridge)
529 return NULL;
530
531 INIT_LIST_HEAD(&bridge->windows);
532 bridge->bus = b;
533 return bridge;
534}
535
536static const unsigned char pcix_bus_speed[] = {
537 PCI_SPEED_UNKNOWN, /* 0 */
538 PCI_SPEED_66MHz_PCIX, /* 1 */
539 PCI_SPEED_100MHz_PCIX, /* 2 */
540 PCI_SPEED_133MHz_PCIX, /* 3 */
541 PCI_SPEED_UNKNOWN, /* 4 */
542 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
543 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
544 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
545 PCI_SPEED_UNKNOWN, /* 8 */
546 PCI_SPEED_66MHz_PCIX_266, /* 9 */
547 PCI_SPEED_100MHz_PCIX_266, /* A */
548 PCI_SPEED_133MHz_PCIX_266, /* B */
549 PCI_SPEED_UNKNOWN, /* C */
550 PCI_SPEED_66MHz_PCIX_533, /* D */
551 PCI_SPEED_100MHz_PCIX_533, /* E */
552 PCI_SPEED_133MHz_PCIX_533 /* F */
553};
554
555const unsigned char pcie_link_speed[] = {
556 PCI_SPEED_UNKNOWN, /* 0 */
557 PCIE_SPEED_2_5GT, /* 1 */
558 PCIE_SPEED_5_0GT, /* 2 */
559 PCIE_SPEED_8_0GT, /* 3 */
560 PCI_SPEED_UNKNOWN, /* 4 */
561 PCI_SPEED_UNKNOWN, /* 5 */
562 PCI_SPEED_UNKNOWN, /* 6 */
563 PCI_SPEED_UNKNOWN, /* 7 */
564 PCI_SPEED_UNKNOWN, /* 8 */
565 PCI_SPEED_UNKNOWN, /* 9 */
566 PCI_SPEED_UNKNOWN, /* A */
567 PCI_SPEED_UNKNOWN, /* B */
568 PCI_SPEED_UNKNOWN, /* C */
569 PCI_SPEED_UNKNOWN, /* D */
570 PCI_SPEED_UNKNOWN, /* E */
571 PCI_SPEED_UNKNOWN /* F */
572};
573
574void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
575{
576 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
577}
578EXPORT_SYMBOL_GPL(pcie_update_link_speed);
579
580static unsigned char agp_speeds[] = {
581 AGP_UNKNOWN,
582 AGP_1X,
583 AGP_2X,
584 AGP_4X,
585 AGP_8X
586};
587
588static enum pci_bus_speed agp_speed(int agp3, int agpstat)
589{
590 int index = 0;
591
592 if (agpstat & 4)
593 index = 3;
594 else if (agpstat & 2)
595 index = 2;
596 else if (agpstat & 1)
597 index = 1;
598 else
599 goto out;
600
601 if (agp3) {
602 index += 2;
603 if (index == 5)
604 index = 0;
605 }
606
607 out:
608 return agp_speeds[index];
609}
610
611static void pci_set_bus_speed(struct pci_bus *bus)
612{
613 struct pci_dev *bridge = bus->self;
614 int pos;
615
616 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
617 if (!pos)
618 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
619 if (pos) {
620 u32 agpstat, agpcmd;
621
622 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
623 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
624
625 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
626 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
627 }
628
629 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
630 if (pos) {
631 u16 status;
632 enum pci_bus_speed max;
633
634 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
635 &status);
636
637 if (status & PCI_X_SSTATUS_533MHZ) {
638 max = PCI_SPEED_133MHz_PCIX_533;
639 } else if (status & PCI_X_SSTATUS_266MHZ) {
640 max = PCI_SPEED_133MHz_PCIX_266;
641 } else if (status & PCI_X_SSTATUS_133MHZ) {
642 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
643 max = PCI_SPEED_133MHz_PCIX_ECC;
644 else
645 max = PCI_SPEED_133MHz_PCIX;
646 } else {
647 max = PCI_SPEED_66MHz_PCIX;
648 }
649
650 bus->max_bus_speed = max;
651 bus->cur_bus_speed = pcix_bus_speed[
652 (status & PCI_X_SSTATUS_FREQ) >> 6];
653
654 return;
655 }
656
657 if (pci_is_pcie(bridge)) {
658 u32 linkcap;
659 u16 linksta;
660
661 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
662 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
663
664 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
665 pcie_update_link_speed(bus, linksta);
666 }
667}
668
669static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
670{
671 struct irq_domain *d;
672
673 /*
674 * Any firmware interface that can resolve the msi_domain
675 * should be called from here.
676 */
677 d = pci_host_bridge_of_msi_domain(bus);
678 if (!d)
679 d = pci_host_bridge_acpi_msi_domain(bus);
680
681#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
682 /*
683 * If no IRQ domain was found via the OF tree, try looking it up
684 * directly through the fwnode_handle.
685 */
686 if (!d) {
687 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
688
689 if (fwnode)
690 d = irq_find_matching_fwnode(fwnode,
691 DOMAIN_BUS_PCI_MSI);
692 }
693#endif
694
695 return d;
696}
697
698static void pci_set_bus_msi_domain(struct pci_bus *bus)
699{
700 struct irq_domain *d;
701 struct pci_bus *b;
702
703 /*
704 * The bus can be a root bus, a subordinate bus, or a virtual bus
705 * created by an SR-IOV device. Walk up to the first bridge device
706 * found or derive the domain from the host bridge.
707 */
708 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
709 if (b->self)
710 d = dev_get_msi_domain(&b->self->dev);
711 }
712
713 if (!d)
714 d = pci_host_bridge_msi_domain(b);
715
716 dev_set_msi_domain(&bus->dev, d);
717}
718
719static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
720 struct pci_dev *bridge, int busnr)
721{
722 struct pci_bus *child;
723 int i;
724 int ret;
725
726 /*
727 * Allocate a new bus, and inherit stuff from the parent..
728 */
729 child = pci_alloc_bus(parent);
730 if (!child)
731 return NULL;
732
733 child->parent = parent;
734 child->ops = parent->ops;
735 child->msi = parent->msi;
736 child->sysdata = parent->sysdata;
737 child->bus_flags = parent->bus_flags;
738
739 /* initialize some portions of the bus device, but don't register it
740 * now as the parent is not properly set up yet.
741 */
742 child->dev.class = &pcibus_class;
743 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
744
745 /*
746 * Set up the primary, secondary and subordinate
747 * bus numbers.
748 */
749 child->number = child->busn_res.start = busnr;
750 child->primary = parent->busn_res.start;
751 child->busn_res.end = 0xff;
752
753 if (!bridge) {
754 child->dev.parent = parent->bridge;
755 goto add_dev;
756 }
757
758 child->self = bridge;
759 child->bridge = get_device(&bridge->dev);
760 child->dev.parent = child->bridge;
761 pci_set_bus_of_node(child);
762 pci_set_bus_speed(child);
763
764 /* Set up default resource pointers and names.. */
765 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
766 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
767 child->resource[i]->name = child->name;
768 }
769 bridge->subordinate = child;
770
771add_dev:
772 pci_set_bus_msi_domain(child);
773 ret = device_register(&child->dev);
774 WARN_ON(ret < 0);
775
776 pcibios_add_bus(child);
777
778 if (child->ops->add_bus) {
779 ret = child->ops->add_bus(child);
780 if (WARN_ON(ret < 0))
781 dev_err(&child->dev, "failed to add bus: %d\n", ret);
782 }
783
784 /* Create legacy_io and legacy_mem files for this bus */
785 pci_create_legacy_files(child);
786
787 return child;
788}
789
790struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
791 int busnr)
792{
793 struct pci_bus *child;
794
795 child = pci_alloc_child_bus(parent, dev, busnr);
796 if (child) {
797 down_write(&pci_bus_sem);
798 list_add_tail(&child->node, &parent->children);
799 up_write(&pci_bus_sem);
800 }
801 return child;
802}
803EXPORT_SYMBOL(pci_add_new_bus);
804
805static void pci_enable_crs(struct pci_dev *pdev)
806{
807 u16 root_cap = 0;
808
809 /* Enable CRS Software Visibility if supported */
810 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
811 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
812 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
813 PCI_EXP_RTCTL_CRSSVE);
814}
815
816/*
817 * If it's a bridge, configure it and scan the bus behind it.
818 * For CardBus bridges, we don't scan behind as the devices will
819 * be handled by the bridge driver itself.
820 *
821 * We need to process bridges in two passes -- first we scan those
822 * already configured by the BIOS and after we are done with all of
823 * them, we proceed to assigning numbers to the remaining buses in
824 * order to avoid overlaps between old and new bus numbers.
825 */
826int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
827{
828 struct pci_bus *child;
829 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
830 u32 buses, i, j = 0;
831 u16 bctl;
832 u8 primary, secondary, subordinate;
833 int broken = 0;
834
835 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
836 primary = buses & 0xFF;
837 secondary = (buses >> 8) & 0xFF;
838 subordinate = (buses >> 16) & 0xFF;
839
840 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
841 secondary, subordinate, pass);
842
843 if (!primary && (primary != bus->number) && secondary && subordinate) {
844 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
845 primary = bus->number;
846 }
847
848 /* Check if setup is sensible at all */
849 if (!pass &&
850 (primary != bus->number || secondary <= bus->number ||
851 secondary > subordinate)) {
852 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
853 secondary, subordinate);
854 broken = 1;
855 }
856
857 /* Disable MasterAbortMode during probing to avoid reporting
858 of bus errors (in some architectures) */
859 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
860 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
861 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
862
863 pci_enable_crs(dev);
864
865 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
866 !is_cardbus && !broken) {
867 unsigned int cmax;
868 /*
869 * Bus already configured by firmware, process it in the first
870 * pass and just note the configuration.
871 */
872 if (pass)
873 goto out;
874
875 /*
876 * The bus might already exist for two reasons: Either we are
877 * rescanning the bus or the bus is reachable through more than
878 * one bridge. The second case can happen with the i450NX
879 * chipset.
880 */
881 child = pci_find_bus(pci_domain_nr(bus), secondary);
882 if (!child) {
883 child = pci_add_new_bus(bus, dev, secondary);
884 if (!child)
885 goto out;
886 child->primary = primary;
887 pci_bus_insert_busn_res(child, secondary, subordinate);
888 child->bridge_ctl = bctl;
889 }
890
891 cmax = pci_scan_child_bus(child);
892 if (cmax > subordinate)
893 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
894 subordinate, cmax);
895 /* subordinate should equal child->busn_res.end */
896 if (subordinate > max)
897 max = subordinate;
898 } else {
899 /*
900 * We need to assign a number to this bus which we always
901 * do in the second pass.
902 */
903 if (!pass) {
904 if (pcibios_assign_all_busses() || broken || is_cardbus)
905 /* Temporarily disable forwarding of the
906 configuration cycles on all bridges in
907 this bus segment to avoid possible
908 conflicts in the second pass between two
909 bridges programmed with overlapping
910 bus ranges. */
911 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
912 buses & ~0xffffff);
913 goto out;
914 }
915
916 /* Clear errors */
917 pci_write_config_word(dev, PCI_STATUS, 0xffff);
918
919 /* Prevent assigning a bus number that already exists.
920 * This can happen when a bridge is hot-plugged, so in
921 * this case we only re-scan this bus. */
922 child = pci_find_bus(pci_domain_nr(bus), max+1);
923 if (!child) {
924 child = pci_add_new_bus(bus, dev, max+1);
925 if (!child)
926 goto out;
927 pci_bus_insert_busn_res(child, max+1, 0xff);
928 }
929 max++;
930 buses = (buses & 0xff000000)
931 | ((unsigned int)(child->primary) << 0)
932 | ((unsigned int)(child->busn_res.start) << 8)
933 | ((unsigned int)(child->busn_res.end) << 16);
934
935 /*
936 * yenta.c forces a secondary latency timer of 176.
937 * Copy that behaviour here.
938 */
939 if (is_cardbus) {
940 buses &= ~0xff000000;
941 buses |= CARDBUS_LATENCY_TIMER << 24;
942 }
943
944 /*
945 * We need to blast all three values with a single write.
946 */
947 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
948
949 if (!is_cardbus) {
950 child->bridge_ctl = bctl;
951 max = pci_scan_child_bus(child);
952 } else {
953 /*
954 * For CardBus bridges, we leave 4 bus numbers
955 * as cards with a PCI-to-PCI bridge can be
956 * inserted later.
957 */
958 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
959 struct pci_bus *parent = bus;
960 if (pci_find_bus(pci_domain_nr(bus),
961 max+i+1))
962 break;
963 while (parent->parent) {
964 if ((!pcibios_assign_all_busses()) &&
965 (parent->busn_res.end > max) &&
966 (parent->busn_res.end <= max+i)) {
967 j = 1;
968 }
969 parent = parent->parent;
970 }
971 if (j) {
972 /*
973 * Often, there are two cardbus bridges
974 * -- try to leave one valid bus number
975 * for each one.
976 */
977 i /= 2;
978 break;
979 }
980 }
981 max += i;
982 }
983 /*
984 * Set the subordinate bus number to its real value.
985 */
986 pci_bus_update_busn_res_end(child, max);
987 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
988 }
989
990 sprintf(child->name,
991 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
992 pci_domain_nr(bus), child->number);
993
994 /* Has only triggered on CardBus, fixup is in yenta_socket */
995 while (bus->parent) {
996 if ((child->busn_res.end > bus->busn_res.end) ||
997 (child->number > bus->busn_res.end) ||
998 (child->number < bus->number) ||
999 (child->busn_res.end < bus->number)) {
1000 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1001 &child->busn_res,
1002 (bus->number > child->busn_res.end &&
1003 bus->busn_res.end < child->number) ?
1004 "wholly" : "partially",
1005 bus->self->transparent ? " transparent" : "",
1006 dev_name(&bus->dev),
1007 &bus->busn_res);
1008 }
1009 bus = bus->parent;
1010 }
1011
1012out:
1013 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1014
1015 return max;
1016}
1017EXPORT_SYMBOL(pci_scan_bridge);
1018
1019/*
1020 * Read interrupt line and base address registers.
1021 * The architecture-dependent code can tweak these, of course.
1022 */
1023static void pci_read_irq(struct pci_dev *dev)
1024{
1025 unsigned char irq;
1026
1027 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1028 dev->pin = irq;
1029 if (irq)
1030 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1031 dev->irq = irq;
1032}
1033
1034void set_pcie_port_type(struct pci_dev *pdev)
1035{
1036 int pos;
1037 u16 reg16;
1038 int type;
1039 struct pci_dev *parent;
1040
1041 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1042 if (!pos)
1043 return;
1044 pdev->pcie_cap = pos;
1045 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1046 pdev->pcie_flags_reg = reg16;
1047 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1048 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1049
1050 /*
1051 * A Root Port is always the upstream end of a Link. No PCIe
1052 * component has two Links. Two Links are connected by a Switch
1053 * that has a Port on each Link and internal logic to connect the
1054 * two Ports.
1055 */
1056 type = pci_pcie_type(pdev);
1057 if (type == PCI_EXP_TYPE_ROOT_PORT)
1058 pdev->has_secondary_link = 1;
1059 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1060 type == PCI_EXP_TYPE_DOWNSTREAM) {
1061 parent = pci_upstream_bridge(pdev);
1062
1063 /*
1064 * Usually there's an upstream device (Root Port or Switch
1065 * Downstream Port), but we can't assume one exists.
1066 */
1067 if (parent && !parent->has_secondary_link)
1068 pdev->has_secondary_link = 1;
1069 }
1070}
1071
1072void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1073{
1074 u32 reg32;
1075
1076 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1077 if (reg32 & PCI_EXP_SLTCAP_HPC)
1078 pdev->is_hotplug_bridge = 1;
1079}
1080
1081/**
1082 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1083 * @dev: PCI device
1084 *
1085 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1086 * when forwarding a type1 configuration request the bridge must check that
1087 * the extended register address field is zero. The bridge is not permitted
1088 * to forward the transactions and must handle it as an Unsupported Request.
1089 * Some bridges do not follow this rule and simply drop the extended register
1090 * bits, resulting in the standard config space being aliased, every 256
1091 * bytes across the entire configuration space. Test for this condition by
1092 * comparing the first dword of each potential alias to the vendor/device ID.
1093 * Known offenders:
1094 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1095 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1096 */
1097static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1098{
1099#ifdef CONFIG_PCI_QUIRKS
1100 int pos;
1101 u32 header, tmp;
1102
1103 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1104
1105 for (pos = PCI_CFG_SPACE_SIZE;
1106 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1107 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1108 || header != tmp)
1109 return false;
1110 }
1111
1112 return true;
1113#else
1114 return false;
1115#endif
1116}
1117
1118/**
1119 * pci_cfg_space_size - get the configuration space size of the PCI device.
1120 * @dev: PCI device
1121 *
1122 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1123 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1124 * access it. Maybe we don't have a way to generate extended config space
1125 * accesses, or the device is behind a reverse Express bridge. So we try
1126 * reading the dword at 0x100 which must either be 0 or a valid extended
1127 * capability header.
1128 */
1129static int pci_cfg_space_size_ext(struct pci_dev *dev)
1130{
1131 u32 status;
1132 int pos = PCI_CFG_SPACE_SIZE;
1133
1134 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1135 return PCI_CFG_SPACE_SIZE;
1136 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1137 return PCI_CFG_SPACE_SIZE;
1138
1139 return PCI_CFG_SPACE_EXP_SIZE;
1140}
1141
1142int pci_cfg_space_size(struct pci_dev *dev)
1143{
1144 int pos;
1145 u32 status;
1146 u16 class;
1147
1148 class = dev->class >> 8;
1149 if (class == PCI_CLASS_BRIDGE_HOST)
1150 return pci_cfg_space_size_ext(dev);
1151
1152 if (pci_is_pcie(dev))
1153 return pci_cfg_space_size_ext(dev);
1154
1155 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1156 if (!pos)
1157 return PCI_CFG_SPACE_SIZE;
1158
1159 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1160 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1161 return pci_cfg_space_size_ext(dev);
1162
1163 return PCI_CFG_SPACE_SIZE;
1164}
1165
1166#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1167
1168static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1169{
1170 /*
1171 * Disable the MSI hardware to avoid screaming interrupts
1172 * during boot. This is the power on reset default so
1173 * usually this should be a noop.
1174 */
1175 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1176 if (dev->msi_cap)
1177 pci_msi_set_enable(dev, 0);
1178
1179 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1180 if (dev->msix_cap)
1181 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1182}
1183
1184/**
1185 * pci_setup_device - fill in class and map information of a device
1186 * @dev: the device structure to fill
1187 *
1188 * Initialize the device structure with information about the device's
1189 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1190 * Called at initialisation of the PCI subsystem and by CardBus services.
1191 * Returns 0 on success and negative if unknown type of device (not normal,
1192 * bridge or CardBus).
1193 */
1194int pci_setup_device(struct pci_dev *dev)
1195{
1196 u32 class;
1197 u16 cmd;
1198 u8 hdr_type;
1199 int pos = 0;
1200 struct pci_bus_region region;
1201 struct resource *res;
1202
1203 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1204 return -EIO;
1205
1206 dev->sysdata = dev->bus->sysdata;
1207 dev->dev.parent = dev->bus->bridge;
1208 dev->dev.bus = &pci_bus_type;
1209 dev->hdr_type = hdr_type & 0x7f;
1210 dev->multifunction = !!(hdr_type & 0x80);
1211 dev->error_state = pci_channel_io_normal;
1212 set_pcie_port_type(dev);
1213
1214 pci_dev_assign_slot(dev);
1215 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1216 set this higher, assuming the system even supports it. */
1217 dev->dma_mask = 0xffffffff;
1218
1219 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1220 dev->bus->number, PCI_SLOT(dev->devfn),
1221 PCI_FUNC(dev->devfn));
1222
1223 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1224 dev->revision = class & 0xff;
1225 dev->class = class >> 8; /* upper 3 bytes */
1226
1227 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1228 dev->vendor, dev->device, dev->hdr_type, dev->class);
1229
1230 /* need to have dev->class ready */
1231 dev->cfg_size = pci_cfg_space_size(dev);
1232
1233 /* "Unknown power state" */
1234 dev->current_state = PCI_UNKNOWN;
1235
1236 /* Early fixups, before probing the BARs */
1237 pci_fixup_device(pci_fixup_early, dev);
1238 /* device class may be changed after fixup */
1239 class = dev->class >> 8;
1240
1241 if (dev->non_compliant_bars) {
1242 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1243 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1244 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1245 cmd &= ~PCI_COMMAND_IO;
1246 cmd &= ~PCI_COMMAND_MEMORY;
1247 pci_write_config_word(dev, PCI_COMMAND, cmd);
1248 }
1249 }
1250
1251 switch (dev->hdr_type) { /* header type */
1252 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1253 if (class == PCI_CLASS_BRIDGE_PCI)
1254 goto bad;
1255 pci_read_irq(dev);
1256 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1257 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1258 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1259
1260 /*
1261 * Do the ugly legacy mode stuff here rather than broken chip
1262 * quirk code. Legacy mode ATA controllers have fixed
1263 * addresses. These are not always echoed in BAR0-3, and
1264 * BAR0-3 in a few cases contain junk!
1265 */
1266 if (class == PCI_CLASS_STORAGE_IDE) {
1267 u8 progif;
1268 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1269 if ((progif & 1) == 0) {
1270 region.start = 0x1F0;
1271 region.end = 0x1F7;
1272 res = &dev->resource[0];
1273 res->flags = LEGACY_IO_RESOURCE;
1274 pcibios_bus_to_resource(dev->bus, res, ®ion);
1275 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1276 res);
1277 region.start = 0x3F6;
1278 region.end = 0x3F6;
1279 res = &dev->resource[1];
1280 res->flags = LEGACY_IO_RESOURCE;
1281 pcibios_bus_to_resource(dev->bus, res, ®ion);
1282 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1283 res);
1284 }
1285 if ((progif & 4) == 0) {
1286 region.start = 0x170;
1287 region.end = 0x177;
1288 res = &dev->resource[2];
1289 res->flags = LEGACY_IO_RESOURCE;
1290 pcibios_bus_to_resource(dev->bus, res, ®ion);
1291 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1292 res);
1293 region.start = 0x376;
1294 region.end = 0x376;
1295 res = &dev->resource[3];
1296 res->flags = LEGACY_IO_RESOURCE;
1297 pcibios_bus_to_resource(dev->bus, res, ®ion);
1298 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1299 res);
1300 }
1301 }
1302 break;
1303
1304 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1305 if (class != PCI_CLASS_BRIDGE_PCI)
1306 goto bad;
1307 /* The PCI-to-PCI bridge spec requires that subtractive
1308 decoding (i.e. transparent) bridge must have programming
1309 interface code of 0x01. */
1310 pci_read_irq(dev);
1311 dev->transparent = ((dev->class & 0xff) == 1);
1312 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1313 set_pcie_hotplug_bridge(dev);
1314 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1315 if (pos) {
1316 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1317 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1318 }
1319 break;
1320
1321 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1322 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1323 goto bad;
1324 pci_read_irq(dev);
1325 pci_read_bases(dev, 1, 0);
1326 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1327 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1328 break;
1329
1330 default: /* unknown header */
1331 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1332 dev->hdr_type);
1333 return -EIO;
1334
1335 bad:
1336 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1337 dev->class, dev->hdr_type);
1338 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1339 }
1340
1341 /* We found a fine healthy device, go go go... */
1342 return 0;
1343}
1344
1345static void pci_configure_mps(struct pci_dev *dev)
1346{
1347 struct pci_dev *bridge = pci_upstream_bridge(dev);
1348 int mps, p_mps, rc;
1349
1350 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1351 return;
1352
1353 mps = pcie_get_mps(dev);
1354 p_mps = pcie_get_mps(bridge);
1355
1356 if (mps == p_mps)
1357 return;
1358
1359 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1360 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1361 mps, pci_name(bridge), p_mps);
1362 return;
1363 }
1364
1365 /*
1366 * Fancier MPS configuration is done later by
1367 * pcie_bus_configure_settings()
1368 */
1369 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1370 return;
1371
1372 rc = pcie_set_mps(dev, p_mps);
1373 if (rc) {
1374 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1375 p_mps);
1376 return;
1377 }
1378
1379 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1380 p_mps, mps, 128 << dev->pcie_mpss);
1381}
1382
1383static struct hpp_type0 pci_default_type0 = {
1384 .revision = 1,
1385 .cache_line_size = 8,
1386 .latency_timer = 0x40,
1387 .enable_serr = 0,
1388 .enable_perr = 0,
1389};
1390
1391static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1392{
1393 u16 pci_cmd, pci_bctl;
1394
1395 if (!hpp)
1396 hpp = &pci_default_type0;
1397
1398 if (hpp->revision > 1) {
1399 dev_warn(&dev->dev,
1400 "PCI settings rev %d not supported; using defaults\n",
1401 hpp->revision);
1402 hpp = &pci_default_type0;
1403 }
1404
1405 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1406 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1407 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1408 if (hpp->enable_serr)
1409 pci_cmd |= PCI_COMMAND_SERR;
1410 if (hpp->enable_perr)
1411 pci_cmd |= PCI_COMMAND_PARITY;
1412 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1413
1414 /* Program bridge control value */
1415 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1416 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1417 hpp->latency_timer);
1418 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1419 if (hpp->enable_serr)
1420 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1421 if (hpp->enable_perr)
1422 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1423 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1424 }
1425}
1426
1427static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1428{
1429 if (hpp)
1430 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1431}
1432
1433static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1434{
1435 int pos;
1436 u32 reg32;
1437
1438 if (!hpp)
1439 return;
1440
1441 if (hpp->revision > 1) {
1442 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1443 hpp->revision);
1444 return;
1445 }
1446
1447 /*
1448 * Don't allow _HPX to change MPS or MRRS settings. We manage
1449 * those to make sure they're consistent with the rest of the
1450 * platform.
1451 */
1452 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1453 PCI_EXP_DEVCTL_READRQ;
1454 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1455 PCI_EXP_DEVCTL_READRQ);
1456
1457 /* Initialize Device Control Register */
1458 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1459 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1460
1461 /* Initialize Link Control Register */
1462 if (pcie_cap_has_lnkctl(dev))
1463 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1464 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1465
1466 /* Find Advanced Error Reporting Enhanced Capability */
1467 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1468 if (!pos)
1469 return;
1470
1471 /* Initialize Uncorrectable Error Mask Register */
1472 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1473 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1474 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1475
1476 /* Initialize Uncorrectable Error Severity Register */
1477 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1478 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1479 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1480
1481 /* Initialize Correctable Error Mask Register */
1482 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1483 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1484 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1485
1486 /* Initialize Advanced Error Capabilities and Control Register */
1487 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1488 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1489 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1490
1491 /*
1492 * FIXME: The following two registers are not supported yet.
1493 *
1494 * o Secondary Uncorrectable Error Severity Register
1495 * o Secondary Uncorrectable Error Mask Register
1496 */
1497}
1498
1499static void pci_configure_device(struct pci_dev *dev)
1500{
1501 struct hotplug_params hpp;
1502 int ret;
1503
1504 pci_configure_mps(dev);
1505
1506 memset(&hpp, 0, sizeof(hpp));
1507 ret = pci_get_hp_params(dev, &hpp);
1508 if (ret)
1509 return;
1510
1511 program_hpp_type2(dev, hpp.t2);
1512 program_hpp_type1(dev, hpp.t1);
1513 program_hpp_type0(dev, hpp.t0);
1514}
1515
1516static void pci_release_capabilities(struct pci_dev *dev)
1517{
1518 pci_vpd_release(dev);
1519 pci_iov_release(dev);
1520 pci_free_cap_save_buffers(dev);
1521}
1522
1523/**
1524 * pci_release_dev - free a pci device structure when all users of it are finished.
1525 * @dev: device that's been disconnected
1526 *
1527 * Will be called only by the device core when all users of this pci device are
1528 * done.
1529 */
1530static void pci_release_dev(struct device *dev)
1531{
1532 struct pci_dev *pci_dev;
1533
1534 pci_dev = to_pci_dev(dev);
1535 pci_release_capabilities(pci_dev);
1536 pci_release_of_node(pci_dev);
1537 pcibios_release_device(pci_dev);
1538 pci_bus_put(pci_dev->bus);
1539 kfree(pci_dev->driver_override);
1540 kfree(pci_dev);
1541}
1542
1543struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1544{
1545 struct pci_dev *dev;
1546
1547 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1548 if (!dev)
1549 return NULL;
1550
1551 INIT_LIST_HEAD(&dev->bus_list);
1552 dev->dev.type = &pci_dev_type;
1553 dev->bus = pci_bus_get(bus);
1554
1555 return dev;
1556}
1557EXPORT_SYMBOL(pci_alloc_dev);
1558
1559bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1560 int crs_timeout)
1561{
1562 int delay = 1;
1563
1564 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1565 return false;
1566
1567 /* some broken boards return 0 or ~0 if a slot is empty: */
1568 if (*l == 0xffffffff || *l == 0x00000000 ||
1569 *l == 0x0000ffff || *l == 0xffff0000)
1570 return false;
1571
1572 /*
1573 * Configuration Request Retry Status. Some root ports return the
1574 * actual device ID instead of the synthetic ID (0xFFFF) required
1575 * by the PCIe spec. Ignore the device ID and only check for
1576 * (vendor id == 1).
1577 */
1578 while ((*l & 0xffff) == 0x0001) {
1579 if (!crs_timeout)
1580 return false;
1581
1582 msleep(delay);
1583 delay *= 2;
1584 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1585 return false;
1586 /* Card hasn't responded in 60 seconds? Must be stuck. */
1587 if (delay > crs_timeout) {
1588 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1589 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1590 PCI_FUNC(devfn));
1591 return false;
1592 }
1593 }
1594
1595 return true;
1596}
1597EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1598
1599/*
1600 * Read the config data for a PCI device, sanity-check it
1601 * and fill in the dev structure...
1602 */
1603static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1604{
1605 struct pci_dev *dev;
1606 u32 l;
1607
1608 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1609 return NULL;
1610
1611 dev = pci_alloc_dev(bus);
1612 if (!dev)
1613 return NULL;
1614
1615 dev->devfn = devfn;
1616 dev->vendor = l & 0xffff;
1617 dev->device = (l >> 16) & 0xffff;
1618
1619 pci_set_of_node(dev);
1620
1621 if (pci_setup_device(dev)) {
1622 pci_bus_put(dev->bus);
1623 kfree(dev);
1624 return NULL;
1625 }
1626
1627 return dev;
1628}
1629
1630static void pci_init_capabilities(struct pci_dev *dev)
1631{
1632 /* Enhanced Allocation */
1633 pci_ea_init(dev);
1634
1635 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1636 pci_msi_setup_pci_dev(dev);
1637
1638 /* Buffers for saving PCIe and PCI-X capabilities */
1639 pci_allocate_cap_save_buffers(dev);
1640
1641 /* Power Management */
1642 pci_pm_init(dev);
1643
1644 /* Vital Product Data */
1645 pci_vpd_init(dev);
1646
1647 /* Alternative Routing-ID Forwarding */
1648 pci_configure_ari(dev);
1649
1650 /* Single Root I/O Virtualization */
1651 pci_iov_init(dev);
1652
1653 /* Address Translation Services */
1654 pci_ats_init(dev);
1655
1656 /* Enable ACS P2P upstream forwarding */
1657 pci_enable_acs(dev);
1658
1659 pci_cleanup_aer_error_status_regs(dev);
1660}
1661
1662/*
1663 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1664 * devices. Firmware interfaces that can select the MSI domain on a
1665 * per-device basis should be called from here.
1666 */
1667static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1668{
1669 struct irq_domain *d;
1670
1671 /*
1672 * If a domain has been set through the pcibios_add_device
1673 * callback, then this is the one (platform code knows best).
1674 */
1675 d = dev_get_msi_domain(&dev->dev);
1676 if (d)
1677 return d;
1678
1679 /*
1680 * Let's see if we have a firmware interface able to provide
1681 * the domain.
1682 */
1683 d = pci_msi_get_device_domain(dev);
1684 if (d)
1685 return d;
1686
1687 return NULL;
1688}
1689
1690static void pci_set_msi_domain(struct pci_dev *dev)
1691{
1692 struct irq_domain *d;
1693
1694 /*
1695 * If the platform or firmware interfaces cannot supply a
1696 * device-specific MSI domain, then inherit the default domain
1697 * from the host bridge itself.
1698 */
1699 d = pci_dev_msi_domain(dev);
1700 if (!d)
1701 d = dev_get_msi_domain(&dev->bus->dev);
1702
1703 dev_set_msi_domain(&dev->dev, d);
1704}
1705
1706/**
1707 * pci_dma_configure - Setup DMA configuration
1708 * @dev: ptr to pci_dev struct of the PCI device
1709 *
1710 * Function to update PCI devices's DMA configuration using the same
1711 * info from the OF node or ACPI node of host bridge's parent (if any).
1712 */
1713static void pci_dma_configure(struct pci_dev *dev)
1714{
1715 struct device *bridge = pci_get_host_bridge_device(dev);
1716
1717 if (IS_ENABLED(CONFIG_OF) &&
1718 bridge->parent && bridge->parent->of_node) {
1719 of_dma_configure(&dev->dev, bridge->parent->of_node);
1720 } else if (has_acpi_companion(bridge)) {
1721 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1722 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1723
1724 if (attr == DEV_DMA_NOT_SUPPORTED)
1725 dev_warn(&dev->dev, "DMA not supported.\n");
1726 else
1727 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1728 attr == DEV_DMA_COHERENT);
1729 }
1730
1731 pci_put_host_bridge_device(bridge);
1732}
1733
1734void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1735{
1736 int ret;
1737
1738 pci_configure_device(dev);
1739
1740 device_initialize(&dev->dev);
1741 dev->dev.release = pci_release_dev;
1742
1743 set_dev_node(&dev->dev, pcibus_to_node(bus));
1744 dev->dev.dma_mask = &dev->dma_mask;
1745 dev->dev.dma_parms = &dev->dma_parms;
1746 dev->dev.coherent_dma_mask = 0xffffffffull;
1747 pci_dma_configure(dev);
1748
1749 pci_set_dma_max_seg_size(dev, 65536);
1750 pci_set_dma_seg_boundary(dev, 0xffffffff);
1751
1752 /* Fix up broken headers */
1753 pci_fixup_device(pci_fixup_header, dev);
1754
1755 /* moved out from quirk header fixup code */
1756 pci_reassigndev_resource_alignment(dev);
1757
1758 /* Clear the state_saved flag. */
1759 dev->state_saved = false;
1760
1761 /* Initialize various capabilities */
1762 pci_init_capabilities(dev);
1763
1764 /*
1765 * Add the device to our list of discovered devices
1766 * and the bus list for fixup functions, etc.
1767 */
1768 down_write(&pci_bus_sem);
1769 list_add_tail(&dev->bus_list, &bus->devices);
1770 up_write(&pci_bus_sem);
1771
1772 ret = pcibios_add_device(dev);
1773 WARN_ON(ret < 0);
1774
1775 /* Setup MSI irq domain */
1776 pci_set_msi_domain(dev);
1777
1778 /* Notifier could use PCI capabilities */
1779 dev->match_driver = false;
1780 ret = device_add(&dev->dev);
1781 WARN_ON(ret < 0);
1782}
1783
1784struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1785{
1786 struct pci_dev *dev;
1787
1788 dev = pci_get_slot(bus, devfn);
1789 if (dev) {
1790 pci_dev_put(dev);
1791 return dev;
1792 }
1793
1794 dev = pci_scan_device(bus, devfn);
1795 if (!dev)
1796 return NULL;
1797
1798 pci_device_add(dev, bus);
1799
1800 return dev;
1801}
1802EXPORT_SYMBOL(pci_scan_single_device);
1803
1804static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1805{
1806 int pos;
1807 u16 cap = 0;
1808 unsigned next_fn;
1809
1810 if (pci_ari_enabled(bus)) {
1811 if (!dev)
1812 return 0;
1813 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1814 if (!pos)
1815 return 0;
1816
1817 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1818 next_fn = PCI_ARI_CAP_NFN(cap);
1819 if (next_fn <= fn)
1820 return 0; /* protect against malformed list */
1821
1822 return next_fn;
1823 }
1824
1825 /* dev may be NULL for non-contiguous multifunction devices */
1826 if (!dev || dev->multifunction)
1827 return (fn + 1) % 8;
1828
1829 return 0;
1830}
1831
1832static int only_one_child(struct pci_bus *bus)
1833{
1834 struct pci_dev *parent = bus->self;
1835
1836 if (!parent || !pci_is_pcie(parent))
1837 return 0;
1838 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1839 return 1;
1840
1841 /*
1842 * PCIe downstream ports are bridges that normally lead to only a
1843 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
1844 * possible devices, not just device 0. See PCIe spec r3.0,
1845 * sec 7.3.1.
1846 */
1847 if (parent->has_secondary_link &&
1848 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1849 return 1;
1850 return 0;
1851}
1852
1853/**
1854 * pci_scan_slot - scan a PCI slot on a bus for devices.
1855 * @bus: PCI bus to scan
1856 * @devfn: slot number to scan (must have zero function.)
1857 *
1858 * Scan a PCI slot on the specified PCI bus for devices, adding
1859 * discovered devices to the @bus->devices list. New devices
1860 * will not have is_added set.
1861 *
1862 * Returns the number of new devices found.
1863 */
1864int pci_scan_slot(struct pci_bus *bus, int devfn)
1865{
1866 unsigned fn, nr = 0;
1867 struct pci_dev *dev;
1868
1869 if (only_one_child(bus) && (devfn > 0))
1870 return 0; /* Already scanned the entire slot */
1871
1872 dev = pci_scan_single_device(bus, devfn);
1873 if (!dev)
1874 return 0;
1875 if (!dev->is_added)
1876 nr++;
1877
1878 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1879 dev = pci_scan_single_device(bus, devfn + fn);
1880 if (dev) {
1881 if (!dev->is_added)
1882 nr++;
1883 dev->multifunction = 1;
1884 }
1885 }
1886
1887 /* only one slot has pcie device */
1888 if (bus->self && nr)
1889 pcie_aspm_init_link_state(bus->self);
1890
1891 return nr;
1892}
1893EXPORT_SYMBOL(pci_scan_slot);
1894
1895static int pcie_find_smpss(struct pci_dev *dev, void *data)
1896{
1897 u8 *smpss = data;
1898
1899 if (!pci_is_pcie(dev))
1900 return 0;
1901
1902 /*
1903 * We don't have a way to change MPS settings on devices that have
1904 * drivers attached. A hot-added device might support only the minimum
1905 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1906 * where devices may be hot-added, we limit the fabric MPS to 128 so
1907 * hot-added devices will work correctly.
1908 *
1909 * However, if we hot-add a device to a slot directly below a Root
1910 * Port, it's impossible for there to be other existing devices below
1911 * the port. We don't limit the MPS in this case because we can
1912 * reconfigure MPS on both the Root Port and the hot-added device,
1913 * and there are no other devices involved.
1914 *
1915 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1916 */
1917 if (dev->is_hotplug_bridge &&
1918 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1919 *smpss = 0;
1920
1921 if (*smpss > dev->pcie_mpss)
1922 *smpss = dev->pcie_mpss;
1923
1924 return 0;
1925}
1926
1927static void pcie_write_mps(struct pci_dev *dev, int mps)
1928{
1929 int rc;
1930
1931 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1932 mps = 128 << dev->pcie_mpss;
1933
1934 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1935 dev->bus->self)
1936 /* For "Performance", the assumption is made that
1937 * downstream communication will never be larger than
1938 * the MRRS. So, the MPS only needs to be configured
1939 * for the upstream communication. This being the case,
1940 * walk from the top down and set the MPS of the child
1941 * to that of the parent bus.
1942 *
1943 * Configure the device MPS with the smaller of the
1944 * device MPSS or the bridge MPS (which is assumed to be
1945 * properly configured at this point to the largest
1946 * allowable MPS based on its parent bus).
1947 */
1948 mps = min(mps, pcie_get_mps(dev->bus->self));
1949 }
1950
1951 rc = pcie_set_mps(dev, mps);
1952 if (rc)
1953 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1954}
1955
1956static void pcie_write_mrrs(struct pci_dev *dev)
1957{
1958 int rc, mrrs;
1959
1960 /* In the "safe" case, do not configure the MRRS. There appear to be
1961 * issues with setting MRRS to 0 on a number of devices.
1962 */
1963 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1964 return;
1965
1966 /* For Max performance, the MRRS must be set to the largest supported
1967 * value. However, it cannot be configured larger than the MPS the
1968 * device or the bus can support. This should already be properly
1969 * configured by a prior call to pcie_write_mps.
1970 */
1971 mrrs = pcie_get_mps(dev);
1972
1973 /* MRRS is a R/W register. Invalid values can be written, but a
1974 * subsequent read will verify if the value is acceptable or not.
1975 * If the MRRS value provided is not acceptable (e.g., too large),
1976 * shrink the value until it is acceptable to the HW.
1977 */
1978 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1979 rc = pcie_set_readrq(dev, mrrs);
1980 if (!rc)
1981 break;
1982
1983 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1984 mrrs /= 2;
1985 }
1986
1987 if (mrrs < 128)
1988 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1989}
1990
1991static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1992{
1993 int mps, orig_mps;
1994
1995 if (!pci_is_pcie(dev))
1996 return 0;
1997
1998 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
1999 pcie_bus_config == PCIE_BUS_DEFAULT)
2000 return 0;
2001
2002 mps = 128 << *(u8 *)data;
2003 orig_mps = pcie_get_mps(dev);
2004
2005 pcie_write_mps(dev, mps);
2006 pcie_write_mrrs(dev);
2007
2008 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2009 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2010 orig_mps, pcie_get_readrq(dev));
2011
2012 return 0;
2013}
2014
2015/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2016 * parents then children fashion. If this changes, then this code will not
2017 * work as designed.
2018 */
2019void pcie_bus_configure_settings(struct pci_bus *bus)
2020{
2021 u8 smpss = 0;
2022
2023 if (!bus->self)
2024 return;
2025
2026 if (!pci_is_pcie(bus->self))
2027 return;
2028
2029 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2030 * to be aware of the MPS of the destination. To work around this,
2031 * simply force the MPS of the entire system to the smallest possible.
2032 */
2033 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2034 smpss = 0;
2035
2036 if (pcie_bus_config == PCIE_BUS_SAFE) {
2037 smpss = bus->self->pcie_mpss;
2038
2039 pcie_find_smpss(bus->self, &smpss);
2040 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2041 }
2042
2043 pcie_bus_configure_set(bus->self, &smpss);
2044 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2045}
2046EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2047
2048unsigned int pci_scan_child_bus(struct pci_bus *bus)
2049{
2050 unsigned int devfn, pass, max = bus->busn_res.start;
2051 struct pci_dev *dev;
2052
2053 dev_dbg(&bus->dev, "scanning bus\n");
2054
2055 /* Go find them, Rover! */
2056 for (devfn = 0; devfn < 0x100; devfn += 8)
2057 pci_scan_slot(bus, devfn);
2058
2059 /* Reserve buses for SR-IOV capability. */
2060 max += pci_iov_bus_range(bus);
2061
2062 /*
2063 * After performing arch-dependent fixup of the bus, look behind
2064 * all PCI-to-PCI bridges on this bus.
2065 */
2066 if (!bus->is_added) {
2067 dev_dbg(&bus->dev, "fixups for bus\n");
2068 pcibios_fixup_bus(bus);
2069 bus->is_added = 1;
2070 }
2071
2072 for (pass = 0; pass < 2; pass++)
2073 list_for_each_entry(dev, &bus->devices, bus_list) {
2074 if (pci_is_bridge(dev))
2075 max = pci_scan_bridge(bus, dev, max, pass);
2076 }
2077
2078 /*
2079 * We've scanned the bus and so we know all about what's on
2080 * the other side of any bridges that may be on this bus plus
2081 * any devices.
2082 *
2083 * Return how far we've got finding sub-buses.
2084 */
2085 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2086 return max;
2087}
2088EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2089
2090/**
2091 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2092 * @bridge: Host bridge to set up.
2093 *
2094 * Default empty implementation. Replace with an architecture-specific setup
2095 * routine, if necessary.
2096 */
2097int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2098{
2099 return 0;
2100}
2101
2102void __weak pcibios_add_bus(struct pci_bus *bus)
2103{
2104}
2105
2106void __weak pcibios_remove_bus(struct pci_bus *bus)
2107{
2108}
2109
2110struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2111 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2112{
2113 int error;
2114 struct pci_host_bridge *bridge;
2115 struct pci_bus *b, *b2;
2116 struct resource_entry *window, *n;
2117 struct resource *res;
2118 resource_size_t offset;
2119 char bus_addr[64];
2120 char *fmt;
2121
2122 b = pci_alloc_bus(NULL);
2123 if (!b)
2124 return NULL;
2125
2126 b->sysdata = sysdata;
2127 b->ops = ops;
2128 b->number = b->busn_res.start = bus;
2129 pci_bus_assign_domain_nr(b, parent);
2130 b2 = pci_find_bus(pci_domain_nr(b), bus);
2131 if (b2) {
2132 /* If we already got to this bus through a different bridge, ignore it */
2133 dev_dbg(&b2->dev, "bus already known\n");
2134 goto err_out;
2135 }
2136
2137 bridge = pci_alloc_host_bridge(b);
2138 if (!bridge)
2139 goto err_out;
2140
2141 bridge->dev.parent = parent;
2142 bridge->dev.release = pci_release_host_bridge_dev;
2143 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2144 error = pcibios_root_bridge_prepare(bridge);
2145 if (error) {
2146 kfree(bridge);
2147 goto err_out;
2148 }
2149
2150 error = device_register(&bridge->dev);
2151 if (error) {
2152 put_device(&bridge->dev);
2153 goto err_out;
2154 }
2155 b->bridge = get_device(&bridge->dev);
2156 device_enable_async_suspend(b->bridge);
2157 pci_set_bus_of_node(b);
2158 pci_set_bus_msi_domain(b);
2159
2160 if (!parent)
2161 set_dev_node(b->bridge, pcibus_to_node(b));
2162
2163 b->dev.class = &pcibus_class;
2164 b->dev.parent = b->bridge;
2165 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2166 error = device_register(&b->dev);
2167 if (error)
2168 goto class_dev_reg_err;
2169
2170 pcibios_add_bus(b);
2171
2172 /* Create legacy_io and legacy_mem files for this bus */
2173 pci_create_legacy_files(b);
2174
2175 if (parent)
2176 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2177 else
2178 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2179
2180 /* Add initial resources to the bus */
2181 resource_list_for_each_entry_safe(window, n, resources) {
2182 list_move_tail(&window->node, &bridge->windows);
2183 res = window->res;
2184 offset = window->offset;
2185 if (res->flags & IORESOURCE_BUS)
2186 pci_bus_insert_busn_res(b, bus, res->end);
2187 else
2188 pci_bus_add_resource(b, res, 0);
2189 if (offset) {
2190 if (resource_type(res) == IORESOURCE_IO)
2191 fmt = " (bus address [%#06llx-%#06llx])";
2192 else
2193 fmt = " (bus address [%#010llx-%#010llx])";
2194 snprintf(bus_addr, sizeof(bus_addr), fmt,
2195 (unsigned long long) (res->start - offset),
2196 (unsigned long long) (res->end - offset));
2197 } else
2198 bus_addr[0] = '\0';
2199 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2200 }
2201
2202 down_write(&pci_bus_sem);
2203 list_add_tail(&b->node, &pci_root_buses);
2204 up_write(&pci_bus_sem);
2205
2206 return b;
2207
2208class_dev_reg_err:
2209 put_device(&bridge->dev);
2210 device_unregister(&bridge->dev);
2211err_out:
2212 kfree(b);
2213 return NULL;
2214}
2215EXPORT_SYMBOL_GPL(pci_create_root_bus);
2216
2217int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2218{
2219 struct resource *res = &b->busn_res;
2220 struct resource *parent_res, *conflict;
2221
2222 res->start = bus;
2223 res->end = bus_max;
2224 res->flags = IORESOURCE_BUS;
2225
2226 if (!pci_is_root_bus(b))
2227 parent_res = &b->parent->busn_res;
2228 else {
2229 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2230 res->flags |= IORESOURCE_PCI_FIXED;
2231 }
2232
2233 conflict = request_resource_conflict(parent_res, res);
2234
2235 if (conflict)
2236 dev_printk(KERN_DEBUG, &b->dev,
2237 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2238 res, pci_is_root_bus(b) ? "domain " : "",
2239 parent_res, conflict->name, conflict);
2240
2241 return conflict == NULL;
2242}
2243
2244int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2245{
2246 struct resource *res = &b->busn_res;
2247 struct resource old_res = *res;
2248 resource_size_t size;
2249 int ret;
2250
2251 if (res->start > bus_max)
2252 return -EINVAL;
2253
2254 size = bus_max - res->start + 1;
2255 ret = adjust_resource(res, res->start, size);
2256 dev_printk(KERN_DEBUG, &b->dev,
2257 "busn_res: %pR end %s updated to %02x\n",
2258 &old_res, ret ? "can not be" : "is", bus_max);
2259
2260 if (!ret && !res->parent)
2261 pci_bus_insert_busn_res(b, res->start, res->end);
2262
2263 return ret;
2264}
2265
2266void pci_bus_release_busn_res(struct pci_bus *b)
2267{
2268 struct resource *res = &b->busn_res;
2269 int ret;
2270
2271 if (!res->flags || !res->parent)
2272 return;
2273
2274 ret = release_resource(res);
2275 dev_printk(KERN_DEBUG, &b->dev,
2276 "busn_res: %pR %s released\n",
2277 res, ret ? "can not be" : "is");
2278}
2279
2280struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2281 struct pci_ops *ops, void *sysdata,
2282 struct list_head *resources, struct msi_controller *msi)
2283{
2284 struct resource_entry *window;
2285 bool found = false;
2286 struct pci_bus *b;
2287 int max;
2288
2289 resource_list_for_each_entry(window, resources)
2290 if (window->res->flags & IORESOURCE_BUS) {
2291 found = true;
2292 break;
2293 }
2294
2295 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2296 if (!b)
2297 return NULL;
2298
2299 b->msi = msi;
2300
2301 if (!found) {
2302 dev_info(&b->dev,
2303 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2304 bus);
2305 pci_bus_insert_busn_res(b, bus, 255);
2306 }
2307
2308 max = pci_scan_child_bus(b);
2309
2310 if (!found)
2311 pci_bus_update_busn_res_end(b, max);
2312
2313 return b;
2314}
2315
2316struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2317 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2318{
2319 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2320 NULL);
2321}
2322EXPORT_SYMBOL(pci_scan_root_bus);
2323
2324struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2325 void *sysdata)
2326{
2327 LIST_HEAD(resources);
2328 struct pci_bus *b;
2329
2330 pci_add_resource(&resources, &ioport_resource);
2331 pci_add_resource(&resources, &iomem_resource);
2332 pci_add_resource(&resources, &busn_resource);
2333 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2334 if (b) {
2335 pci_scan_child_bus(b);
2336 } else {
2337 pci_free_resource_list(&resources);
2338 }
2339 return b;
2340}
2341EXPORT_SYMBOL(pci_scan_bus);
2342
2343/**
2344 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2345 * @bridge: PCI bridge for the bus to scan
2346 *
2347 * Scan a PCI bus and child buses for new devices, add them,
2348 * and enable them, resizing bridge mmio/io resource if necessary
2349 * and possible. The caller must ensure the child devices are already
2350 * removed for resizing to occur.
2351 *
2352 * Returns the max number of subordinate bus discovered.
2353 */
2354unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2355{
2356 unsigned int max;
2357 struct pci_bus *bus = bridge->subordinate;
2358
2359 max = pci_scan_child_bus(bus);
2360
2361 pci_assign_unassigned_bridge_resources(bridge);
2362
2363 pci_bus_add_devices(bus);
2364
2365 return max;
2366}
2367
2368/**
2369 * pci_rescan_bus - scan a PCI bus for devices.
2370 * @bus: PCI bus to scan
2371 *
2372 * Scan a PCI bus and child buses for new devices, adds them,
2373 * and enables them.
2374 *
2375 * Returns the max number of subordinate bus discovered.
2376 */
2377unsigned int pci_rescan_bus(struct pci_bus *bus)
2378{
2379 unsigned int max;
2380
2381 max = pci_scan_child_bus(bus);
2382 pci_assign_unassigned_bus_resources(bus);
2383 pci_bus_add_devices(bus);
2384
2385 return max;
2386}
2387EXPORT_SYMBOL_GPL(pci_rescan_bus);
2388
2389/*
2390 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2391 * routines should always be executed under this mutex.
2392 */
2393static DEFINE_MUTEX(pci_rescan_remove_lock);
2394
2395void pci_lock_rescan_remove(void)
2396{
2397 mutex_lock(&pci_rescan_remove_lock);
2398}
2399EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2400
2401void pci_unlock_rescan_remove(void)
2402{
2403 mutex_unlock(&pci_rescan_remove_lock);
2404}
2405EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2406
2407static int __init pci_sort_bf_cmp(const struct device *d_a,
2408 const struct device *d_b)
2409{
2410 const struct pci_dev *a = to_pci_dev(d_a);
2411 const struct pci_dev *b = to_pci_dev(d_b);
2412
2413 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2414 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2415
2416 if (a->bus->number < b->bus->number) return -1;
2417 else if (a->bus->number > b->bus->number) return 1;
2418
2419 if (a->devfn < b->devfn) return -1;
2420 else if (a->devfn > b->devfn) return 1;
2421
2422 return 0;
2423}
2424
2425void __init pci_sort_breadthfirst(void)
2426{
2427 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2428}