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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
4 * Copyright (C) 2015 Linaro Ltd.
5 * Author: Jassi Brar <jaswinder.singh@linaro.org>
6 */
7
8#include <linux/amba/bus.h>
9#include <linux/device.h>
10#include <linux/err.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/mailbox_controller.h>
14#include <linux/module.h>
15
16#define INTR_STAT_OFS 0x0
17#define INTR_SET_OFS 0x8
18#define INTR_CLR_OFS 0x10
19
20#define MHU_LP_OFFSET 0x0
21#define MHU_HP_OFFSET 0x20
22#define MHU_SEC_OFFSET 0x200
23#define TX_REG_OFFSET 0x100
24
25#define MHU_CHANS 3
26
27struct mhu_link {
28 unsigned irq;
29 void __iomem *tx_reg;
30 void __iomem *rx_reg;
31};
32
33struct arm_mhu {
34 void __iomem *base;
35 struct mhu_link mlink[MHU_CHANS];
36 struct mbox_chan chan[MHU_CHANS];
37 struct mbox_controller mbox;
38};
39
40static irqreturn_t mhu_rx_interrupt(int irq, void *p)
41{
42 struct mbox_chan *chan = p;
43 struct mhu_link *mlink = chan->con_priv;
44 u32 val;
45
46 val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
47 if (!val)
48 return IRQ_NONE;
49
50 mbox_chan_received_data(chan, (void *)&val);
51
52 writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
53
54 return IRQ_HANDLED;
55}
56
57static bool mhu_last_tx_done(struct mbox_chan *chan)
58{
59 struct mhu_link *mlink = chan->con_priv;
60 u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
61
62 return (val == 0);
63}
64
65static int mhu_send_data(struct mbox_chan *chan, void *data)
66{
67 struct mhu_link *mlink = chan->con_priv;
68 u32 *arg = data;
69
70 writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
71
72 return 0;
73}
74
75static int mhu_startup(struct mbox_chan *chan)
76{
77 struct mhu_link *mlink = chan->con_priv;
78 u32 val;
79 int ret;
80
81 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
82 writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
83
84 ret = request_irq(mlink->irq, mhu_rx_interrupt,
85 IRQF_SHARED, "mhu_link", chan);
86 if (ret) {
87 dev_err(chan->mbox->dev,
88 "Unable to acquire IRQ %d\n", mlink->irq);
89 return ret;
90 }
91
92 return 0;
93}
94
95static void mhu_shutdown(struct mbox_chan *chan)
96{
97 struct mhu_link *mlink = chan->con_priv;
98
99 free_irq(mlink->irq, chan);
100}
101
102static const struct mbox_chan_ops mhu_ops = {
103 .send_data = mhu_send_data,
104 .startup = mhu_startup,
105 .shutdown = mhu_shutdown,
106 .last_tx_done = mhu_last_tx_done,
107};
108
109static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
110{
111 int i, err;
112 struct arm_mhu *mhu;
113 struct device *dev = &adev->dev;
114 int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
115
116 if (!of_device_is_compatible(dev->of_node, "arm,mhu"))
117 return -ENODEV;
118
119 /* Allocate memory for device */
120 mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
121 if (!mhu)
122 return -ENOMEM;
123
124 mhu->base = devm_ioremap_resource(dev, &adev->res);
125 if (IS_ERR(mhu->base))
126 return PTR_ERR(mhu->base);
127
128 for (i = 0; i < MHU_CHANS; i++) {
129 mhu->chan[i].con_priv = &mhu->mlink[i];
130 mhu->mlink[i].irq = adev->irq[i];
131 mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];
132 mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
133 }
134
135 mhu->mbox.dev = dev;
136 mhu->mbox.chans = &mhu->chan[0];
137 mhu->mbox.num_chans = MHU_CHANS;
138 mhu->mbox.ops = &mhu_ops;
139 mhu->mbox.txdone_irq = false;
140 mhu->mbox.txdone_poll = true;
141 mhu->mbox.txpoll_period = 1;
142
143 amba_set_drvdata(adev, mhu);
144
145 err = devm_mbox_controller_register(dev, &mhu->mbox);
146 if (err) {
147 dev_err(dev, "Failed to register mailboxes %d\n", err);
148 return err;
149 }
150
151 dev_info(dev, "ARM MHU Mailbox registered\n");
152 return 0;
153}
154
155static struct amba_id mhu_ids[] = {
156 {
157 .id = 0x1bb098,
158 .mask = 0xffffff,
159 },
160 { 0, 0 },
161};
162MODULE_DEVICE_TABLE(amba, mhu_ids);
163
164static struct amba_driver arm_mhu_driver = {
165 .drv = {
166 .name = "mhu",
167 },
168 .id_table = mhu_ids,
169 .probe = mhu_probe,
170};
171module_amba_driver(arm_mhu_driver);
172
173MODULE_LICENSE("GPL v2");
174MODULE_DESCRIPTION("ARM MHU Driver");
175MODULE_AUTHOR("Jassi Brar <jassisinghbrar@gmail.com>");
1/*
2 * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
3 * Copyright (C) 2015 Linaro Ltd.
4 * Author: Jassi Brar <jaswinder.singh@linaro.org>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/interrupt.h>
17#include <linux/spinlock.h>
18#include <linux/mutex.h>
19#include <linux/delay.h>
20#include <linux/slab.h>
21#include <linux/err.h>
22#include <linux/io.h>
23#include <linux/module.h>
24#include <linux/amba/bus.h>
25#include <linux/mailbox_controller.h>
26
27#define INTR_STAT_OFS 0x0
28#define INTR_SET_OFS 0x8
29#define INTR_CLR_OFS 0x10
30
31#define MHU_LP_OFFSET 0x0
32#define MHU_HP_OFFSET 0x20
33#define MHU_SEC_OFFSET 0x200
34#define TX_REG_OFFSET 0x100
35
36#define MHU_CHANS 3
37
38struct mhu_link {
39 unsigned irq;
40 void __iomem *tx_reg;
41 void __iomem *rx_reg;
42};
43
44struct arm_mhu {
45 void __iomem *base;
46 struct mhu_link mlink[MHU_CHANS];
47 struct mbox_chan chan[MHU_CHANS];
48 struct mbox_controller mbox;
49};
50
51static irqreturn_t mhu_rx_interrupt(int irq, void *p)
52{
53 struct mbox_chan *chan = p;
54 struct mhu_link *mlink = chan->con_priv;
55 u32 val;
56
57 val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
58 if (!val)
59 return IRQ_NONE;
60
61 mbox_chan_received_data(chan, (void *)&val);
62
63 writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
64
65 return IRQ_HANDLED;
66}
67
68static bool mhu_last_tx_done(struct mbox_chan *chan)
69{
70 struct mhu_link *mlink = chan->con_priv;
71 u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
72
73 return (val == 0);
74}
75
76static int mhu_send_data(struct mbox_chan *chan, void *data)
77{
78 struct mhu_link *mlink = chan->con_priv;
79 u32 *arg = data;
80
81 writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
82
83 return 0;
84}
85
86static int mhu_startup(struct mbox_chan *chan)
87{
88 struct mhu_link *mlink = chan->con_priv;
89 u32 val;
90 int ret;
91
92 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
93 writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
94
95 ret = request_irq(mlink->irq, mhu_rx_interrupt,
96 IRQF_SHARED, "mhu_link", chan);
97 if (ret) {
98 dev_err(chan->mbox->dev,
99 "Unable to acquire IRQ %d\n", mlink->irq);
100 return ret;
101 }
102
103 return 0;
104}
105
106static void mhu_shutdown(struct mbox_chan *chan)
107{
108 struct mhu_link *mlink = chan->con_priv;
109
110 free_irq(mlink->irq, chan);
111}
112
113static const struct mbox_chan_ops mhu_ops = {
114 .send_data = mhu_send_data,
115 .startup = mhu_startup,
116 .shutdown = mhu_shutdown,
117 .last_tx_done = mhu_last_tx_done,
118};
119
120static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
121{
122 int i, err;
123 struct arm_mhu *mhu;
124 struct device *dev = &adev->dev;
125 int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
126
127 /* Allocate memory for device */
128 mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
129 if (!mhu)
130 return -ENOMEM;
131
132 mhu->base = devm_ioremap_resource(dev, &adev->res);
133 if (IS_ERR(mhu->base)) {
134 dev_err(dev, "ioremap failed\n");
135 return PTR_ERR(mhu->base);
136 }
137
138 for (i = 0; i < MHU_CHANS; i++) {
139 mhu->chan[i].con_priv = &mhu->mlink[i];
140 mhu->mlink[i].irq = adev->irq[i];
141 mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];
142 mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
143 }
144
145 mhu->mbox.dev = dev;
146 mhu->mbox.chans = &mhu->chan[0];
147 mhu->mbox.num_chans = MHU_CHANS;
148 mhu->mbox.ops = &mhu_ops;
149 mhu->mbox.txdone_irq = false;
150 mhu->mbox.txdone_poll = true;
151 mhu->mbox.txpoll_period = 1;
152
153 amba_set_drvdata(adev, mhu);
154
155 err = mbox_controller_register(&mhu->mbox);
156 if (err) {
157 dev_err(dev, "Failed to register mailboxes %d\n", err);
158 return err;
159 }
160
161 dev_info(dev, "ARM MHU Mailbox registered\n");
162 return 0;
163}
164
165static int mhu_remove(struct amba_device *adev)
166{
167 struct arm_mhu *mhu = amba_get_drvdata(adev);
168
169 mbox_controller_unregister(&mhu->mbox);
170
171 return 0;
172}
173
174static struct amba_id mhu_ids[] = {
175 {
176 .id = 0x1bb098,
177 .mask = 0xffffff,
178 },
179 { 0, 0 },
180};
181MODULE_DEVICE_TABLE(amba, mhu_ids);
182
183static struct amba_driver arm_mhu_driver = {
184 .drv = {
185 .name = "mhu",
186 },
187 .id_table = mhu_ids,
188 .probe = mhu_probe,
189 .remove = mhu_remove,
190};
191module_amba_driver(arm_mhu_driver);
192
193MODULE_LICENSE("GPL v2");
194MODULE_DESCRIPTION("ARM MHU Driver");
195MODULE_AUTHOR("Jassi Brar <jassisinghbrar@gmail.com>");