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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * I2C driver for the Renesas EMEV2 SoC
4 *
5 * Copyright (C) 2015 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright 2013 Codethink Ltd.
7 * Copyright 2010-2015 Renesas Electronics Corporation
8 */
9
10#include <linux/clk.h>
11#include <linux/completion.h>
12#include <linux/device.h>
13#include <linux/i2c.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/sched.h>
22
23/* I2C Registers */
24#define I2C_OFS_IICACT0 0x00 /* start */
25#define I2C_OFS_IIC0 0x04 /* shift */
26#define I2C_OFS_IICC0 0x08 /* control */
27#define I2C_OFS_SVA0 0x0c /* slave address */
28#define I2C_OFS_IICCL0 0x10 /* clock select */
29#define I2C_OFS_IICX0 0x14 /* extension */
30#define I2C_OFS_IICS0 0x18 /* status */
31#define I2C_OFS_IICSE0 0x1c /* status For emulation */
32#define I2C_OFS_IICF0 0x20 /* IIC flag */
33
34/* I2C IICACT0 Masks */
35#define I2C_BIT_IICE0 0x0001
36
37/* I2C IICC0 Masks */
38#define I2C_BIT_LREL0 0x0040
39#define I2C_BIT_WREL0 0x0020
40#define I2C_BIT_SPIE0 0x0010
41#define I2C_BIT_WTIM0 0x0008
42#define I2C_BIT_ACKE0 0x0004
43#define I2C_BIT_STT0 0x0002
44#define I2C_BIT_SPT0 0x0001
45
46/* I2C IICCL0 Masks */
47#define I2C_BIT_SMC0 0x0008
48#define I2C_BIT_DFC0 0x0004
49
50/* I2C IICSE0 Masks */
51#define I2C_BIT_MSTS0 0x0080
52#define I2C_BIT_ALD0 0x0040
53#define I2C_BIT_EXC0 0x0020
54#define I2C_BIT_COI0 0x0010
55#define I2C_BIT_TRC0 0x0008
56#define I2C_BIT_ACKD0 0x0004
57#define I2C_BIT_STD0 0x0002
58#define I2C_BIT_SPD0 0x0001
59
60/* I2C IICF0 Masks */
61#define I2C_BIT_STCF 0x0080
62#define I2C_BIT_IICBSY 0x0040
63#define I2C_BIT_STCEN 0x0002
64#define I2C_BIT_IICRSV 0x0001
65
66struct em_i2c_device {
67 void __iomem *base;
68 struct i2c_adapter adap;
69 struct completion msg_done;
70 struct clk *sclk;
71 struct i2c_client *slave;
72 int irq;
73};
74
75static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg)
76{
77 writeb((readb(priv->base + reg) & ~clear) | set, priv->base + reg);
78}
79
80static int em_i2c_wait_for_event(struct em_i2c_device *priv)
81{
82 unsigned long time_left;
83 int status;
84
85 reinit_completion(&priv->msg_done);
86
87 time_left = wait_for_completion_timeout(&priv->msg_done, priv->adap.timeout);
88
89 if (!time_left)
90 return -ETIMEDOUT;
91
92 status = readb(priv->base + I2C_OFS_IICSE0);
93 return status & I2C_BIT_ALD0 ? -EAGAIN : status;
94}
95
96static void em_i2c_stop(struct em_i2c_device *priv)
97{
98 /* Send Stop condition */
99 em_clear_set_bit(priv, 0, I2C_BIT_SPT0 | I2C_BIT_SPIE0, I2C_OFS_IICC0);
100
101 /* Wait for stop condition */
102 em_i2c_wait_for_event(priv);
103}
104
105static void em_i2c_reset(struct i2c_adapter *adap)
106{
107 struct em_i2c_device *priv = i2c_get_adapdata(adap);
108 int retr;
109
110 /* If I2C active */
111 if (readb(priv->base + I2C_OFS_IICACT0) & I2C_BIT_IICE0) {
112 /* Disable I2C operation */
113 writeb(0, priv->base + I2C_OFS_IICACT0);
114
115 retr = 1000;
116 while (readb(priv->base + I2C_OFS_IICACT0) == 1 && retr)
117 retr--;
118 WARN_ON(retr == 0);
119 }
120
121 /* Transfer mode set */
122 writeb(I2C_BIT_DFC0, priv->base + I2C_OFS_IICCL0);
123
124 /* Can Issue start without detecting a stop, Reservation disabled. */
125 writeb(I2C_BIT_STCEN | I2C_BIT_IICRSV, priv->base + I2C_OFS_IICF0);
126
127 /* I2C enable, 9 bit interrupt mode */
128 writeb(I2C_BIT_WTIM0, priv->base + I2C_OFS_IICC0);
129
130 /* Enable I2C operation */
131 writeb(I2C_BIT_IICE0, priv->base + I2C_OFS_IICACT0);
132
133 retr = 1000;
134 while (readb(priv->base + I2C_OFS_IICACT0) == 0 && retr)
135 retr--;
136 WARN_ON(retr == 0);
137}
138
139static int __em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
140 int stop)
141{
142 struct em_i2c_device *priv = i2c_get_adapdata(adap);
143 int count, status, read = !!(msg->flags & I2C_M_RD);
144
145 /* Send start condition */
146 em_clear_set_bit(priv, 0, I2C_BIT_ACKE0 | I2C_BIT_WTIM0, I2C_OFS_IICC0);
147 em_clear_set_bit(priv, 0, I2C_BIT_STT0, I2C_OFS_IICC0);
148
149 /* Send slave address and R/W type */
150 writeb(i2c_8bit_addr_from_msg(msg), priv->base + I2C_OFS_IIC0);
151
152 /* Wait for transaction */
153 status = em_i2c_wait_for_event(priv);
154 if (status < 0)
155 goto out_reset;
156
157 /* Received NACK (result of setting slave address and R/W) */
158 if (!(status & I2C_BIT_ACKD0)) {
159 em_i2c_stop(priv);
160 goto out;
161 }
162
163 /* Extra setup for read transactions */
164 if (read) {
165 /* 8 bit interrupt mode */
166 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, I2C_OFS_IICC0);
167 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, I2C_OFS_IICC0);
168
169 /* Wait for transaction */
170 status = em_i2c_wait_for_event(priv);
171 if (status < 0)
172 goto out_reset;
173 }
174
175 /* Send / receive data */
176 for (count = 0; count < msg->len; count++) {
177 if (read) { /* Read transaction */
178 msg->buf[count] = readb(priv->base + I2C_OFS_IIC0);
179 em_clear_set_bit(priv, 0, I2C_BIT_WREL0, I2C_OFS_IICC0);
180
181 } else { /* Write transaction */
182 /* Received NACK */
183 if (!(status & I2C_BIT_ACKD0)) {
184 em_i2c_stop(priv);
185 goto out;
186 }
187
188 /* Write data */
189 writeb(msg->buf[count], priv->base + I2C_OFS_IIC0);
190 }
191
192 /* Wait for R/W transaction */
193 status = em_i2c_wait_for_event(priv);
194 if (status < 0)
195 goto out_reset;
196 }
197
198 if (stop)
199 em_i2c_stop(priv);
200
201 return count;
202
203out_reset:
204 em_i2c_reset(adap);
205out:
206 return status < 0 ? status : -ENXIO;
207}
208
209static int em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
210 int num)
211{
212 struct em_i2c_device *priv = i2c_get_adapdata(adap);
213 int ret, i;
214
215 if (readb(priv->base + I2C_OFS_IICF0) & I2C_BIT_IICBSY)
216 return -EAGAIN;
217
218 for (i = 0; i < num; i++) {
219 ret = __em_i2c_xfer(adap, &msgs[i], (i == (num - 1)));
220 if (ret < 0)
221 return ret;
222 }
223
224 /* I2C transfer completed */
225 return num;
226}
227
228static bool em_i2c_slave_irq(struct em_i2c_device *priv)
229{
230 u8 status, value;
231 enum i2c_slave_event event;
232 int ret;
233
234 if (!priv->slave)
235 return false;
236
237 status = readb(priv->base + I2C_OFS_IICSE0);
238
239 /* Extension code, do not participate */
240 if (status & I2C_BIT_EXC0) {
241 em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
242 return true;
243 }
244
245 /* Stop detected, we don't know if it's for slave or master */
246 if (status & I2C_BIT_SPD0) {
247 /* Notify slave device */
248 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
249 /* Pretend we did not handle the interrupt */
250 return false;
251 }
252
253 /* Only handle interrupts addressed to us */
254 if (!(status & I2C_BIT_COI0))
255 return false;
256
257 /* Enable stop interrupts */
258 em_clear_set_bit(priv, 0, I2C_BIT_SPIE0, I2C_OFS_IICC0);
259
260 /* Transmission or Reception */
261 if (status & I2C_BIT_TRC0) {
262 if (status & I2C_BIT_ACKD0) {
263 /* 9 bit interrupt mode */
264 em_clear_set_bit(priv, 0, I2C_BIT_WTIM0, I2C_OFS_IICC0);
265
266 /* Send data */
267 event = status & I2C_BIT_STD0 ?
268 I2C_SLAVE_READ_REQUESTED :
269 I2C_SLAVE_READ_PROCESSED;
270 i2c_slave_event(priv->slave, event, &value);
271 writeb(value, priv->base + I2C_OFS_IIC0);
272 } else {
273 /* NACK, stop transmitting */
274 em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
275 }
276 } else {
277 /* 8 bit interrupt mode */
278 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0,
279 I2C_OFS_IICC0);
280 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0,
281 I2C_OFS_IICC0);
282
283 if (status & I2C_BIT_STD0) {
284 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED,
285 &value);
286 } else {
287 /* Recv data */
288 value = readb(priv->base + I2C_OFS_IIC0);
289 ret = i2c_slave_event(priv->slave,
290 I2C_SLAVE_WRITE_RECEIVED, &value);
291 if (ret < 0)
292 em_clear_set_bit(priv, I2C_BIT_ACKE0, 0,
293 I2C_OFS_IICC0);
294 }
295 }
296
297 return true;
298}
299
300static irqreturn_t em_i2c_irq_handler(int this_irq, void *dev_id)
301{
302 struct em_i2c_device *priv = dev_id;
303
304 if (em_i2c_slave_irq(priv))
305 return IRQ_HANDLED;
306
307 complete(&priv->msg_done);
308
309 return IRQ_HANDLED;
310}
311
312static u32 em_i2c_func(struct i2c_adapter *adap)
313{
314 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE;
315}
316
317static int em_i2c_reg_slave(struct i2c_client *slave)
318{
319 struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter);
320
321 if (priv->slave)
322 return -EBUSY;
323
324 if (slave->flags & I2C_CLIENT_TEN)
325 return -EAFNOSUPPORT;
326
327 priv->slave = slave;
328
329 /* Set slave address */
330 writeb(slave->addr << 1, priv->base + I2C_OFS_SVA0);
331
332 return 0;
333}
334
335static int em_i2c_unreg_slave(struct i2c_client *slave)
336{
337 struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter);
338
339 WARN_ON(!priv->slave);
340
341 writeb(0, priv->base + I2C_OFS_SVA0);
342
343 /*
344 * Wait for interrupt to finish. New slave irqs cannot happen because we
345 * cleared the slave address and, thus, only extension codes will be
346 * detected which do not use the slave ptr.
347 */
348 synchronize_irq(priv->irq);
349 priv->slave = NULL;
350
351 return 0;
352}
353
354static const struct i2c_algorithm em_i2c_algo = {
355 .master_xfer = em_i2c_xfer,
356 .functionality = em_i2c_func,
357 .reg_slave = em_i2c_reg_slave,
358 .unreg_slave = em_i2c_unreg_slave,
359};
360
361static int em_i2c_probe(struct platform_device *pdev)
362{
363 struct em_i2c_device *priv;
364 int ret;
365
366 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
367 if (!priv)
368 return -ENOMEM;
369
370 priv->base = devm_platform_ioremap_resource(pdev, 0);
371 if (IS_ERR(priv->base))
372 return PTR_ERR(priv->base);
373
374 strscpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
375
376 priv->sclk = devm_clk_get(&pdev->dev, "sclk");
377 if (IS_ERR(priv->sclk))
378 return PTR_ERR(priv->sclk);
379
380 ret = clk_prepare_enable(priv->sclk);
381 if (ret)
382 return ret;
383
384 priv->adap.timeout = msecs_to_jiffies(100);
385 priv->adap.retries = 5;
386 priv->adap.dev.parent = &pdev->dev;
387 priv->adap.algo = &em_i2c_algo;
388 priv->adap.owner = THIS_MODULE;
389 priv->adap.dev.of_node = pdev->dev.of_node;
390
391 init_completion(&priv->msg_done);
392
393 platform_set_drvdata(pdev, priv);
394 i2c_set_adapdata(&priv->adap, priv);
395
396 em_i2c_reset(&priv->adap);
397
398 ret = platform_get_irq(pdev, 0);
399 if (ret < 0)
400 goto err_clk;
401 priv->irq = ret;
402 ret = devm_request_irq(&pdev->dev, priv->irq, em_i2c_irq_handler, 0,
403 "em_i2c", priv);
404 if (ret)
405 goto err_clk;
406
407 ret = i2c_add_adapter(&priv->adap);
408
409 if (ret)
410 goto err_clk;
411
412 dev_info(&pdev->dev, "Added i2c controller %d, irq %d\n", priv->adap.nr,
413 priv->irq);
414
415 return 0;
416
417err_clk:
418 clk_disable_unprepare(priv->sclk);
419 return ret;
420}
421
422static int em_i2c_remove(struct platform_device *dev)
423{
424 struct em_i2c_device *priv = platform_get_drvdata(dev);
425
426 i2c_del_adapter(&priv->adap);
427 clk_disable_unprepare(priv->sclk);
428
429 return 0;
430}
431
432static const struct of_device_id em_i2c_ids[] = {
433 { .compatible = "renesas,iic-emev2", },
434 { }
435};
436
437static struct platform_driver em_i2c_driver = {
438 .probe = em_i2c_probe,
439 .remove = em_i2c_remove,
440 .driver = {
441 .name = "em-i2c",
442 .of_match_table = em_i2c_ids,
443 }
444};
445module_platform_driver(em_i2c_driver);
446
447MODULE_DESCRIPTION("EMEV2 I2C bus driver");
448MODULE_AUTHOR("Ian Molton");
449MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
450MODULE_LICENSE("GPL v2");
451MODULE_DEVICE_TABLE(of, em_i2c_ids);
1/*
2 * I2C driver for the Renesas EMEV2 SoC
3 *
4 * Copyright (C) 2015 Wolfram Sang <wsa@sang-engineering.com>
5 * Copyright 2013 Codethink Ltd.
6 * Copyright 2010-2015 Renesas Electronics Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2
10 * as published by the Free Software Foundation.
11 */
12
13#include <linux/clk.h>
14#include <linux/completion.h>
15#include <linux/device.h>
16#include <linux/i2c.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/sched.h>
25
26/* I2C Registers */
27#define I2C_OFS_IICACT0 0x00 /* start */
28#define I2C_OFS_IIC0 0x04 /* shift */
29#define I2C_OFS_IICC0 0x08 /* control */
30#define I2C_OFS_SVA0 0x0c /* slave address */
31#define I2C_OFS_IICCL0 0x10 /* clock select */
32#define I2C_OFS_IICX0 0x14 /* extension */
33#define I2C_OFS_IICS0 0x18 /* status */
34#define I2C_OFS_IICSE0 0x1c /* status For emulation */
35#define I2C_OFS_IICF0 0x20 /* IIC flag */
36
37/* I2C IICACT0 Masks */
38#define I2C_BIT_IICE0 0x0001
39
40/* I2C IICC0 Masks */
41#define I2C_BIT_LREL0 0x0040
42#define I2C_BIT_WREL0 0x0020
43#define I2C_BIT_SPIE0 0x0010
44#define I2C_BIT_WTIM0 0x0008
45#define I2C_BIT_ACKE0 0x0004
46#define I2C_BIT_STT0 0x0002
47#define I2C_BIT_SPT0 0x0001
48
49/* I2C IICCL0 Masks */
50#define I2C_BIT_SMC0 0x0008
51#define I2C_BIT_DFC0 0x0004
52
53/* I2C IICSE0 Masks */
54#define I2C_BIT_MSTS0 0x0080
55#define I2C_BIT_ALD0 0x0040
56#define I2C_BIT_EXC0 0x0020
57#define I2C_BIT_COI0 0x0010
58#define I2C_BIT_TRC0 0x0008
59#define I2C_BIT_ACKD0 0x0004
60#define I2C_BIT_STD0 0x0002
61#define I2C_BIT_SPD0 0x0001
62
63/* I2C IICF0 Masks */
64#define I2C_BIT_STCF 0x0080
65#define I2C_BIT_IICBSY 0x0040
66#define I2C_BIT_STCEN 0x0002
67#define I2C_BIT_IICRSV 0x0001
68
69struct em_i2c_device {
70 void __iomem *base;
71 struct i2c_adapter adap;
72 struct completion msg_done;
73 struct clk *sclk;
74 struct i2c_client *slave;
75};
76
77static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg)
78{
79 writeb((readb(priv->base + reg) & ~clear) | set, priv->base + reg);
80}
81
82static int em_i2c_wait_for_event(struct em_i2c_device *priv)
83{
84 unsigned long time_left;
85 int status;
86
87 reinit_completion(&priv->msg_done);
88
89 time_left = wait_for_completion_timeout(&priv->msg_done, priv->adap.timeout);
90
91 if (!time_left)
92 return -ETIMEDOUT;
93
94 status = readb(priv->base + I2C_OFS_IICSE0);
95 return status & I2C_BIT_ALD0 ? -EAGAIN : status;
96}
97
98static void em_i2c_stop(struct em_i2c_device *priv)
99{
100 /* Send Stop condition */
101 em_clear_set_bit(priv, 0, I2C_BIT_SPT0 | I2C_BIT_SPIE0, I2C_OFS_IICC0);
102
103 /* Wait for stop condition */
104 em_i2c_wait_for_event(priv);
105}
106
107static void em_i2c_reset(struct i2c_adapter *adap)
108{
109 struct em_i2c_device *priv = i2c_get_adapdata(adap);
110 int retr;
111
112 /* If I2C active */
113 if (readb(priv->base + I2C_OFS_IICACT0) & I2C_BIT_IICE0) {
114 /* Disable I2C operation */
115 writeb(0, priv->base + I2C_OFS_IICACT0);
116
117 retr = 1000;
118 while (readb(priv->base + I2C_OFS_IICACT0) == 1 && retr)
119 retr--;
120 WARN_ON(retr == 0);
121 }
122
123 /* Transfer mode set */
124 writeb(I2C_BIT_DFC0, priv->base + I2C_OFS_IICCL0);
125
126 /* Can Issue start without detecting a stop, Reservation disabled. */
127 writeb(I2C_BIT_STCEN | I2C_BIT_IICRSV, priv->base + I2C_OFS_IICF0);
128
129 /* I2C enable, 9 bit interrupt mode */
130 writeb(I2C_BIT_WTIM0, priv->base + I2C_OFS_IICC0);
131
132 /* Enable I2C operation */
133 writeb(I2C_BIT_IICE0, priv->base + I2C_OFS_IICACT0);
134
135 retr = 1000;
136 while (readb(priv->base + I2C_OFS_IICACT0) == 0 && retr)
137 retr--;
138 WARN_ON(retr == 0);
139}
140
141static int __em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
142 int stop)
143{
144 struct em_i2c_device *priv = i2c_get_adapdata(adap);
145 int count, status, read = !!(msg->flags & I2C_M_RD);
146
147 /* Send start condition */
148 em_clear_set_bit(priv, 0, I2C_BIT_ACKE0 | I2C_BIT_WTIM0, I2C_OFS_IICC0);
149 em_clear_set_bit(priv, 0, I2C_BIT_STT0, I2C_OFS_IICC0);
150
151 /* Send slave address and R/W type */
152 writeb((msg->addr << 1) | read, priv->base + I2C_OFS_IIC0);
153
154 /* Wait for transaction */
155 status = em_i2c_wait_for_event(priv);
156 if (status < 0)
157 goto out_reset;
158
159 /* Received NACK (result of setting slave address and R/W) */
160 if (!(status & I2C_BIT_ACKD0)) {
161 em_i2c_stop(priv);
162 goto out;
163 }
164
165 /* Extra setup for read transactions */
166 if (read) {
167 /* 8 bit interrupt mode */
168 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, I2C_OFS_IICC0);
169 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, I2C_OFS_IICC0);
170
171 /* Wait for transaction */
172 status = em_i2c_wait_for_event(priv);
173 if (status < 0)
174 goto out_reset;
175 }
176
177 /* Send / receive data */
178 for (count = 0; count < msg->len; count++) {
179 if (read) { /* Read transaction */
180 msg->buf[count] = readb(priv->base + I2C_OFS_IIC0);
181 em_clear_set_bit(priv, 0, I2C_BIT_WREL0, I2C_OFS_IICC0);
182
183 } else { /* Write transaction */
184 /* Received NACK */
185 if (!(status & I2C_BIT_ACKD0)) {
186 em_i2c_stop(priv);
187 goto out;
188 }
189
190 /* Write data */
191 writeb(msg->buf[count], priv->base + I2C_OFS_IIC0);
192 }
193
194 /* Wait for R/W transaction */
195 status = em_i2c_wait_for_event(priv);
196 if (status < 0)
197 goto out_reset;
198 }
199
200 if (stop)
201 em_i2c_stop(priv);
202
203 return count;
204
205out_reset:
206 em_i2c_reset(adap);
207out:
208 return status < 0 ? status : -ENXIO;
209}
210
211static int em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
212 int num)
213{
214 struct em_i2c_device *priv = i2c_get_adapdata(adap);
215 int ret, i;
216
217 if (readb(priv->base + I2C_OFS_IICF0) & I2C_BIT_IICBSY)
218 return -EAGAIN;
219
220 for (i = 0; i < num; i++) {
221 ret = __em_i2c_xfer(adap, &msgs[i], (i == (num - 1)));
222 if (ret < 0)
223 return ret;
224 }
225
226 /* I2C transfer completed */
227 return num;
228}
229
230static bool em_i2c_slave_irq(struct em_i2c_device *priv)
231{
232 u8 status, value;
233 enum i2c_slave_event event;
234 int ret;
235
236 if (!priv->slave)
237 return false;
238
239 status = readb(priv->base + I2C_OFS_IICSE0);
240
241 /* Extension code, do not participate */
242 if (status & I2C_BIT_EXC0) {
243 em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
244 return true;
245 }
246
247 /* Stop detected, we don't know if it's for slave or master */
248 if (status & I2C_BIT_SPD0) {
249 /* Notify slave device */
250 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
251 /* Pretend we did not handle the interrupt */
252 return false;
253 }
254
255 /* Only handle interrupts addressed to us */
256 if (!(status & I2C_BIT_COI0))
257 return false;
258
259 /* Enable stop interrupts */
260 em_clear_set_bit(priv, 0, I2C_BIT_SPIE0, I2C_OFS_IICC0);
261
262 /* Transmission or Reception */
263 if (status & I2C_BIT_TRC0) {
264 if (status & I2C_BIT_ACKD0) {
265 /* 9 bit interrupt mode */
266 em_clear_set_bit(priv, 0, I2C_BIT_WTIM0, I2C_OFS_IICC0);
267
268 /* Send data */
269 event = status & I2C_BIT_STD0 ?
270 I2C_SLAVE_READ_REQUESTED :
271 I2C_SLAVE_READ_PROCESSED;
272 i2c_slave_event(priv->slave, event, &value);
273 writeb(value, priv->base + I2C_OFS_IIC0);
274 } else {
275 /* NACK, stop transmitting */
276 em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
277 }
278 } else {
279 /* 8 bit interrupt mode */
280 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0,
281 I2C_OFS_IICC0);
282 em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0,
283 I2C_OFS_IICC0);
284
285 if (status & I2C_BIT_STD0) {
286 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED,
287 &value);
288 } else {
289 /* Recv data */
290 value = readb(priv->base + I2C_OFS_IIC0);
291 ret = i2c_slave_event(priv->slave,
292 I2C_SLAVE_WRITE_RECEIVED, &value);
293 if (ret < 0)
294 em_clear_set_bit(priv, I2C_BIT_ACKE0, 0,
295 I2C_OFS_IICC0);
296 }
297 }
298
299 return true;
300}
301
302static irqreturn_t em_i2c_irq_handler(int this_irq, void *dev_id)
303{
304 struct em_i2c_device *priv = dev_id;
305
306 if (em_i2c_slave_irq(priv))
307 return IRQ_HANDLED;
308
309 complete(&priv->msg_done);
310
311 return IRQ_HANDLED;
312}
313
314static u32 em_i2c_func(struct i2c_adapter *adap)
315{
316 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE;
317}
318
319static int em_i2c_reg_slave(struct i2c_client *slave)
320{
321 struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter);
322
323 if (priv->slave)
324 return -EBUSY;
325
326 if (slave->flags & I2C_CLIENT_TEN)
327 return -EAFNOSUPPORT;
328
329 priv->slave = slave;
330
331 /* Set slave address */
332 writeb(slave->addr << 1, priv->base + I2C_OFS_SVA0);
333
334 return 0;
335}
336
337static int em_i2c_unreg_slave(struct i2c_client *slave)
338{
339 struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter);
340
341 WARN_ON(!priv->slave);
342
343 writeb(0, priv->base + I2C_OFS_SVA0);
344
345 priv->slave = NULL;
346
347 return 0;
348}
349
350static struct i2c_algorithm em_i2c_algo = {
351 .master_xfer = em_i2c_xfer,
352 .functionality = em_i2c_func,
353 .reg_slave = em_i2c_reg_slave,
354 .unreg_slave = em_i2c_unreg_slave,
355};
356
357static int em_i2c_probe(struct platform_device *pdev)
358{
359 struct em_i2c_device *priv;
360 struct resource *r;
361 int irq, ret;
362
363 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
364 if (!priv)
365 return -ENOMEM;
366
367 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
368 priv->base = devm_ioremap_resource(&pdev->dev, r);
369 if (IS_ERR(priv->base))
370 return PTR_ERR(priv->base);
371
372 strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
373
374 priv->sclk = devm_clk_get(&pdev->dev, "sclk");
375 if (IS_ERR(priv->sclk))
376 return PTR_ERR(priv->sclk);
377
378 clk_prepare_enable(priv->sclk);
379
380 priv->adap.timeout = msecs_to_jiffies(100);
381 priv->adap.retries = 5;
382 priv->adap.dev.parent = &pdev->dev;
383 priv->adap.algo = &em_i2c_algo;
384 priv->adap.owner = THIS_MODULE;
385 priv->adap.dev.of_node = pdev->dev.of_node;
386
387 init_completion(&priv->msg_done);
388
389 platform_set_drvdata(pdev, priv);
390 i2c_set_adapdata(&priv->adap, priv);
391
392 em_i2c_reset(&priv->adap);
393
394 irq = platform_get_irq(pdev, 0);
395 ret = devm_request_irq(&pdev->dev, irq, em_i2c_irq_handler, 0,
396 "em_i2c", priv);
397 if (ret)
398 goto err_clk;
399
400 ret = i2c_add_adapter(&priv->adap);
401
402 if (ret)
403 goto err_clk;
404
405 dev_info(&pdev->dev, "Added i2c controller %d, irq %d\n", priv->adap.nr, irq);
406
407 return 0;
408
409err_clk:
410 clk_disable_unprepare(priv->sclk);
411 return ret;
412}
413
414static int em_i2c_remove(struct platform_device *dev)
415{
416 struct em_i2c_device *priv = platform_get_drvdata(dev);
417
418 i2c_del_adapter(&priv->adap);
419 clk_disable_unprepare(priv->sclk);
420
421 return 0;
422}
423
424static const struct of_device_id em_i2c_ids[] = {
425 { .compatible = "renesas,iic-emev2", },
426 { }
427};
428
429static struct platform_driver em_i2c_driver = {
430 .probe = em_i2c_probe,
431 .remove = em_i2c_remove,
432 .driver = {
433 .name = "em-i2c",
434 .of_match_table = em_i2c_ids,
435 }
436};
437module_platform_driver(em_i2c_driver);
438
439MODULE_DESCRIPTION("EMEV2 I2C bus driver");
440MODULE_AUTHOR("Ian Molton and Wolfram Sang <wsa@sang-engineering.com>");
441MODULE_LICENSE("GPL v2");
442MODULE_DEVICE_TABLE(of, em_i2c_ids);