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1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (C) 2008-2009 The GameCube Linux Team
3// Copyright (C) 2008,2009 Albert Herranz
4// Copyright (C) 2017-2018 Jonathan Neuschäfer
5//
6// Nintendo Wii (Hollywood) GPIO driver
7
8#include <linux/gpio/driver.h>
9#include <linux/io.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_platform.h>
14#include <linux/slab.h>
15
16/*
17 * Register names and offsets courtesy of WiiBrew:
18 * https://wiibrew.org/wiki/Hardware/Hollywood_GPIOs
19 *
20 * Note that for most registers, there are two versions:
21 * - HW_GPIOB_* Is always accessible by the Broadway PowerPC core, but does
22 * always give access to all GPIO lines
23 * - HW_GPIO_* Is only accessible by the Broadway PowerPC code if the memory
24 * firewall (AHBPROT) in the Hollywood chipset has been configured to allow
25 * such access.
26 *
27 * The ownership of each GPIO line can be configured in the HW_GPIO_OWNER
28 * register: A one bit configures the line for access via the HW_GPIOB_*
29 * registers, a zero bit indicates access via HW_GPIO_*. This driver uses
30 * HW_GPIOB_*.
31 */
32#define HW_GPIOB_OUT 0x00
33#define HW_GPIOB_DIR 0x04
34#define HW_GPIOB_IN 0x08
35#define HW_GPIOB_INTLVL 0x0c
36#define HW_GPIOB_INTFLAG 0x10
37#define HW_GPIOB_INTMASK 0x14
38#define HW_GPIOB_INMIR 0x18
39#define HW_GPIO_ENABLE 0x1c
40#define HW_GPIO_OUT 0x20
41#define HW_GPIO_DIR 0x24
42#define HW_GPIO_IN 0x28
43#define HW_GPIO_INTLVL 0x2c
44#define HW_GPIO_INTFLAG 0x30
45#define HW_GPIO_INTMASK 0x34
46#define HW_GPIO_INMIR 0x38
47#define HW_GPIO_OWNER 0x3c
48
49struct hlwd_gpio {
50 struct gpio_chip gpioc;
51 struct irq_chip irqc;
52 void __iomem *regs;
53 int irq;
54 u32 edge_emulation;
55 u32 rising_edge, falling_edge;
56};
57
58static void hlwd_gpio_irqhandler(struct irq_desc *desc)
59{
60 struct hlwd_gpio *hlwd =
61 gpiochip_get_data(irq_desc_get_handler_data(desc));
62 struct irq_chip *chip = irq_desc_get_chip(desc);
63 unsigned long flags;
64 unsigned long pending;
65 int hwirq;
66 u32 emulated_pending;
67
68 raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
69 pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
70 pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
71
72 /* Treat interrupts due to edge trigger emulation separately */
73 emulated_pending = hlwd->edge_emulation & pending;
74 pending &= ~emulated_pending;
75 if (emulated_pending) {
76 u32 level, rising, falling;
77
78 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
79 rising = level & emulated_pending;
80 falling = ~level & emulated_pending;
81
82 /* Invert the levels */
83 iowrite32be(level ^ emulated_pending,
84 hlwd->regs + HW_GPIOB_INTLVL);
85
86 /* Ack all emulated-edge interrupts */
87 iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
88
89 /* Signal interrupts only on the correct edge */
90 rising &= hlwd->rising_edge;
91 falling &= hlwd->falling_edge;
92
93 /* Mark emulated interrupts as pending */
94 pending |= rising | falling;
95 }
96 raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
97
98 chained_irq_enter(chip, desc);
99
100 for_each_set_bit(hwirq, &pending, 32)
101 generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);
102
103 chained_irq_exit(chip, desc);
104}
105
106static void hlwd_gpio_irq_ack(struct irq_data *data)
107{
108 struct hlwd_gpio *hlwd =
109 gpiochip_get_data(irq_data_get_irq_chip_data(data));
110
111 iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
112}
113
114static void hlwd_gpio_irq_mask(struct irq_data *data)
115{
116 struct hlwd_gpio *hlwd =
117 gpiochip_get_data(irq_data_get_irq_chip_data(data));
118 unsigned long flags;
119 u32 mask;
120
121 raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
122 mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
123 mask &= ~BIT(data->hwirq);
124 iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
125 raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
126}
127
128static void hlwd_gpio_irq_unmask(struct irq_data *data)
129{
130 struct hlwd_gpio *hlwd =
131 gpiochip_get_data(irq_data_get_irq_chip_data(data));
132 unsigned long flags;
133 u32 mask;
134
135 raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
136 mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
137 mask |= BIT(data->hwirq);
138 iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
139 raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
140}
141
142static void hlwd_gpio_irq_enable(struct irq_data *data)
143{
144 hlwd_gpio_irq_ack(data);
145 hlwd_gpio_irq_unmask(data);
146}
147
148static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
149 unsigned int flow_type)
150{
151 u32 level, state;
152
153 /* Set the trigger level to the inactive level */
154 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
155 state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
156 level &= ~BIT(hwirq);
157 level |= state ^ BIT(hwirq);
158 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
159
160 hlwd->edge_emulation |= BIT(hwirq);
161 hlwd->rising_edge &= ~BIT(hwirq);
162 hlwd->falling_edge &= ~BIT(hwirq);
163 if (flow_type & IRQ_TYPE_EDGE_RISING)
164 hlwd->rising_edge |= BIT(hwirq);
165 if (flow_type & IRQ_TYPE_EDGE_FALLING)
166 hlwd->falling_edge |= BIT(hwirq);
167}
168
169static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
170{
171 struct hlwd_gpio *hlwd =
172 gpiochip_get_data(irq_data_get_irq_chip_data(data));
173 unsigned long flags;
174 u32 level;
175
176 raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
177
178 hlwd->edge_emulation &= ~BIT(data->hwirq);
179
180 switch (flow_type) {
181 case IRQ_TYPE_LEVEL_HIGH:
182 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
183 level |= BIT(data->hwirq);
184 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
185 break;
186 case IRQ_TYPE_LEVEL_LOW:
187 level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
188 level &= ~BIT(data->hwirq);
189 iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
190 break;
191 case IRQ_TYPE_EDGE_RISING:
192 case IRQ_TYPE_EDGE_FALLING:
193 case IRQ_TYPE_EDGE_BOTH:
194 hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
195 break;
196 default:
197 raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
198 return -EINVAL;
199 }
200
201 raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
202 return 0;
203}
204
205static int hlwd_gpio_probe(struct platform_device *pdev)
206{
207 struct hlwd_gpio *hlwd;
208 u32 ngpios;
209 int res;
210
211 hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);
212 if (!hlwd)
213 return -ENOMEM;
214
215 hlwd->regs = devm_platform_ioremap_resource(pdev, 0);
216 if (IS_ERR(hlwd->regs))
217 return PTR_ERR(hlwd->regs);
218
219 /*
220 * Claim all GPIOs using the OWNER register. This will not work on
221 * systems where the AHBPROT memory firewall hasn't been configured to
222 * permit PPC access to HW_GPIO_*.
223 *
224 * Note that this has to happen before bgpio_init reads the
225 * HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong
226 * values.
227 */
228 iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);
229
230 res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,
231 hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,
232 NULL, hlwd->regs + HW_GPIOB_DIR, NULL,
233 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
234 if (res < 0) {
235 dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res);
236 return res;
237 }
238
239 res = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios);
240 if (res)
241 ngpios = 32;
242 hlwd->gpioc.ngpio = ngpios;
243
244 /* Mask and ack all interrupts */
245 iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
246 iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
247
248 /*
249 * If this GPIO controller is not marked as an interrupt controller in
250 * the DT, skip interrupt support.
251 */
252 if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
253 struct gpio_irq_chip *girq;
254
255 hlwd->irq = platform_get_irq(pdev, 0);
256 if (hlwd->irq < 0) {
257 dev_info(&pdev->dev, "platform_get_irq returned %d\n",
258 hlwd->irq);
259 return hlwd->irq;
260 }
261
262 hlwd->irqc.name = dev_name(&pdev->dev);
263 hlwd->irqc.irq_mask = hlwd_gpio_irq_mask;
264 hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask;
265 hlwd->irqc.irq_enable = hlwd_gpio_irq_enable;
266 hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type;
267
268 girq = &hlwd->gpioc.irq;
269 girq->chip = &hlwd->irqc;
270 girq->parent_handler = hlwd_gpio_irqhandler;
271 girq->num_parents = 1;
272 girq->parents = devm_kcalloc(&pdev->dev, 1,
273 sizeof(*girq->parents),
274 GFP_KERNEL);
275 if (!girq->parents)
276 return -ENOMEM;
277 girq->parents[0] = hlwd->irq;
278 girq->default_type = IRQ_TYPE_NONE;
279 girq->handler = handle_level_irq;
280 }
281
282 return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
283}
284
285static const struct of_device_id hlwd_gpio_match[] = {
286 { .compatible = "nintendo,hollywood-gpio", },
287 {},
288};
289MODULE_DEVICE_TABLE(of, hlwd_gpio_match);
290
291static struct platform_driver hlwd_gpio_driver = {
292 .driver = {
293 .name = "gpio-hlwd",
294 .of_match_table = hlwd_gpio_match,
295 },
296 .probe = hlwd_gpio_probe,
297};
298module_platform_driver(hlwd_gpio_driver);
299
300MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
301MODULE_DESCRIPTION("Nintendo Wii GPIO driver");
302MODULE_LICENSE("GPL");