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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) MIPS Technologies, Inc.
8 * written by Ralf Baechle <ralf@linux-mips.org>
9 */
10#ifndef _ASM_HAZARDS_H
11#define _ASM_HAZARDS_H
12
13#include <linux/stringify.h>
14#include <asm/compiler.h>
15
16#define ___ssnop \
17 sll $0, $0, 1
18
19#define ___ehb \
20 sll $0, $0, 3
21
22/*
23 * TLB hazards
24 */
25#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
26 defined(CONFIG_CPU_MIPSR6)) && \
27 !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
28
29/*
30 * MIPSR2 defines ehb for hazard avoidance
31 */
32
33#define __mtc0_tlbw_hazard \
34 ___ehb
35
36#define __mtc0_tlbr_hazard \
37 ___ehb
38
39#define __tlbw_use_hazard \
40 ___ehb
41
42#define __tlb_read_hazard \
43 ___ehb
44
45#define __tlb_probe_hazard \
46 ___ehb
47
48#define __irq_enable_hazard \
49 ___ehb
50
51#define __irq_disable_hazard \
52 ___ehb
53
54#define __back_to_back_c0_hazard \
55 ___ehb
56
57/*
58 * gcc has a tradition of misscompiling the previous construct using the
59 * address of a label as argument to inline assembler. Gas otoh has the
60 * annoying difference between la and dla which are only usable for 32-bit
61 * rsp. 64-bit code, so can't be used without conditional compilation.
62 * The alternative is switching the assembler to 64-bit code which happens
63 * to work right even for 32-bit code...
64 */
65#define instruction_hazard() \
66do { \
67 unsigned long tmp; \
68 \
69 __asm__ __volatile__( \
70 " .set push \n" \
71 " .set "MIPS_ISA_LEVEL" \n" \
72 " dla %0, 1f \n" \
73 " jr.hb %0 \n" \
74 " .set pop \n" \
75 "1: \n" \
76 : "=r" (tmp)); \
77} while (0)
78
79#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
80 defined(CONFIG_CPU_BMIPS)
81
82/*
83 * These are slightly complicated by the fact that we guarantee R1 kernels to
84 * run fine on R2 processors.
85 */
86
87#define __mtc0_tlbw_hazard \
88 ___ssnop; \
89 ___ssnop; \
90 ___ehb
91
92#define __mtc0_tlbr_hazard \
93 ___ssnop; \
94 ___ssnop; \
95 ___ehb
96
97#define __tlbw_use_hazard \
98 ___ssnop; \
99 ___ssnop; \
100 ___ssnop; \
101 ___ehb
102
103#define __tlb_read_hazard \
104 ___ssnop; \
105 ___ssnop; \
106 ___ssnop; \
107 ___ehb
108
109#define __tlb_probe_hazard \
110 ___ssnop; \
111 ___ssnop; \
112 ___ssnop; \
113 ___ehb
114
115#define __irq_enable_hazard \
116 ___ssnop; \
117 ___ssnop; \
118 ___ssnop; \
119 ___ehb
120
121#define __irq_disable_hazard \
122 ___ssnop; \
123 ___ssnop; \
124 ___ssnop; \
125 ___ehb
126
127#define __back_to_back_c0_hazard \
128 ___ssnop; \
129 ___ssnop; \
130 ___ssnop; \
131 ___ehb
132
133/*
134 * gcc has a tradition of misscompiling the previous construct using the
135 * address of a label as argument to inline assembler. Gas otoh has the
136 * annoying difference between la and dla which are only usable for 32-bit
137 * rsp. 64-bit code, so can't be used without conditional compilation.
138 * The alternative is switching the assembler to 64-bit code which happens
139 * to work right even for 32-bit code...
140 */
141#define __instruction_hazard() \
142do { \
143 unsigned long tmp; \
144 \
145 __asm__ __volatile__( \
146 " .set push \n" \
147 " .set mips64r2 \n" \
148 " dla %0, 1f \n" \
149 " jr.hb %0 \n" \
150 " .set pop \n" \
151 "1: \n" \
152 : "=r" (tmp)); \
153} while (0)
154
155#define instruction_hazard() \
156do { \
157 if (cpu_has_mips_r2_r6) \
158 __instruction_hazard(); \
159} while (0)
160
161#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
162 defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \
163 defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500)
164
165/*
166 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
167 */
168
169#define __mtc0_tlbw_hazard
170
171#define __mtc0_tlbr_hazard
172
173#define __tlbw_use_hazard
174
175#define __tlb_read_hazard
176
177#define __tlb_probe_hazard
178
179#define __irq_enable_hazard
180
181#define __irq_disable_hazard
182
183#define __back_to_back_c0_hazard
184
185#define instruction_hazard() do { } while (0)
186
187#elif defined(CONFIG_CPU_SB1)
188
189/*
190 * Mostly like R4000 for historic reasons
191 */
192#define __mtc0_tlbw_hazard
193
194#define __mtc0_tlbr_hazard
195
196#define __tlbw_use_hazard
197
198#define __tlb_read_hazard
199
200#define __tlb_probe_hazard
201
202#define __irq_enable_hazard
203
204#define __irq_disable_hazard \
205 ___ssnop; \
206 ___ssnop; \
207 ___ssnop
208
209#define __back_to_back_c0_hazard
210
211#define instruction_hazard() do { } while (0)
212
213#else
214
215/*
216 * Finally the catchall case for all other processors including R4000, R4400,
217 * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
218 *
219 * The taken branch will result in a two cycle penalty for the two killed
220 * instructions on R4000 / R4400. Other processors only have a single cycle
221 * hazard so this is nice trick to have an optimal code for a range of
222 * processors.
223 */
224#define __mtc0_tlbw_hazard \
225 nop; \
226 nop
227
228#define __mtc0_tlbr_hazard \
229 nop; \
230 nop
231
232#define __tlbw_use_hazard \
233 nop; \
234 nop; \
235 nop
236
237#define __tlb_read_hazard \
238 nop; \
239 nop; \
240 nop
241
242#define __tlb_probe_hazard \
243 nop; \
244 nop; \
245 nop
246
247#define __irq_enable_hazard \
248 ___ssnop; \
249 ___ssnop; \
250 ___ssnop
251
252#define __irq_disable_hazard \
253 nop; \
254 nop; \
255 nop
256
257#define __back_to_back_c0_hazard \
258 ___ssnop; \
259 ___ssnop; \
260 ___ssnop
261
262#define instruction_hazard() do { } while (0)
263
264#endif
265
266
267/* FPU hazards */
268
269#if defined(CONFIG_CPU_SB1)
270
271#define __enable_fpu_hazard \
272 .set push; \
273 .set mips64; \
274 .set noreorder; \
275 ___ssnop; \
276 bnezl $0, .+4; \
277 ___ssnop; \
278 .set pop
279
280#define __disable_fpu_hazard
281
282#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
283 defined(CONFIG_CPU_MIPSR6)
284
285#define __enable_fpu_hazard \
286 ___ehb
287
288#define __disable_fpu_hazard \
289 ___ehb
290
291#else
292
293#define __enable_fpu_hazard \
294 nop; \
295 nop; \
296 nop; \
297 nop
298
299#define __disable_fpu_hazard \
300 ___ehb
301
302#endif
303
304#ifdef __ASSEMBLY__
305
306#define _ssnop ___ssnop
307#define _ehb ___ehb
308#define mtc0_tlbw_hazard __mtc0_tlbw_hazard
309#define mtc0_tlbr_hazard __mtc0_tlbr_hazard
310#define tlbw_use_hazard __tlbw_use_hazard
311#define tlb_read_hazard __tlb_read_hazard
312#define tlb_probe_hazard __tlb_probe_hazard
313#define irq_enable_hazard __irq_enable_hazard
314#define irq_disable_hazard __irq_disable_hazard
315#define back_to_back_c0_hazard __back_to_back_c0_hazard
316#define enable_fpu_hazard __enable_fpu_hazard
317#define disable_fpu_hazard __disable_fpu_hazard
318
319#else
320
321#define _ssnop() \
322do { \
323 __asm__ __volatile__( \
324 __stringify(___ssnop) \
325 ); \
326} while (0)
327
328#define _ehb() \
329do { \
330 __asm__ __volatile__( \
331 __stringify(___ehb) \
332 ); \
333} while (0)
334
335
336#define mtc0_tlbw_hazard() \
337do { \
338 __asm__ __volatile__( \
339 __stringify(__mtc0_tlbw_hazard) \
340 ); \
341} while (0)
342
343
344#define mtc0_tlbr_hazard() \
345do { \
346 __asm__ __volatile__( \
347 __stringify(__mtc0_tlbr_hazard) \
348 ); \
349} while (0)
350
351
352#define tlbw_use_hazard() \
353do { \
354 __asm__ __volatile__( \
355 __stringify(__tlbw_use_hazard) \
356 ); \
357} while (0)
358
359
360#define tlb_read_hazard() \
361do { \
362 __asm__ __volatile__( \
363 __stringify(__tlb_read_hazard) \
364 ); \
365} while (0)
366
367
368#define tlb_probe_hazard() \
369do { \
370 __asm__ __volatile__( \
371 __stringify(__tlb_probe_hazard) \
372 ); \
373} while (0)
374
375
376#define irq_enable_hazard() \
377do { \
378 __asm__ __volatile__( \
379 __stringify(__irq_enable_hazard) \
380 ); \
381} while (0)
382
383
384#define irq_disable_hazard() \
385do { \
386 __asm__ __volatile__( \
387 __stringify(__irq_disable_hazard) \
388 ); \
389} while (0)
390
391
392#define back_to_back_c0_hazard() \
393do { \
394 __asm__ __volatile__( \
395 __stringify(__back_to_back_c0_hazard) \
396 ); \
397} while (0)
398
399
400#define enable_fpu_hazard() \
401do { \
402 __asm__ __volatile__( \
403 __stringify(__enable_fpu_hazard) \
404 ); \
405} while (0)
406
407
408#define disable_fpu_hazard() \
409do { \
410 __asm__ __volatile__( \
411 __stringify(__disable_fpu_hazard) \
412 ); \
413} while (0)
414
415/*
416 * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
417 */
418extern void mips_ihb(void);
419
420#endif /* __ASSEMBLY__ */
421
422#endif /* _ASM_HAZARDS_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) MIPS Technologies, Inc.
8 * written by Ralf Baechle <ralf@linux-mips.org>
9 */
10#ifndef _ASM_HAZARDS_H
11#define _ASM_HAZARDS_H
12
13#include <linux/stringify.h>
14#include <asm/compiler.h>
15
16#define ___ssnop \
17 sll $0, $0, 1
18
19#define ___ehb \
20 sll $0, $0, 3
21
22/*
23 * TLB hazards
24 */
25#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
26
27/*
28 * MIPSR2 defines ehb for hazard avoidance
29 */
30
31#define __mtc0_tlbw_hazard \
32 ___ehb
33
34#define __mtc0_tlbr_hazard \
35 ___ehb
36
37#define __tlbw_use_hazard \
38 ___ehb
39
40#define __tlb_read_hazard \
41 ___ehb
42
43#define __tlb_probe_hazard \
44 ___ehb
45
46#define __irq_enable_hazard \
47 ___ehb
48
49#define __irq_disable_hazard \
50 ___ehb
51
52#define __back_to_back_c0_hazard \
53 ___ehb
54
55/*
56 * gcc has a tradition of misscompiling the previous construct using the
57 * address of a label as argument to inline assembler. Gas otoh has the
58 * annoying difference between la and dla which are only usable for 32-bit
59 * rsp. 64-bit code, so can't be used without conditional compilation.
60 * The alterantive is switching the assembler to 64-bit code which happens
61 * to work right even for 32-bit code ...
62 */
63#define instruction_hazard() \
64do { \
65 unsigned long tmp; \
66 \
67 __asm__ __volatile__( \
68 " .set "MIPS_ISA_LEVEL" \n" \
69 " dla %0, 1f \n" \
70 " jr.hb %0 \n" \
71 " .set mips0 \n" \
72 "1: \n" \
73 : "=r" (tmp)); \
74} while (0)
75
76#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
77 defined(CONFIG_CPU_BMIPS)
78
79/*
80 * These are slightly complicated by the fact that we guarantee R1 kernels to
81 * run fine on R2 processors.
82 */
83
84#define __mtc0_tlbw_hazard \
85 ___ssnop; \
86 ___ssnop; \
87 ___ehb
88
89#define __mtc0_tlbr_hazard \
90 ___ssnop; \
91 ___ssnop; \
92 ___ehb
93
94#define __tlbw_use_hazard \
95 ___ssnop; \
96 ___ssnop; \
97 ___ssnop; \
98 ___ehb
99
100#define __tlb_read_hazard \
101 ___ssnop; \
102 ___ssnop; \
103 ___ssnop; \
104 ___ehb
105
106#define __tlb_probe_hazard \
107 ___ssnop; \
108 ___ssnop; \
109 ___ssnop; \
110 ___ehb
111
112#define __irq_enable_hazard \
113 ___ssnop; \
114 ___ssnop; \
115 ___ssnop; \
116 ___ehb
117
118#define __irq_disable_hazard \
119 ___ssnop; \
120 ___ssnop; \
121 ___ssnop; \
122 ___ehb
123
124#define __back_to_back_c0_hazard \
125 ___ssnop; \
126 ___ssnop; \
127 ___ssnop; \
128 ___ehb
129
130/*
131 * gcc has a tradition of misscompiling the previous construct using the
132 * address of a label as argument to inline assembler. Gas otoh has the
133 * annoying difference between la and dla which are only usable for 32-bit
134 * rsp. 64-bit code, so can't be used without conditional compilation.
135 * The alterantive is switching the assembler to 64-bit code which happens
136 * to work right even for 32-bit code ...
137 */
138#define __instruction_hazard() \
139do { \
140 unsigned long tmp; \
141 \
142 __asm__ __volatile__( \
143 " .set mips64r2 \n" \
144 " dla %0, 1f \n" \
145 " jr.hb %0 \n" \
146 " .set mips0 \n" \
147 "1: \n" \
148 : "=r" (tmp)); \
149} while (0)
150
151#define instruction_hazard() \
152do { \
153 if (cpu_has_mips_r2_r6) \
154 __instruction_hazard(); \
155} while (0)
156
157#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
158 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
159 defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
160
161/*
162 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
163 */
164
165#define __mtc0_tlbw_hazard
166
167#define __mtc0_tlbr_hazard
168
169#define __tlbw_use_hazard
170
171#define __tlb_read_hazard
172
173#define __tlb_probe_hazard
174
175#define __irq_enable_hazard
176
177#define __irq_disable_hazard
178
179#define __back_to_back_c0_hazard
180
181#define instruction_hazard() do { } while (0)
182
183#elif defined(CONFIG_CPU_SB1)
184
185/*
186 * Mostly like R4000 for historic reasons
187 */
188#define __mtc0_tlbw_hazard
189
190#define __mtc0_tlbr_hazard
191
192#define __tlbw_use_hazard
193
194#define __tlb_read_hazard
195
196#define __tlb_probe_hazard
197
198#define __irq_enable_hazard
199
200#define __irq_disable_hazard \
201 ___ssnop; \
202 ___ssnop; \
203 ___ssnop
204
205#define __back_to_back_c0_hazard
206
207#define instruction_hazard() do { } while (0)
208
209#else
210
211/*
212 * Finally the catchall case for all other processors including R4000, R4400,
213 * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
214 *
215 * The taken branch will result in a two cycle penalty for the two killed
216 * instructions on R4000 / R4400. Other processors only have a single cycle
217 * hazard so this is nice trick to have an optimal code for a range of
218 * processors.
219 */
220#define __mtc0_tlbw_hazard \
221 nop; \
222 nop
223
224#define __mtc0_tlbr_hazard \
225 nop; \
226 nop
227
228#define __tlbw_use_hazard \
229 nop; \
230 nop; \
231 nop
232
233#define __tlb_read_hazard \
234 nop; \
235 nop; \
236 nop
237
238#define __tlb_probe_hazard \
239 nop; \
240 nop; \
241 nop
242
243#define __irq_enable_hazard \
244 ___ssnop; \
245 ___ssnop; \
246 ___ssnop
247
248#define __irq_disable_hazard \
249 nop; \
250 nop; \
251 nop
252
253#define __back_to_back_c0_hazard \
254 ___ssnop; \
255 ___ssnop; \
256 ___ssnop
257
258#define instruction_hazard() do { } while (0)
259
260#endif
261
262
263/* FPU hazards */
264
265#if defined(CONFIG_CPU_SB1)
266
267#define __enable_fpu_hazard \
268 .set push; \
269 .set mips64; \
270 .set noreorder; \
271 ___ssnop; \
272 bnezl $0, .+4; \
273 ___ssnop; \
274 .set pop
275
276#define __disable_fpu_hazard
277
278#elif defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
279
280#define __enable_fpu_hazard \
281 ___ehb
282
283#define __disable_fpu_hazard \
284 ___ehb
285
286#else
287
288#define __enable_fpu_hazard \
289 nop; \
290 nop; \
291 nop; \
292 nop
293
294#define __disable_fpu_hazard \
295 ___ehb
296
297#endif
298
299#ifdef __ASSEMBLY__
300
301#define _ssnop ___ssnop
302#define _ehb ___ehb
303#define mtc0_tlbw_hazard __mtc0_tlbw_hazard
304#define mtc0_tlbr_hazard __mtc0_tlbr_hazard
305#define tlbw_use_hazard __tlbw_use_hazard
306#define tlb_read_hazard __tlb_read_hazard
307#define tlb_probe_hazard __tlb_probe_hazard
308#define irq_enable_hazard __irq_enable_hazard
309#define irq_disable_hazard __irq_disable_hazard
310#define back_to_back_c0_hazard __back_to_back_c0_hazard
311#define enable_fpu_hazard __enable_fpu_hazard
312#define disable_fpu_hazard __disable_fpu_hazard
313
314#else
315
316#define _ssnop() \
317do { \
318 __asm__ __volatile__( \
319 __stringify(___ssnop) \
320 ); \
321} while (0)
322
323#define _ehb() \
324do { \
325 __asm__ __volatile__( \
326 __stringify(___ehb) \
327 ); \
328} while (0)
329
330
331#define mtc0_tlbw_hazard() \
332do { \
333 __asm__ __volatile__( \
334 __stringify(__mtc0_tlbw_hazard) \
335 ); \
336} while (0)
337
338
339#define mtc0_tlbr_hazard() \
340do { \
341 __asm__ __volatile__( \
342 __stringify(__mtc0_tlbr_hazard) \
343 ); \
344} while (0)
345
346
347#define tlbw_use_hazard() \
348do { \
349 __asm__ __volatile__( \
350 __stringify(__tlbw_use_hazard) \
351 ); \
352} while (0)
353
354
355#define tlb_read_hazard() \
356do { \
357 __asm__ __volatile__( \
358 __stringify(__tlb_read_hazard) \
359 ); \
360} while (0)
361
362
363#define tlb_probe_hazard() \
364do { \
365 __asm__ __volatile__( \
366 __stringify(__tlb_probe_hazard) \
367 ); \
368} while (0)
369
370
371#define irq_enable_hazard() \
372do { \
373 __asm__ __volatile__( \
374 __stringify(__irq_enable_hazard) \
375 ); \
376} while (0)
377
378
379#define irq_disable_hazard() \
380do { \
381 __asm__ __volatile__( \
382 __stringify(__irq_disable_hazard) \
383 ); \
384} while (0)
385
386
387#define back_to_back_c0_hazard() \
388do { \
389 __asm__ __volatile__( \
390 __stringify(__back_to_back_c0_hazard) \
391 ); \
392} while (0)
393
394
395#define enable_fpu_hazard() \
396do { \
397 __asm__ __volatile__( \
398 __stringify(__enable_fpu_hazard) \
399 ); \
400} while (0)
401
402
403#define disable_fpu_hazard() \
404do { \
405 __asm__ __volatile__( \
406 __stringify(__disable_fpu_hazard) \
407 ); \
408} while (0)
409
410/*
411 * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
412 */
413extern void mips_ihb(void);
414
415#endif /* __ASSEMBLY__ */
416
417#endif /* _ASM_HAZARDS_H */