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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mm/nommu.c
4 *
5 * ARM uCLinux supporting functions.
6 */
7#include <linux/module.h>
8#include <linux/mm.h>
9#include <linux/pagemap.h>
10#include <linux/io.h>
11#include <linux/memblock.h>
12#include <linux/kernel.h>
13
14#include <asm/cacheflush.h>
15#include <asm/cp15.h>
16#include <asm/sections.h>
17#include <asm/page.h>
18#include <asm/setup.h>
19#include <asm/traps.h>
20#include <asm/mach/arch.h>
21#include <asm/cputype.h>
22#include <asm/mpu.h>
23#include <asm/procinfo.h>
24
25#include "mm.h"
26
27unsigned long vectors_base;
28
29/*
30 * empty_zero_page is a special page that is used for
31 * zero-initialized data and COW.
32 */
33struct page *empty_zero_page;
34EXPORT_SYMBOL(empty_zero_page);
35
36#ifdef CONFIG_ARM_MPU
37struct mpu_rgn_info mpu_rgn_info;
38#endif
39
40#ifdef CONFIG_CPU_CP15
41#ifdef CONFIG_CPU_HIGH_VECTOR
42unsigned long setup_vectors_base(void)
43{
44 unsigned long reg = get_cr();
45
46 set_cr(reg | CR_V);
47 return 0xffff0000;
48}
49#else /* CONFIG_CPU_HIGH_VECTOR */
50/* Write exception base address to VBAR */
51static inline void set_vbar(unsigned long val)
52{
53 asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc");
54}
55
56/*
57 * Security extensions, bits[7:4], permitted values,
58 * 0b0000 - not implemented, 0b0001/0b0010 - implemented
59 */
60static inline bool security_extensions_enabled(void)
61{
62 /* Check CPUID Identification Scheme before ID_PFR1 read */
63 if ((read_cpuid_id() & 0x000f0000) == 0x000f0000)
64 return cpuid_feature_extract(CPUID_EXT_PFR1, 4) ||
65 cpuid_feature_extract(CPUID_EXT_PFR1, 20);
66 return 0;
67}
68
69unsigned long setup_vectors_base(void)
70{
71 unsigned long base = 0, reg = get_cr();
72
73 set_cr(reg & ~CR_V);
74 if (security_extensions_enabled()) {
75 if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM))
76 base = CONFIG_DRAM_BASE;
77 set_vbar(base);
78 } else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) {
79 if (CONFIG_DRAM_BASE != 0)
80 pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n");
81 }
82
83 return base;
84}
85#endif /* CONFIG_CPU_HIGH_VECTOR */
86#endif /* CONFIG_CPU_CP15 */
87
88void __init arm_mm_memblock_reserve(void)
89{
90#ifndef CONFIG_CPU_V7M
91 vectors_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vectors_base() : 0;
92 /*
93 * Register the exception vector page.
94 * some architectures which the DRAM is the exception vector to trap,
95 * alloc_page breaks with error, although it is not NULL, but "0."
96 */
97 memblock_reserve(vectors_base, 2 * PAGE_SIZE);
98#else /* ifndef CONFIG_CPU_V7M */
99 /*
100 * There is no dedicated vector page on V7-M. So nothing needs to be
101 * reserved here.
102 */
103#endif
104 /*
105 * In any case, always ensure address 0 is never used as many things
106 * get very confused if 0 is returned as a legitimate address.
107 */
108 memblock_reserve(0, 1);
109}
110
111static void __init adjust_lowmem_bounds_mpu(void)
112{
113 unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA;
114
115 switch (pmsa) {
116 case MMFR0_PMSAv7:
117 pmsav7_adjust_lowmem_bounds();
118 break;
119 case MMFR0_PMSAv8:
120 pmsav8_adjust_lowmem_bounds();
121 break;
122 default:
123 break;
124 }
125}
126
127static void __init mpu_setup(void)
128{
129 unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA;
130
131 switch (pmsa) {
132 case MMFR0_PMSAv7:
133 pmsav7_setup();
134 break;
135 case MMFR0_PMSAv8:
136 pmsav8_setup();
137 break;
138 default:
139 break;
140 }
141}
142
143void __init adjust_lowmem_bounds(void)
144{
145 phys_addr_t end;
146 adjust_lowmem_bounds_mpu();
147 end = memblock_end_of_DRAM();
148 high_memory = __va(end - 1) + 1;
149 memblock_set_current_limit(end);
150}
151
152/*
153 * paging_init() sets up the page tables, initialises the zone memory
154 * maps, and sets up the zero page, bad page and bad page tables.
155 */
156void __init paging_init(const struct machine_desc *mdesc)
157{
158 void *zero_page;
159
160 early_trap_init((void *)vectors_base);
161 mpu_setup();
162
163 /* allocate the zero page. */
164 zero_page = (void *)memblock_alloc(PAGE_SIZE, PAGE_SIZE);
165 if (!zero_page)
166 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
167 __func__, PAGE_SIZE, PAGE_SIZE);
168
169 bootmem_init();
170
171 empty_zero_page = virt_to_page(zero_page);
172 flush_dcache_page(empty_zero_page);
173}
174
175/*
176 * We don't need to do anything here for nommu machines.
177 */
178void setup_mm_for_reboot(void)
179{
180}
181
182void flush_dcache_page(struct page *page)
183{
184 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
185}
186EXPORT_SYMBOL(flush_dcache_page);
187
188void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
189 unsigned long uaddr, void *dst, const void *src,
190 unsigned long len)
191{
192 memcpy(dst, src, len);
193 if (vma->vm_flags & VM_EXEC)
194 __cpuc_coherent_user_range(uaddr, uaddr + len);
195}
196
197void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
198 size_t size, unsigned int mtype)
199{
200 if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
201 return NULL;
202 return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
203}
204EXPORT_SYMBOL(__arm_ioremap_pfn);
205
206void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
207 unsigned int mtype, void *caller)
208{
209 return (void __iomem *)phys_addr;
210}
211
212void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
213
214void __iomem *ioremap(resource_size_t res_cookie, size_t size)
215{
216 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE,
217 __builtin_return_address(0));
218}
219EXPORT_SYMBOL(ioremap);
220
221void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
222{
223 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
224 __builtin_return_address(0));
225}
226EXPORT_SYMBOL(ioremap_cache);
227
228void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
229{
230 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC,
231 __builtin_return_address(0));
232}
233EXPORT_SYMBOL(ioremap_wc);
234
235#ifdef CONFIG_PCI
236
237#include <asm/mach/map.h>
238
239void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size)
240{
241 return arch_ioremap_caller(res_cookie, size, MT_UNCACHED,
242 __builtin_return_address(0));
243}
244EXPORT_SYMBOL_GPL(pci_remap_cfgspace);
245#endif
246
247void *arch_memremap_wb(phys_addr_t phys_addr, size_t size)
248{
249 return (void *)phys_addr;
250}
251
252void iounmap(volatile void __iomem *io_addr)
253{
254}
255EXPORT_SYMBOL(iounmap);
1/*
2 * linux/arch/arm/mm/nommu.c
3 *
4 * ARM uCLinux supporting functions.
5 */
6#include <linux/module.h>
7#include <linux/mm.h>
8#include <linux/pagemap.h>
9#include <linux/io.h>
10#include <linux/memblock.h>
11#include <linux/kernel.h>
12
13#include <asm/cacheflush.h>
14#include <asm/sections.h>
15#include <asm/page.h>
16#include <asm/setup.h>
17#include <asm/traps.h>
18#include <asm/mach/arch.h>
19#include <asm/cputype.h>
20#include <asm/mpu.h>
21#include <asm/procinfo.h>
22
23#include "mm.h"
24
25#ifdef CONFIG_ARM_MPU
26struct mpu_rgn_info mpu_rgn_info;
27
28/* Region number */
29static void rgnr_write(u32 v)
30{
31 asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v));
32}
33
34/* Data-side / unified region attributes */
35
36/* Region access control register */
37static void dracr_write(u32 v)
38{
39 asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v));
40}
41
42/* Region size register */
43static void drsr_write(u32 v)
44{
45 asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v));
46}
47
48/* Region base address register */
49static void drbar_write(u32 v)
50{
51 asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v));
52}
53
54static u32 drbar_read(void)
55{
56 u32 v;
57 asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v));
58 return v;
59}
60/* Optional instruction-side region attributes */
61
62/* I-side Region access control register */
63static void iracr_write(u32 v)
64{
65 asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v));
66}
67
68/* I-side Region size register */
69static void irsr_write(u32 v)
70{
71 asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v));
72}
73
74/* I-side Region base address register */
75static void irbar_write(u32 v)
76{
77 asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v));
78}
79
80static unsigned long irbar_read(void)
81{
82 unsigned long v;
83 asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v));
84 return v;
85}
86
87/* MPU initialisation functions */
88void __init sanity_check_meminfo_mpu(void)
89{
90 phys_addr_t phys_offset = PHYS_OFFSET;
91 phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
92 struct memblock_region *reg;
93 bool first = true;
94 phys_addr_t mem_start;
95 phys_addr_t mem_end;
96
97 for_each_memblock(memory, reg) {
98 if (first) {
99 /*
100 * Initially only use memory continuous from
101 * PHYS_OFFSET */
102 if (reg->base != phys_offset)
103 panic("First memory bank must be contiguous from PHYS_OFFSET");
104
105 mem_start = reg->base;
106 mem_end = reg->base + reg->size;
107 specified_mem_size = reg->size;
108 first = false;
109 } else {
110 /*
111 * memblock auto merges contiguous blocks, remove
112 * all blocks afterwards in one go (we can't remove
113 * blocks separately while iterating)
114 */
115 pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
116 &mem_end, ®->base);
117 memblock_remove(reg->base, 0 - reg->base);
118 break;
119 }
120 }
121
122 /*
123 * MPU has curious alignment requirements: Size must be power of 2, and
124 * region start must be aligned to the region size
125 */
126 if (phys_offset != 0)
127 pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
128
129 /*
130 * Maximum aligned region might overflow phys_addr_t if phys_offset is
131 * 0. Hence we keep everything below 4G until we take the smaller of
132 * the aligned_region_size and rounded_mem_size, one of which is
133 * guaranteed to be smaller than the maximum physical address.
134 */
135 aligned_region_size = (phys_offset - 1) ^ (phys_offset);
136 /* Find the max power-of-two sized region that fits inside our bank */
137 rounded_mem_size = (1 << __fls(specified_mem_size)) - 1;
138
139 /* The actual region size is the smaller of the two */
140 aligned_region_size = aligned_region_size < rounded_mem_size
141 ? aligned_region_size + 1
142 : rounded_mem_size + 1;
143
144 if (aligned_region_size != specified_mem_size) {
145 pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
146 &specified_mem_size, &aligned_region_size);
147 memblock_remove(mem_start + aligned_region_size,
148 specified_mem_size - aligned_region_size);
149
150 mem_end = mem_start + aligned_region_size;
151 }
152
153 pr_debug("MPU Region from %pa size %pa (end %pa))\n",
154 &phys_offset, &aligned_region_size, &mem_end);
155
156}
157
158static int mpu_present(void)
159{
160 return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
161}
162
163static int mpu_max_regions(void)
164{
165 /*
166 * We don't support a different number of I/D side regions so if we
167 * have separate instruction and data memory maps then return
168 * whichever side has a smaller number of supported regions.
169 */
170 u32 dregions, iregions, mpuir;
171 mpuir = read_cpuid(CPUID_MPUIR);
172
173 dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
174
175 /* Check for separate d-side and i-side memory maps */
176 if (mpuir & MPUIR_nU)
177 iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
178
179 /* Use the smallest of the two maxima */
180 return min(dregions, iregions);
181}
182
183static int mpu_iside_independent(void)
184{
185 /* MPUIR.nU specifies whether there is *not* a unified memory map */
186 return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
187}
188
189static int mpu_min_region_order(void)
190{
191 u32 drbar_result, irbar_result;
192 /* We've kept a region free for this probing */
193 rgnr_write(MPU_PROBE_REGION);
194 isb();
195 /*
196 * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
197 * region order
198 */
199 drbar_write(0xFFFFFFFC);
200 drbar_result = irbar_result = drbar_read();
201 drbar_write(0x0);
202 /* If the MPU is non-unified, we use the larger of the two minima*/
203 if (mpu_iside_independent()) {
204 irbar_write(0xFFFFFFFC);
205 irbar_result = irbar_read();
206 irbar_write(0x0);
207 }
208 isb(); /* Ensure that MPU region operations have completed */
209 /* Return whichever result is larger */
210 return __ffs(max(drbar_result, irbar_result));
211}
212
213static int mpu_setup_region(unsigned int number, phys_addr_t start,
214 unsigned int size_order, unsigned int properties)
215{
216 u32 size_data;
217
218 /* We kept a region free for probing resolution of MPU regions*/
219 if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
220 return -ENOENT;
221
222 if (size_order > 32)
223 return -ENOMEM;
224
225 if (size_order < mpu_min_region_order())
226 return -ENOMEM;
227
228 /* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */
229 size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;
230
231 dsb(); /* Ensure all previous data accesses occur with old mappings */
232 rgnr_write(number);
233 isb();
234 drbar_write(start);
235 dracr_write(properties);
236 isb(); /* Propagate properties before enabling region */
237 drsr_write(size_data);
238
239 /* Check for independent I-side registers */
240 if (mpu_iside_independent()) {
241 irbar_write(start);
242 iracr_write(properties);
243 isb();
244 irsr_write(size_data);
245 }
246 isb();
247
248 /* Store region info (we treat i/d side the same, so only store d) */
249 mpu_rgn_info.rgns[number].dracr = properties;
250 mpu_rgn_info.rgns[number].drbar = start;
251 mpu_rgn_info.rgns[number].drsr = size_data;
252 return 0;
253}
254
255/*
256* Set up default MPU regions, doing nothing if there is no MPU
257*/
258void __init mpu_setup(void)
259{
260 int region_err;
261 if (!mpu_present())
262 return;
263
264 region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
265 ilog2(memblock.memory.regions[0].size),
266 MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
267 if (region_err) {
268 panic("MPU region initialization failure! %d", region_err);
269 } else {
270 pr_info("Using ARMv7 PMSA Compliant MPU. "
271 "Region independence: %s, Max regions: %d\n",
272 mpu_iside_independent() ? "Yes" : "No",
273 mpu_max_regions());
274 }
275}
276#else
277static void sanity_check_meminfo_mpu(void) {}
278static void __init mpu_setup(void) {}
279#endif /* CONFIG_ARM_MPU */
280
281void __init arm_mm_memblock_reserve(void)
282{
283#ifndef CONFIG_CPU_V7M
284 /*
285 * Register the exception vector page.
286 * some architectures which the DRAM is the exception vector to trap,
287 * alloc_page breaks with error, although it is not NULL, but "0."
288 */
289 memblock_reserve(CONFIG_VECTORS_BASE, 2 * PAGE_SIZE);
290#else /* ifndef CONFIG_CPU_V7M */
291 /*
292 * There is no dedicated vector page on V7-M. So nothing needs to be
293 * reserved here.
294 */
295#endif
296}
297
298void __init sanity_check_meminfo(void)
299{
300 phys_addr_t end;
301 sanity_check_meminfo_mpu();
302 end = memblock_end_of_DRAM();
303 high_memory = __va(end - 1) + 1;
304 memblock_set_current_limit(end);
305}
306
307/*
308 * paging_init() sets up the page tables, initialises the zone memory
309 * maps, and sets up the zero page, bad page and bad page tables.
310 */
311void __init paging_init(const struct machine_desc *mdesc)
312{
313 early_trap_init((void *)CONFIG_VECTORS_BASE);
314 mpu_setup();
315 bootmem_init();
316}
317
318/*
319 * We don't need to do anything here for nommu machines.
320 */
321void setup_mm_for_reboot(void)
322{
323}
324
325void flush_dcache_page(struct page *page)
326{
327 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
328}
329EXPORT_SYMBOL(flush_dcache_page);
330
331void flush_kernel_dcache_page(struct page *page)
332{
333 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
334}
335EXPORT_SYMBOL(flush_kernel_dcache_page);
336
337void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
338 unsigned long uaddr, void *dst, const void *src,
339 unsigned long len)
340{
341 memcpy(dst, src, len);
342 if (vma->vm_flags & VM_EXEC)
343 __cpuc_coherent_user_range(uaddr, uaddr + len);
344}
345
346void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
347 size_t size, unsigned int mtype)
348{
349 if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
350 return NULL;
351 return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
352}
353EXPORT_SYMBOL(__arm_ioremap_pfn);
354
355void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
356 unsigned int mtype, void *caller)
357{
358 return (void __iomem *)phys_addr;
359}
360
361void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
362
363void __iomem *ioremap(resource_size_t res_cookie, size_t size)
364{
365 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE,
366 __builtin_return_address(0));
367}
368EXPORT_SYMBOL(ioremap);
369
370void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
371{
372 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
373 __builtin_return_address(0));
374}
375EXPORT_SYMBOL(ioremap_cache);
376
377void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
378{
379 return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_WC,
380 __builtin_return_address(0));
381}
382EXPORT_SYMBOL(ioremap_wc);
383
384void __iounmap(volatile void __iomem *addr)
385{
386}
387EXPORT_SYMBOL(__iounmap);
388
389void (*arch_iounmap)(volatile void __iomem *);
390
391void iounmap(volatile void __iomem *addr)
392{
393}
394EXPORT_SYMBOL(iounmap);