1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
  4 */
  5
 
 
 
 
 
  6
  7#ifndef __ASM_ARCH_MXC_COMMON_H__
  8#define __ASM_ARCH_MXC_COMMON_H__
  9
 10#include <linux/reboot.h>
 11
 12struct irq_data;
 13struct platform_device;
 14struct pt_regs;
 15struct clk;
 16struct device_node;
 17enum mxc_cpu_pwr_mode;
 18struct of_device_id;
 19
 
 
 
 20void mx31_map_io(void);
 21void mx35_map_io(void);
 
 22void imx21_init_early(void);
 
 23void imx31_init_early(void);
 24void imx35_init_early(void);
 
 
 
 
 
 25void mx31_init_irq(void);
 26void mx35_init_irq(void);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 27void mxc_set_cpu_type(unsigned int type);
 28void mxc_restart(enum reboot_mode, const char *);
 29void mxc_arch_reset_init(void __iomem *);
 30void imx1_reset_init(void __iomem *);
 31void imx_set_aips(void __iomem *);
 32void imx_aips_allow_unprivileged_access(const char *compat);
 33int mxc_device_init(void);
 34void imx_set_soc_revision(unsigned int rev);
 35void imx_init_revision_from_anatop(void);
 
 36void imx6_enable_rbc(bool enable);
 37void imx_gpc_check_dt(void);
 38void imx_gpc_set_arm_power_in_lpm(bool power_off);
 39void imx_gpc_set_l2_mem_power_in_lpm(bool power_off);
 40void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
 41void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
 42void imx25_pm_init(void);
 43void imx27_pm_init(void);
 44void imx5_pmu_init(void);
 45
 46enum mxc_cpu_pwr_mode {
 47	WAIT_CLOCKED,		/* wfi only */
 48	WAIT_UNCLOCKED,		/* WAIT */
 49	WAIT_UNCLOCKED_POWER_OFF,	/* WAIT + SRPG */
 50	STOP_POWER_ON,		/* just STOP */
 51	STOP_POWER_OFF,		/* STOP + SRPG */
 52};
 53
 54enum ulp_cpu_pwr_mode {
 55	ULP_PM_HSRUN,    /* High speed run mode */
 56	ULP_PM_RUN,      /* Run mode */
 57	ULP_PM_WAIT,     /* Wait mode */
 58	ULP_PM_STOP,     /* Stop mode */
 59	ULP_PM_VLPS,     /* Very low power stop mode */
 60	ULP_PM_VLLS,     /* very low leakage stop mode */
 61};
 62
 
 
 63void imx_enable_cpu(int cpu, bool enable);
 64void imx_set_cpu_jump(int cpu, void *jump_addr);
 65u32 imx_get_cpu_arg(int cpu);
 66void imx_set_cpu_arg(int cpu, u32 arg);
 67#ifdef CONFIG_SMP
 68void v7_secondary_startup(void);
 69void imx_scu_map_io(void);
 70void imx_smp_prepare(void);
 71#else
 72static inline void imx_scu_map_io(void) {}
 73static inline void imx_smp_prepare(void) {}
 74#endif
 75void imx_src_init(void);
 76void imx7_src_init(void);
 77void imx_gpc_pre_suspend(bool arm_power_off);
 78void imx_gpc_post_resume(void);
 79void imx_gpc_mask_all(void);
 80void imx_gpc_restore_all(void);
 81void imx_gpc_hwirq_mask(unsigned int hwirq);
 82void imx_gpc_hwirq_unmask(unsigned int hwirq);
 83void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn);
 84void imx_anatop_init(void);
 85void imx_anatop_pre_suspend(void);
 86void imx_anatop_post_resume(void);
 87int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
 88void imx6_set_int_mem_clk_lpm(bool enable);
 
 89int imx_mmdc_get_ddr_type(void);
 90int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
 91
 92void imx_cpu_die(unsigned int cpu);
 93int imx_cpu_kill(unsigned int cpu);
 94
 95#ifdef CONFIG_SUSPEND
 
 96void imx53_suspend(void __iomem *ocram_vbase);
 97extern const u32 imx53_suspend_sz;
 98void imx6_suspend(void __iomem *ocram_vbase);
 99#else
 
100static inline void imx53_suspend(void __iomem *ocram_vbase) {}
101static const u32 imx53_suspend_sz;
102static inline void imx6_suspend(void __iomem *ocram_vbase) {}
103#endif
104
105void v7_cpu_resume(void);
106
107void imx6_pm_ccm_init(const char *ccm_compat);
108void imx6q_pm_init(void);
109void imx6dl_pm_init(void);
110void imx6sl_pm_init(void);
111void imx6sx_pm_init(void);
112void imx6ul_pm_init(void);
113void imx7ulp_pm_init(void);
114
115#ifdef CONFIG_PM
116void imx51_pm_init(void);
117void imx53_pm_init(void);
118#else
119static inline void imx51_pm_init(void) {}
120static inline void imx53_pm_init(void) {}
121#endif
122
123#ifdef CONFIG_NEON
124int mx51_neon_fixup(void);
125#else
126static inline int mx51_neon_fixup(void) { return 0; }
127#endif
128
129#ifdef CONFIG_CACHE_L2X0
130void imx_init_l2cache(void);
131#else
132static inline void imx_init_l2cache(void) {}
133#endif
134
135extern const struct smp_operations imx_smp_ops;
136extern const struct smp_operations imx7_smp_ops;
137extern const struct smp_operations ls1021a_smp_ops;
138
139#endif

 
  1/*
  2 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
  3 */
  4
  5/*
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 */
 10
 11#ifndef __ASM_ARCH_MXC_COMMON_H__
 12#define __ASM_ARCH_MXC_COMMON_H__
 13
 14#include <linux/reboot.h>
 15
 16struct irq_data;
 17struct platform_device;
 18struct pt_regs;
 19struct clk;
 20struct device_node;
 21enum mxc_cpu_pwr_mode;
 22struct of_device_id;
 23
 24void mx1_map_io(void);
 25void mx21_map_io(void);
 26void mx27_map_io(void);
 27void mx31_map_io(void);
 28void mx35_map_io(void);
 29void imx1_init_early(void);
 30void imx21_init_early(void);
 31void imx27_init_early(void);
 32void imx31_init_early(void);
 33void imx35_init_early(void);
 34void mxc_init_irq(void __iomem *);
 35void tzic_init_irq(void);
 36void mx1_init_irq(void);
 37void mx21_init_irq(void);
 38void mx27_init_irq(void);
 39void mx31_init_irq(void);
 40void mx35_init_irq(void);
 41void imx1_soc_init(void);
 42void imx21_soc_init(void);
 43void imx27_soc_init(void);
 44void imx31_soc_init(void);
 45void imx35_soc_init(void);
 46void epit_timer_init(void __iomem *base, int irq);
 47int mx1_clocks_init(unsigned long fref);
 48int mx21_clocks_init(unsigned long lref, unsigned long fref);
 49int mx27_clocks_init(unsigned long fref);
 50int mx31_clocks_init(unsigned long fref);
 51int mx35_clocks_init(void);
 52int mx31_clocks_init_dt(void);
 53struct platform_device *mxc_register_gpio(char *name, int id,
 54	resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 55void mxc_set_cpu_type(unsigned int type);
 56void mxc_restart(enum reboot_mode, const char *);
 57void mxc_arch_reset_init(void __iomem *);
 
 58void imx_set_aips(void __iomem *);
 59void imx_aips_allow_unprivileged_access(const char *compat);
 60int mxc_device_init(void);
 61void imx_set_soc_revision(unsigned int rev);
 62void imx_init_revision_from_anatop(void);
 63struct device *imx_soc_device_init(void);
 64void imx6_enable_rbc(bool enable);
 65void imx_gpc_check_dt(void);
 66void imx_gpc_set_arm_power_in_lpm(bool power_off);
 
 67void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
 68void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
 69void imx25_pm_init(void);
 
 
 70
 71enum mxc_cpu_pwr_mode {
 72	WAIT_CLOCKED,		/* wfi only */
 73	WAIT_UNCLOCKED,		/* WAIT */
 74	WAIT_UNCLOCKED_POWER_OFF,	/* WAIT + SRPG */
 75	STOP_POWER_ON,		/* just STOP */
 76	STOP_POWER_OFF,		/* STOP + SRPG */
 77};
 78
 79enum mx3_cpu_pwr_mode {
 80	MX3_RUN,
 81	MX3_WAIT,
 82	MX3_DOZE,
 83	MX3_SLEEP,
 
 
 84};
 85
 86void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
 87
 88void imx_enable_cpu(int cpu, bool enable);
 89void imx_set_cpu_jump(int cpu, void *jump_addr);
 90u32 imx_get_cpu_arg(int cpu);
 91void imx_set_cpu_arg(int cpu, u32 arg);
 92#ifdef CONFIG_SMP
 93void v7_secondary_startup(void);
 94void imx_scu_map_io(void);
 95void imx_smp_prepare(void);
 96#else
 97static inline void imx_scu_map_io(void) {}
 98static inline void imx_smp_prepare(void) {}
 99#endif
100void imx_src_init(void);
 
101void imx_gpc_pre_suspend(bool arm_power_off);
102void imx_gpc_post_resume(void);
103void imx_gpc_mask_all(void);
104void imx_gpc_restore_all(void);
105void imx_gpc_hwirq_mask(unsigned int hwirq);
106void imx_gpc_hwirq_unmask(unsigned int hwirq);
 
107void imx_anatop_init(void);
108void imx_anatop_pre_suspend(void);
109void imx_anatop_post_resume(void);
110int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
111void imx6q_set_int_mem_clk_lpm(bool enable);
112void imx6sl_set_wait_clk(bool enter);
113int imx_mmdc_get_ddr_type(void);
 
114
115void imx_cpu_die(unsigned int cpu);
116int imx_cpu_kill(unsigned int cpu);
117
118#ifdef CONFIG_SUSPEND
119void v7_cpu_resume(void);
120void imx53_suspend(void __iomem *ocram_vbase);
121extern const u32 imx53_suspend_sz;
122void imx6_suspend(void __iomem *ocram_vbase);
123#else
124static inline void v7_cpu_resume(void) {}
125static inline void imx53_suspend(void __iomem *ocram_vbase) {}
126static const u32 imx53_suspend_sz;
127static inline void imx6_suspend(void __iomem *ocram_vbase) {}
128#endif
129
 
 
130void imx6_pm_ccm_init(const char *ccm_compat);
131void imx6q_pm_init(void);
132void imx6dl_pm_init(void);
133void imx6sl_pm_init(void);
134void imx6sx_pm_init(void);
135void imx6ul_pm_init(void);
 
136
137#ifdef CONFIG_PM
138void imx51_pm_init(void);
139void imx53_pm_init(void);
140#else
141static inline void imx51_pm_init(void) {}
142static inline void imx53_pm_init(void) {}
143#endif
144
145#ifdef CONFIG_NEON
146int mx51_neon_fixup(void);
147#else
148static inline int mx51_neon_fixup(void) { return 0; }
149#endif
150
151#ifdef CONFIG_CACHE_L2X0
152void imx_init_l2cache(void);
153#else
154static inline void imx_init_l2cache(void) {}
155#endif
156
157extern const struct smp_operations imx_smp_ops;
 
158extern const struct smp_operations ls1021a_smp_ops;
159
160#endif