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1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2015 Freescale Semiconductor, Inc.
4// Copyright 2016 Toradex AG
5
6#include "imx7s.dtsi"
7#include <dt-bindings/reset/imx7-reset.h>
8
9/ {
10 aliases {
11 usb0 = &usbotg1;
12 usb1 = &usbotg2;
13 usb2 = &usbh;
14 };
15
16 cpus {
17 cpu0: cpu@0 {
18 clock-frequency = <996000000>;
19 operating-points-v2 = <&cpu0_opp_table>;
20 #cooling-cells = <2>;
21 nvmem-cells = <&fuse_grade>;
22 nvmem-cell-names = "speed_grade";
23 };
24
25 cpu1: cpu@1 {
26 compatible = "arm,cortex-a7";
27 device_type = "cpu";
28 reg = <1>;
29 clock-frequency = <996000000>;
30 operating-points-v2 = <&cpu0_opp_table>;
31 #cooling-cells = <2>;
32 cpu-idle-states = <&cpu_sleep_wait>;
33 };
34 };
35
36 timer {
37 compatible = "arm,armv7-timer";
38 interrupt-parent = <&intc>;
39 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
40 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
41 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
42 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
43 };
44
45 cpu0_opp_table: opp-table {
46 compatible = "operating-points-v2";
47 opp-shared;
48
49 opp-792000000 {
50 opp-hz = /bits/ 64 <792000000>;
51 opp-microvolt = <1000000>;
52 clock-latency-ns = <150000>;
53 opp-supported-hw = <0xd>, <0x7>;
54 opp-suspend;
55 };
56
57 opp-996000000 {
58 opp-hz = /bits/ 64 <996000000>;
59 opp-microvolt = <1100000>;
60 clock-latency-ns = <150000>;
61 opp-supported-hw = <0xc>, <0x7>;
62 opp-suspend;
63 };
64
65 opp-1200000000 {
66 opp-hz = /bits/ 64 <1200000000>;
67 opp-microvolt = <1225000>;
68 clock-latency-ns = <150000>;
69 opp-supported-hw = <0x8>, <0x3>;
70 opp-suspend;
71 };
72 };
73
74 usbphynop2: usbphynop2 {
75 compatible = "usb-nop-xceiv";
76 clocks = <&clks IMX7D_USB_PHY2_CLK>;
77 clock-names = "main_clk";
78 #phy-cells = <0>;
79 };
80
81 soc: soc {
82 etm@3007d000 {
83 compatible = "arm,coresight-etm3x", "arm,primecell";
84 reg = <0x3007d000 0x1000>;
85
86 /*
87 * System will hang if added nosmp in kernel command line
88 * without arm,primecell-periphid because amba bus try to
89 * read id and core1 power off at this time.
90 */
91 arm,primecell-periphid = <0xbb956>;
92 cpu = <&cpu1>;
93 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
94 clock-names = "apb_pclk";
95
96 out-ports {
97 port {
98 etm1_out_port: endpoint {
99 remote-endpoint = <&ca_funnel_in_port1>;
100 };
101 };
102 };
103 };
104
105 intc: interrupt-controller@31001000 {
106 compatible = "arm,cortex-a7-gic";
107 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
108 #interrupt-cells = <3>;
109 interrupt-controller;
110 interrupt-parent = <&intc>;
111 reg = <0x31001000 0x1000>,
112 <0x31002000 0x2000>,
113 <0x31004000 0x2000>,
114 <0x31006000 0x2000>;
115 };
116
117 pcie: pcie@33800000 {
118 compatible = "fsl,imx7d-pcie";
119 reg = <0x33800000 0x4000>,
120 <0x4ff00000 0x80000>;
121 reg-names = "dbi", "config";
122 #address-cells = <3>;
123 #size-cells = <2>;
124 device_type = "pci";
125 bus-range = <0x00 0xff>;
126 ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */
127 <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
128 num-lanes = <1>;
129 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
130 interrupt-names = "msi";
131 #interrupt-cells = <1>;
132 interrupt-map-mask = <0 0 0 0x7>;
133 /*
134 * Reference manual lists pci irqs incorrectly
135 * Real hardware ordering is same as imx6: D+MSI, C, B, A
136 */
137 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
138 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
139 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
140 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
142 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
143 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
144 clock-names = "pcie", "pcie_bus", "pcie_phy";
145 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
146 <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
147 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
148 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
149
150 fsl,max-link-speed = <2>;
151 power-domains = <&pgc_pcie_phy>;
152 resets = <&src IMX7_RESET_PCIEPHY>,
153 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
154 <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
155 reset-names = "pciephy", "apps", "turnoff";
156 fsl,imx7d-pcie-phy = <&pcie_phy>;
157 status = "disabled";
158 };
159 };
160};
161
162&aips2 {
163 pcie_phy: pcie-phy@306d0000 {
164 compatible = "fsl,imx7d-pcie-phy";
165 reg = <0x306d0000 0x10000>;
166 status = "disabled";
167 };
168};
169
170&aips3 {
171 usbotg2: usb@30b20000 {
172 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
173 reg = <0x30b20000 0x200>;
174 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&clks IMX7D_USB_CTRL_CLK>;
176 fsl,usbphy = <&usbphynop2>;
177 fsl,usbmisc = <&usbmisc2 0>;
178 phy-clkgate-delay-us = <400>;
179 status = "disabled";
180 };
181
182 usbmisc2: usbmisc@30b20200 {
183 #index-cells = <1>;
184 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
185 reg = <0x30b20200 0x200>;
186 };
187
188 fec2: ethernet@30bf0000 {
189 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
190 reg = <0x30bf0000 0x10000>;
191 interrupt-names = "int0", "int1", "int2", "pps";
192 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
197 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
198 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
199 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
200 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
201 clock-names = "ipg", "ahb", "ptp",
202 "enet_clk_ref", "enet_out";
203 fsl,num-tx-queues = <3>;
204 fsl,num-rx-queues = <3>;
205 fsl,stop-mode = <&gpr 0x10 4>;
206 status = "disabled";
207 };
208};
209
210&ca_funnel_in_ports {
211 #address-cells = <1>;
212 #size-cells = <0>;
213
214 port@1 {
215 reg = <1>;
216 ca_funnel_in_port1: endpoint {
217 remote-endpoint = <&etm1_out_port>;
218 };
219 };
220};
1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/imx7d-clock.h>
44#include <dt-bindings/gpio/gpio.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include "imx7d-pinfunc.h"
47#include "skeleton.dtsi"
48
49/ {
50 aliases {
51 gpio0 = &gpio1;
52 gpio1 = &gpio2;
53 gpio2 = &gpio3;
54 gpio3 = &gpio4;
55 gpio4 = &gpio5;
56 gpio5 = &gpio6;
57 gpio6 = &gpio7;
58 i2c0 = &i2c1;
59 i2c1 = &i2c2;
60 i2c2 = &i2c3;
61 i2c3 = &i2c4;
62 mmc0 = &usdhc1;
63 mmc1 = &usdhc2;
64 mmc2 = &usdhc3;
65 serial0 = &uart1;
66 serial1 = &uart2;
67 serial2 = &uart3;
68 serial3 = &uart4;
69 serial4 = &uart5;
70 serial5 = &uart6;
71 serial6 = &uart7;
72 };
73
74 cpus {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 cpu0: cpu@0 {
79 compatible = "arm,cortex-a7";
80 device_type = "cpu";
81 reg = <0>;
82 operating-points = <
83 /* KHz uV */
84 996000 1075000
85 792000 975000
86 >;
87 clock-latency = <61036>; /* two CLK32 periods */
88 clocks = <&clks IMX7D_CLK_ARM>;
89 };
90
91 cpu1: cpu@1 {
92 compatible = "arm,cortex-a7";
93 device_type = "cpu";
94 reg = <1>;
95 };
96 };
97
98 intc: interrupt-controller@31001000 {
99 compatible = "arm,cortex-a7-gic";
100 #interrupt-cells = <3>;
101 interrupt-controller;
102 reg = <0x31001000 0x1000>,
103 <0x31002000 0x1000>,
104 <0x31004000 0x2000>,
105 <0x31006000 0x2000>;
106 };
107
108 ckil: clock-cki {
109 compatible = "fixed-clock";
110 #clock-cells = <0>;
111 clock-frequency = <32768>;
112 clock-output-names = "ckil";
113 };
114
115 osc: clock-osc {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 clock-frequency = <24000000>;
119 clock-output-names = "osc";
120 };
121
122 timer {
123 compatible = "arm,armv7-timer";
124 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
125 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
126 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
127 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
128 interrupt-parent = <&intc>;
129 };
130
131 etr@30086000 {
132 compatible = "arm,coresight-tmc", "arm,primecell";
133 reg = <0x30086000 0x1000>;
134 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
135 clock-names = "apb_pclk";
136
137 port {
138 etr_in_port: endpoint {
139 slave-mode;
140 remote-endpoint = <&replicator_out_port1>;
141 };
142 };
143 };
144
145 tpiu@30087000 {
146 compatible = "arm,coresight-tpiu", "arm,primecell";
147 reg = <0x30087000 0x1000>;
148 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
149 clock-names = "apb_pclk";
150
151 port {
152 tpiu_in_port: endpoint {
153 slave-mode;
154 remote-endpoint = <&replicator_out_port1>;
155 };
156 };
157 };
158
159 replicator {
160 /*
161 * non-configurable replicators don't show up on the
162 * AMBA bus. As such no need to add "arm,primecell"
163 */
164 compatible = "arm,coresight-replicator";
165
166 ports {
167 #address-cells = <1>;
168 #size-cells = <0>;
169
170 /* replicator output ports */
171 port@0 {
172 reg = <0>;
173 replicator_out_port0: endpoint {
174 remote-endpoint = <&tpiu_in_port>;
175 };
176 };
177
178 port@1 {
179 reg = <1>;
180 replicator_out_port1: endpoint {
181 remote-endpoint = <&etr_in_port>;
182 };
183 };
184
185 /* replicator input port */
186 port@2 {
187 reg = <0>;
188 replicator_in_port0: endpoint {
189 slave-mode;
190 remote-endpoint = <&etf_out_port>;
191 };
192 };
193 };
194 };
195
196 etf@30084000 {
197 compatible = "arm,coresight-tmc", "arm,primecell";
198 reg = <0x30084000 0x1000>;
199 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
200 clock-names = "apb_pclk";
201
202 ports {
203 #address-cells = <1>;
204 #size-cells = <0>;
205
206 port@0 {
207 reg = <0>;
208 etf_in_port: endpoint {
209 slave-mode;
210 remote-endpoint = <&hugo_funnel_out_port0>;
211 };
212 };
213
214 port@1 {
215 reg = <0>;
216 etf_out_port: endpoint {
217 remote-endpoint = <&replicator_in_port0>;
218 };
219 };
220 };
221 };
222
223 funnel@30083000 {
224 compatible = "arm,coresight-funnel", "arm,primecell";
225 reg = <0x30083000 0x1000>;
226 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
227 clock-names = "apb_pclk";
228
229 ports {
230 #address-cells = <1>;
231 #size-cells = <0>;
232
233 /* funnel input ports */
234 port@0 {
235 reg = <0>;
236 hugo_funnel_in_port0: endpoint {
237 slave-mode;
238 remote-endpoint = <&ca_funnel_out_port0>;
239 };
240 };
241
242 port@1 {
243 reg = <1>;
244 hugo_funnel_in_port1: endpoint {
245 slave-mode; /* M4 input */
246 };
247 };
248
249 port@2 {
250 reg = <0>;
251 hugo_funnel_out_port0: endpoint {
252 remote-endpoint = <&etf_in_port>;
253 };
254 };
255
256 /* the other input ports are not connect to anything */
257 };
258 };
259
260 funnel@30041000 {
261 compatible = "arm,coresight-funnel", "arm,primecell";
262 reg = <0x30041000 0x1000>;
263 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
264 clock-names = "apb_pclk";
265
266 ports {
267 #address-cells = <1>;
268 #size-cells = <0>;
269
270 /* funnel input ports */
271 port@0 {
272 reg = <0>;
273 ca_funnel_in_port0: endpoint {
274 slave-mode;
275 remote-endpoint = <&etm0_out_port>;
276 };
277 };
278
279 port@1 {
280 reg = <1>;
281 ca_funnel_in_port1: endpoint {
282 slave-mode;
283 remote-endpoint = <&etm1_out_port>;
284 };
285 };
286
287 /* funnel output port */
288 port@2 {
289 reg = <0>;
290 ca_funnel_out_port0: endpoint {
291 remote-endpoint = <&hugo_funnel_in_port0>;
292 };
293 };
294
295 /* the other input ports are not connect to anything */
296 };
297 };
298
299 etm@3007c000 {
300 compatible = "arm,coresight-etm3x", "arm,primecell";
301 reg = <0x3007c000 0x1000>;
302 cpu = <&cpu0>;
303 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
304 clock-names = "apb_pclk";
305
306 port {
307 etm0_out_port: endpoint {
308 remote-endpoint = <&ca_funnel_in_port0>;
309 };
310 };
311 };
312
313 etm@3007d000 {
314 compatible = "arm,coresight-etm3x", "arm,primecell";
315 reg = <0x3007d000 0x1000>;
316
317 /*
318 * System will hang if added nosmp in kernel command line
319 * without arm,primecell-periphid because amba bus try to
320 * read id and core1 power off at this time.
321 */
322 arm,primecell-periphid = <0xbb956>;
323 cpu = <&cpu1>;
324 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
325 clock-names = "apb_pclk";
326
327 port {
328 etm1_out_port: endpoint {
329 remote-endpoint = <&ca_funnel_in_port1>;
330 };
331 };
332 };
333
334 soc {
335 #address-cells = <1>;
336 #size-cells = <1>;
337 compatible = "simple-bus";
338 interrupt-parent = <&intc>;
339 ranges;
340
341 aips1: aips-bus@30000000 {
342 compatible = "fsl,aips-bus", "simple-bus";
343 #address-cells = <1>;
344 #size-cells = <1>;
345 reg = <0x30000000 0x400000>;
346 ranges;
347
348 gpio1: gpio@30200000 {
349 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
350 reg = <0x30200000 0x10000>;
351 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
352 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
353 gpio-controller;
354 #gpio-cells = <2>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 };
358
359 gpio2: gpio@30210000 {
360 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
361 reg = <0x30210000 0x10000>;
362 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 };
369
370 gpio3: gpio@30220000 {
371 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
372 reg = <0x30220000 0x10000>;
373 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
375 gpio-controller;
376 #gpio-cells = <2>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 };
380
381 gpio4: gpio@30230000 {
382 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
383 reg = <0x30230000 0x10000>;
384 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
386 gpio-controller;
387 #gpio-cells = <2>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
390 };
391
392 gpio5: gpio@30240000 {
393 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
394 reg = <0x30240000 0x10000>;
395 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
397 gpio-controller;
398 #gpio-cells = <2>;
399 interrupt-controller;
400 #interrupt-cells = <2>;
401 };
402
403 gpio6: gpio@30250000 {
404 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
405 reg = <0x30250000 0x10000>;
406 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
408 gpio-controller;
409 #gpio-cells = <2>;
410 interrupt-controller;
411 #interrupt-cells = <2>;
412 };
413
414 gpio7: gpio@30260000 {
415 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
416 reg = <0x30260000 0x10000>;
417 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
419 gpio-controller;
420 #gpio-cells = <2>;
421 interrupt-controller;
422 #interrupt-cells = <2>;
423 };
424
425 wdog1: wdog@30280000 {
426 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
427 reg = <0x30280000 0x10000>;
428 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
430 };
431
432 wdog2: wdog@30290000 {
433 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
434 reg = <0x30290000 0x10000>;
435 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
437 status = "disabled";
438 };
439
440 wdog3: wdog@302a0000 {
441 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
442 reg = <0x302a0000 0x10000>;
443 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
445 status = "disabled";
446 };
447
448 wdog4: wdog@302b0000 {
449 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
450 reg = <0x302b0000 0x10000>;
451 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
453 status = "disabled";
454 };
455
456 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
457 compatible = "fsl,imx7d-iomuxc-lpsr";
458 reg = <0x302c0000 0x10000>;
459 fsl,input-sel = <&iomuxc>;
460 };
461
462 gpt1: gpt@302d0000 {
463 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
464 reg = <0x302d0000 0x10000>;
465 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clks IMX7D_CLK_DUMMY>,
467 <&clks IMX7D_GPT1_ROOT_CLK>;
468 clock-names = "ipg", "per";
469 };
470
471 gpt2: gpt@302e0000 {
472 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
473 reg = <0x302e0000 0x10000>;
474 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clks IMX7D_CLK_DUMMY>,
476 <&clks IMX7D_GPT2_ROOT_CLK>;
477 clock-names = "ipg", "per";
478 status = "disabled";
479 };
480
481 gpt3: gpt@302f0000 {
482 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
483 reg = <0x302f0000 0x10000>;
484 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clks IMX7D_CLK_DUMMY>,
486 <&clks IMX7D_GPT3_ROOT_CLK>;
487 clock-names = "ipg", "per";
488 status = "disabled";
489 };
490
491 gpt4: gpt@30300000 {
492 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
493 reg = <0x30300000 0x10000>;
494 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&clks IMX7D_CLK_DUMMY>,
496 <&clks IMX7D_GPT4_ROOT_CLK>;
497 clock-names = "ipg", "per";
498 status = "disabled";
499 };
500
501 iomuxc: iomuxc@30330000 {
502 compatible = "fsl,imx7d-iomuxc";
503 reg = <0x30330000 0x10000>;
504 };
505
506 gpr: iomuxc-gpr@30340000 {
507 compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
508 reg = <0x30340000 0x10000>;
509 };
510
511 ocotp: ocotp-ctrl@30350000 {
512 compatible = "syscon";
513 reg = <0x30350000 0x10000>;
514 clocks = <&clks IMX7D_CLK_DUMMY>;
515 status = "disabled";
516 };
517
518 anatop: anatop@30360000 {
519 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
520 "syscon", "simple-bus";
521 reg = <0x30360000 0x10000>;
522 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
524
525 reg_1p0d: regulator-vdd1p0d@210 {
526 compatible = "fsl,anatop-regulator";
527 regulator-name = "vdd1p0d";
528 regulator-min-microvolt = <800000>;
529 regulator-max-microvolt = <1200000>;
530 anatop-reg-offset = <0x210>;
531 anatop-vol-bit-shift = <8>;
532 anatop-vol-bit-width = <5>;
533 anatop-min-bit-val = <8>;
534 anatop-min-voltage = <800000>;
535 anatop-max-voltage = <1200000>;
536 anatop-enable-bit = <31>;
537 };
538 };
539
540 snvs: snvs@30370000 {
541 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
542 reg = <0x30370000 0x10000>;
543
544 snvs_rtc: snvs-rtc-lp {
545 compatible = "fsl,sec-v4.0-mon-rtc-lp";
546 regmap = <&snvs>;
547 offset = <0x34>;
548 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
550 };
551
552 snvs_poweroff: snvs-poweroff {
553 compatible = "syscon-poweroff";
554 regmap = <&snvs>;
555 offset = <0x38>;
556 mask = <0x60>;
557 };
558
559 snvs_pwrkey: snvs-powerkey {
560 compatible = "fsl,sec-v4.0-pwrkey";
561 regmap = <&snvs>;
562 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
563 linux,keycode = <KEY_POWER>;
564 wakeup-source;
565 };
566 };
567
568 clks: ccm@30380000 {
569 compatible = "fsl,imx7d-ccm";
570 reg = <0x30380000 0x10000>;
571 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
573 #clock-cells = <1>;
574 clocks = <&ckil>, <&osc>;
575 clock-names = "ckil", "osc";
576 };
577
578 src: src@30390000 {
579 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
580 reg = <0x30390000 0x10000>;
581 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
582 #reset-cells = <1>;
583 };
584 };
585
586 aips2: aips-bus@30400000 {
587 compatible = "fsl,aips-bus", "simple-bus";
588 #address-cells = <1>;
589 #size-cells = <1>;
590 reg = <0x30400000 0x400000>;
591 ranges;
592
593 adc1: adc@30610000 {
594 compatible = "fsl,imx7d-adc";
595 reg = <0x30610000 0x10000>;
596 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
598 clock-names = "adc";
599 status = "disabled";
600 };
601
602 adc2: adc@30620000 {
603 compatible = "fsl,imx7d-adc";
604 reg = <0x30620000 0x10000>;
605 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
607 clock-names = "adc";
608 status = "disabled";
609 };
610
611 pwm1: pwm@30660000 {
612 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
613 reg = <0x30660000 0x10000>;
614 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
616 <&clks IMX7D_PWM1_ROOT_CLK>;
617 clock-names = "ipg", "per";
618 #pwm-cells = <2>;
619 status = "disabled";
620 };
621
622 pwm2: pwm@30670000 {
623 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
624 reg = <0x30670000 0x10000>;
625 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
627 <&clks IMX7D_PWM2_ROOT_CLK>;
628 clock-names = "ipg", "per";
629 #pwm-cells = <2>;
630 status = "disabled";
631 };
632
633 pwm3: pwm@30680000 {
634 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
635 reg = <0x30680000 0x10000>;
636 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
638 <&clks IMX7D_PWM3_ROOT_CLK>;
639 clock-names = "ipg", "per";
640 #pwm-cells = <2>;
641 status = "disabled";
642 };
643
644 pwm4: pwm@30690000 {
645 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
646 reg = <0x30690000 0x10000>;
647 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
649 <&clks IMX7D_PWM4_ROOT_CLK>;
650 clock-names = "ipg", "per";
651 #pwm-cells = <2>;
652 status = "disabled";
653 };
654 };
655
656 aips3: aips-bus@30800000 {
657 compatible = "fsl,aips-bus", "simple-bus";
658 #address-cells = <1>;
659 #size-cells = <1>;
660 reg = <0x30800000 0x400000>;
661 ranges;
662
663 uart1: serial@30860000 {
664 compatible = "fsl,imx7d-uart",
665 "fsl,imx6q-uart";
666 reg = <0x30860000 0x10000>;
667 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
669 <&clks IMX7D_UART1_ROOT_CLK>;
670 clock-names = "ipg", "per";
671 status = "disabled";
672 };
673
674 uart2: serial@30890000 {
675 compatible = "fsl,imx7d-uart",
676 "fsl,imx6q-uart";
677 reg = <0x30890000 0x10000>;
678 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
680 <&clks IMX7D_UART2_ROOT_CLK>;
681 clock-names = "ipg", "per";
682 status = "disabled";
683 };
684
685 uart3: serial@30880000 {
686 compatible = "fsl,imx7d-uart",
687 "fsl,imx6q-uart";
688 reg = <0x30880000 0x10000>;
689 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
691 <&clks IMX7D_UART3_ROOT_CLK>;
692 clock-names = "ipg", "per";
693 status = "disabled";
694 };
695
696 i2c1: i2c@30a20000 {
697 #address-cells = <1>;
698 #size-cells = <0>;
699 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
700 reg = <0x30a20000 0x10000>;
701 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
703 status = "disabled";
704 };
705
706 i2c2: i2c@30a30000 {
707 #address-cells = <1>;
708 #size-cells = <0>;
709 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
710 reg = <0x30a30000 0x10000>;
711 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
713 status = "disabled";
714 };
715
716 i2c3: i2c@30a40000 {
717 #address-cells = <1>;
718 #size-cells = <0>;
719 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
720 reg = <0x30a40000 0x10000>;
721 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
723 status = "disabled";
724 };
725
726 i2c4: i2c@30a50000 {
727 #address-cells = <1>;
728 #size-cells = <0>;
729 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
730 reg = <0x30a50000 0x10000>;
731 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
733 status = "disabled";
734 };
735
736 uart4: serial@30a60000 {
737 compatible = "fsl,imx7d-uart",
738 "fsl,imx6q-uart";
739 reg = <0x30a60000 0x10000>;
740 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
742 <&clks IMX7D_UART4_ROOT_CLK>;
743 clock-names = "ipg", "per";
744 status = "disabled";
745 };
746
747 uart5: serial@30a70000 {
748 compatible = "fsl,imx7d-uart",
749 "fsl,imx6q-uart";
750 reg = <0x30a70000 0x10000>;
751 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
753 <&clks IMX7D_UART5_ROOT_CLK>;
754 clock-names = "ipg", "per";
755 status = "disabled";
756 };
757
758 uart6: serial@30a80000 {
759 compatible = "fsl,imx7d-uart",
760 "fsl,imx6q-uart";
761 reg = <0x30a80000 0x10000>;
762 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
764 <&clks IMX7D_UART6_ROOT_CLK>;
765 clock-names = "ipg", "per";
766 status = "disabled";
767 };
768
769 uart7: serial@30a90000 {
770 compatible = "fsl,imx7d-uart",
771 "fsl,imx6q-uart";
772 reg = <0x30a90000 0x10000>;
773 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
775 <&clks IMX7D_UART7_ROOT_CLK>;
776 clock-names = "ipg", "per";
777 status = "disabled";
778 };
779
780 usbotg1: usb@30b10000 {
781 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
782 reg = <0x30b10000 0x200>;
783 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&clks IMX7D_USB_CTRL_CLK>;
785 fsl,usbphy = <&usbphynop1>;
786 fsl,usbmisc = <&usbmisc1 0>;
787 phy-clkgate-delay-us = <400>;
788 status = "disabled";
789 };
790
791 usbotg2: usb@30b20000 {
792 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
793 reg = <0x30b20000 0x200>;
794 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clks IMX7D_USB_CTRL_CLK>;
796 fsl,usbphy = <&usbphynop2>;
797 fsl,usbmisc = <&usbmisc2 0>;
798 phy-clkgate-delay-us = <400>;
799 status = "disabled";
800 };
801
802 usbh: usb@30b30000 {
803 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
804 reg = <0x30b30000 0x200>;
805 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&clks IMX7D_USB_CTRL_CLK>;
807 fsl,usbphy = <&usbphynop3>;
808 fsl,usbmisc = <&usbmisc3 0>;
809 phy_type = "hsic";
810 dr_mode = "host";
811 phy-clkgate-delay-us = <400>;
812 status = "disabled";
813 };
814
815 usbmisc1: usbmisc@30b10200 {
816 #index-cells = <1>;
817 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
818 reg = <0x30b10200 0x200>;
819 };
820
821 usbmisc2: usbmisc@30b20200 {
822 #index-cells = <1>;
823 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
824 reg = <0x30b20200 0x200>;
825 };
826
827 usbmisc3: usbmisc@30b30200 {
828 #index-cells = <1>;
829 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
830 reg = <0x30b30200 0x200>;
831 };
832
833 usbphynop1: usbphynop1 {
834 compatible = "usb-nop-xceiv";
835 clocks = <&clks IMX7D_USB_PHY1_CLK>;
836 clock-names = "main_clk";
837 };
838
839 usbphynop2: usbphynop2 {
840 compatible = "usb-nop-xceiv";
841 clocks = <&clks IMX7D_USB_PHY2_CLK>;
842 clock-names = "main_clk";
843 };
844
845 usbphynop3: usbphynop3 {
846 compatible = "usb-nop-xceiv";
847 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
848 clock-names = "main_clk";
849 };
850
851 usdhc1: usdhc@30b40000 {
852 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
853 reg = <0x30b40000 0x10000>;
854 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&clks IMX7D_CLK_DUMMY>,
856 <&clks IMX7D_CLK_DUMMY>,
857 <&clks IMX7D_USDHC1_ROOT_CLK>;
858 clock-names = "ipg", "ahb", "per";
859 bus-width = <4>;
860 status = "disabled";
861 };
862
863 usdhc2: usdhc@30b50000 {
864 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
865 reg = <0x30b50000 0x10000>;
866 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&clks IMX7D_CLK_DUMMY>,
868 <&clks IMX7D_CLK_DUMMY>,
869 <&clks IMX7D_USDHC2_ROOT_CLK>;
870 clock-names = "ipg", "ahb", "per";
871 bus-width = <4>;
872 status = "disabled";
873 };
874
875 usdhc3: usdhc@30b60000 {
876 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
877 reg = <0x30b60000 0x10000>;
878 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clks IMX7D_CLK_DUMMY>,
880 <&clks IMX7D_CLK_DUMMY>,
881 <&clks IMX7D_USDHC3_ROOT_CLK>;
882 clock-names = "ipg", "ahb", "per";
883 bus-width = <4>;
884 status = "disabled";
885 };
886
887 fec1: ethernet@30be0000 {
888 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
889 reg = <0x30be0000 0x10000>;
890 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
894 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
895 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
896 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
897 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
898 clock-names = "ipg", "ahb", "ptp",
899 "enet_clk_ref", "enet_out";
900 fsl,num-tx-queues=<3>;
901 fsl,num-rx-queues=<3>;
902 status = "disabled";
903 };
904
905 fec2: ethernet@30bf0000 {
906 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
907 reg = <0x30bf0000 0x10000>;
908 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
912 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
913 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
914 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
915 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
916 clock-names = "ipg", "ahb", "ptp",
917 "enet_clk_ref", "enet_out";
918 fsl,num-tx-queues=<3>;
919 fsl,num-rx-queues=<3>;
920 status = "disabled";
921 };
922 };
923 };
924};