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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/* AM437x GP EVM */
7
8/dts-v1/;
9
10#include "am4372.dtsi"
11#include <dt-bindings/pinctrl/am43xx.h>
12#include <dt-bindings/pwm/pwm.h>
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "TI AM437x GP EVM";
17 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
18
19 aliases {
20 display0 = &lcd0;
21 };
22
23 chosen {
24 stdout-path = &uart0;
25 };
26
27 evm_v3_3d: fixedregulator-v3_3d {
28 compatible = "regulator-fixed";
29 regulator-name = "evm_v3_3d";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 enable-active-high;
33 };
34
35 vtt_fixed: fixedregulator-vtt {
36 compatible = "regulator-fixed";
37 regulator-name = "vtt_fixed";
38 regulator-min-microvolt = <1500000>;
39 regulator-max-microvolt = <1500000>;
40 regulator-always-on;
41 regulator-boot-on;
42 enable-active-high;
43 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
44 };
45
46 vmmcwl_fixed: fixedregulator-mmcwl {
47 compatible = "regulator-fixed";
48 regulator-name = "vmmcwl_fixed";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <1800000>;
51 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 };
54
55 lcd_bl: backlight {
56 compatible = "pwm-backlight";
57 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
58 brightness-levels = <0 51 53 56 62 75 101 152 255>;
59 default-brightness-level = <8>;
60 };
61
62 matrix_keypad: matrix_keypad0 {
63 compatible = "gpio-matrix-keypad";
64 debounce-delay-ms = <5>;
65 col-scan-delay-us = <2>;
66
67 pinctrl-names = "default", "sleep";
68 pinctrl-0 = <&matrix_keypad_default>;
69 pinctrl-1 = <&matrix_keypad_sleep>;
70
71 wakeup-source;
72
73 row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */
74 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
75 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
76
77 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
78 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
79
80 linux,keymap = <0x00000201 /* P1 */
81 0x00010202 /* P2 */
82 0x01000067 /* UP */
83 0x0101006a /* RIGHT */
84 0x02000069 /* LEFT */
85 0x0201006c>; /* DOWN */
86 };
87
88 lcd0: display {
89 compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";
90 label = "lcd";
91
92 backlight = <&lcd_bl>;
93
94 port {
95 lcd_in: endpoint {
96 remote-endpoint = <&dpi_out>;
97 };
98 };
99 };
100
101 /* fixed 12MHz oscillator */
102 refclk: oscillator {
103 #clock-cells = <0>;
104 compatible = "fixed-clock";
105 clock-frequency = <12000000>;
106 };
107
108 /* fixed 32k external oscillator clock */
109 clk_32k_rtc: clk_32k_rtc {
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
112 clock-frequency = <32768>;
113 };
114
115 sound0: sound0 {
116 compatible = "simple-audio-card";
117 simple-audio-card,name = "AM437x-GP-EVM";
118 simple-audio-card,widgets =
119 "Headphone", "Headphone Jack",
120 "Line", "Line In";
121 simple-audio-card,routing =
122 "Headphone Jack", "HPLOUT",
123 "Headphone Jack", "HPROUT",
124 "LINE1L", "Line In",
125 "LINE1R", "Line In";
126 simple-audio-card,format = "dsp_b";
127 simple-audio-card,bitclock-master = <&sound0_master>;
128 simple-audio-card,frame-master = <&sound0_master>;
129 simple-audio-card,bitclock-inversion;
130
131 simple-audio-card,cpu {
132 sound-dai = <&mcasp1>;
133 system-clock-frequency = <12000000>;
134 };
135
136 sound0_master: simple-audio-card,codec {
137 sound-dai = <&tlv320aic3106>;
138 system-clock-frequency = <12000000>;
139 };
140 };
141
142 beeper: beeper {
143 compatible = "gpio-beeper";
144 pinctrl-names = "default";
145 pinctrl-0 = <&beeper_pins_default>;
146 pinctrl-1 = <&beeper_pins_sleep>;
147 gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
148 };
149};
150
151&am43xx_pinmux {
152 pinctrl-names = "default", "sleep";
153 pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>;
154 pinctrl-1 = <&wlan_pins_sleep>;
155
156 ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
157 pinctrl-single,pins = <
158 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */
159 >;
160 };
161
162 i2c0_pins: i2c0_pins {
163 pinctrl-single,pins = <
164 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
165 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
166 >;
167 };
168
169 i2c1_pins: i2c1_pins {
170 pinctrl-single,pins = <
171 AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
172 AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
173 >;
174 };
175
176 mmc1_pins: pinmux_mmc1_pins {
177 pinctrl-single,pins = <
178 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
179 >;
180 };
181
182 ecap0_pins: backlight_pins {
183 pinctrl-single,pins = <
184 AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
185 >;
186 };
187
188 pixcir_ts_pins: pixcir_ts_pins {
189 pinctrl-single,pins = <
190 AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
191 >;
192 };
193
194 cpsw_default: cpsw_default {
195 pinctrl-single,pins = <
196 /* Slave 1 */
197 AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
198 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
199 AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
200 AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
201 AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
202 AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
203 AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
204 AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
205 AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
206 AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
207 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
208 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
209 >;
210 };
211
212 cpsw_sleep: cpsw_sleep {
213 pinctrl-single,pins = <
214 /* Slave 1 reset value */
215 AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
216 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
217 AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
218 AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
219 AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
220 AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
221 AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
222 AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
223 AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
224 AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
225 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
226 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
227 >;
228 };
229
230 davinci_mdio_default: davinci_mdio_default {
231 pinctrl-single,pins = <
232 /* MDIO */
233 AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
234 AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
235 >;
236 };
237
238 davinci_mdio_sleep: davinci_mdio_sleep {
239 pinctrl-single,pins = <
240 /* MDIO reset value */
241 AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
242 AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
243 >;
244 };
245
246 nand_flash_x8: nand_flash_x8 {
247 pinctrl-single,pins = <
248 AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
249 AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
250 AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
251 AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
252 AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
253 AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
254 AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
255 AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
256 AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
257 AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
258 AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
259 AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
260 AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
261 AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
262 AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
263 >;
264 };
265
266 dss_pins: dss_pins {
267 pinctrl-single,pins = <
268 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
269 AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
270 AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
271 AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
272 AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
273 AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
274 AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
275 AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
276 AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
277 AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
278 AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
279 AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
280 AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
281 AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
282 AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
283 AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
284 AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
285 AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
286 AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
287 AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
288 AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
289 AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
290 AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
291 AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
292 AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
293 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
294 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
295 AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
296
297 >;
298 };
299
300 display_mux_pins: display_mux_pins {
301 pinctrl-single,pins = <
302 /* GPIO 5_8 to select LCD / HDMI */
303 AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
304 >;
305 };
306
307 dcan0_default: dcan0_default_pins {
308 pinctrl-single,pins = <
309 AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
310 AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
311 >;
312 };
313
314 dcan0_sleep: dcan0_sleep_pins {
315 pinctrl-single,pins = <
316 AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */
317 AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */
318 >;
319 };
320
321 dcan1_default: dcan1_default_pins {
322 pinctrl-single,pins = <
323 AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
324 AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
325 >;
326 };
327
328 dcan1_sleep: dcan1_sleep_pins {
329 pinctrl-single,pins = <
330 AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */
331 AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */
332 >;
333 };
334
335 vpfe0_pins_default: vpfe0_pins_default {
336 pinctrl-single,pins = <
337 AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
338 AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
339 AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
340 AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
341 AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
342 AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
343 AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
344 AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
345 AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
346 AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
347 AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
348 AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
349 AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
350 >;
351 };
352
353 vpfe0_pins_sleep: vpfe0_pins_sleep {
354 pinctrl-single,pins = <
355 AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
356 AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
357 AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
358 AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
359 AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
360 AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
361 AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
362 AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
363 AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
364 AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
365 AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
366 AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
367 AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
368 >;
369 };
370
371 vpfe1_pins_default: vpfe1_pins_default {
372 pinctrl-single,pins = <
373 AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
374 AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
375 AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
376 AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
377 AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
378 AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
379 AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
380 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
381 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
382 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
383 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
384 AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
385 AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
386 >;
387 };
388
389 vpfe1_pins_sleep: vpfe1_pins_sleep {
390 pinctrl-single,pins = <
391 AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
392 AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
393 AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
394 AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
395 AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
396 AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
397 AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
398 AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
399 AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
400 AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
401 AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
402 AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
403 AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
404 >;
405 };
406
407 mmc3_pins_default: pinmux_mmc3_pins_default {
408 pinctrl-single,pins = <
409 AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
410 AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
411 AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
412 AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
413 AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
414 AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
415 >;
416 };
417
418 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
419 pinctrl-single,pins = <
420 AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
421 AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
422 AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
423 AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
424 AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
425 AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
426 >;
427 };
428
429 wlan_pins_default: pinmux_wlan_pins_default {
430 pinctrl-single,pins = <
431 AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
432 AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
433 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
434 >;
435 };
436
437 wlan_pins_sleep: pinmux_wlan_pins_sleep {
438 pinctrl-single,pins = <
439 AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
440 AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
441 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
442 >;
443 };
444
445 uart3_pins: uart3_pins {
446 pinctrl-single,pins = <
447 AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
448 AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
449 AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
450 AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
451 >;
452 };
453
454 mcasp1_pins: mcasp1_pins {
455 pinctrl-single,pins = <
456 AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
457 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
458 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
459 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
460 >;
461 };
462
463 mcasp1_sleep_pins: mcasp1_sleep_pins {
464 pinctrl-single,pins = <
465 AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
466 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
467 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
468 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
469 >;
470 };
471
472 gpio0_pins: gpio0_pins {
473 pinctrl-single,pins = <
474 AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
475 >;
476 };
477
478 emmc_pins_default: emmc_pins_default {
479 pinctrl-single,pins = <
480 AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
481 AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
482 AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
483 AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
484 AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
485 AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
486 AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
487 AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
488 AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
489 AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
490 >;
491 };
492
493 emmc_pins_sleep: emmc_pins_sleep {
494 pinctrl-single,pins = <
495 AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
496 AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
497 AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
498 AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
499 AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
500 AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
501 AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
502 AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
503 AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
504 AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
505 >;
506 };
507
508 beeper_pins_default: beeper_pins_default {
509 pinctrl-single,pins = <
510 AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */
511 >;
512 };
513
514 beeper_pins_sleep: beeper_pins_sleep {
515 pinctrl-single,pins = <
516 AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */
517 >;
518 };
519
520 unused_pins: unused_pins {
521 pinctrl-single,pins = <
522 AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
523 AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
524 AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
525 AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
526 AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
527 AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
528 AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7)
529 AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7)
530 AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7)
531 AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7)
532 AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7)
533 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
534 AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
535 AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7)
536 AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7)
537 AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7)
538 AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7)
539 AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7)
540 AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
541 AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7)
542 AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
543 AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7)
544 AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7)
545 AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7)
546 AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE)
547 AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN)
548 AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN)
549 AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7)
550 AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7)
551 AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7)
552 AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7)
553 AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7)
554 AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7)
555 AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7)
556 AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7)
557 AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7)
558 AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7)
559 AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7)
560 AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7)
561 AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7)
562 AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7)
563 AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7)
564 AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7)
565 AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7)
566 >;
567 };
568
569 debugss_pins: pinmux_debugss_pins {
570 pinctrl-single,pins = <
571 AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN)
572 AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN)
573 AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN)
574 AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN)
575 AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN)
576 AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN)
577 AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN)
578 >;
579 };
580
581 uart0_pins_default: uart0_pins_default {
582 pinctrl-single,pins = <
583 AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
584 AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
585 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
586 AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
587 >;
588 };
589
590 uart0_pins_sleep: uart0_pins_sleep {
591 pinctrl-single,pins = <
592 AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */
593 AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */
594 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
595 AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
596 >;
597 };
598
599 matrix_keypad_default: matrix_keypad_default {
600 pinctrl-single,pins = <
601 AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7)
602 AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7)
603 AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
604 AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
605 >;
606 };
607
608 matrix_keypad_sleep: matrix_keypad_sleep {
609 pinctrl-single,pins = <
610 AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7)
611 AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7)
612 AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
613 AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
614 >;
615 };
616};
617
618&uart0 {
619 status = "okay";
620 pinctrl-names = "default", "sleep";
621 pinctrl-0 = <&uart0_pins_default>;
622 pinctrl-1 = <&uart0_pins_sleep>;
623};
624
625&i2c0 {
626 status = "okay";
627 pinctrl-names = "default";
628 pinctrl-0 = <&i2c0_pins>;
629 clock-frequency = <100000>;
630
631 tps65218: tps65218@24 {
632 reg = <0x24>;
633 compatible = "ti,tps65218";
634 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */
635 interrupt-controller;
636 #interrupt-cells = <2>;
637
638 dcdc1: regulator-dcdc1 {
639 regulator-name = "vdd_core";
640 regulator-min-microvolt = <912000>;
641 regulator-max-microvolt = <1144000>;
642 regulator-boot-on;
643 regulator-always-on;
644 };
645
646 dcdc2: regulator-dcdc2 {
647 regulator-name = "vdd_mpu";
648 regulator-min-microvolt = <912000>;
649 regulator-max-microvolt = <1378000>;
650 regulator-boot-on;
651 regulator-always-on;
652 };
653
654 dcdc3: regulator-dcdc3 {
655 regulator-name = "vdcdc3";
656 regulator-boot-on;
657 regulator-always-on;
658 regulator-state-mem {
659 regulator-on-in-suspend;
660 };
661 regulator-state-disk {
662 regulator-off-in-suspend;
663 };
664 };
665
666 dcdc5: regulator-dcdc5 {
667 regulator-name = "v1_0bat";
668 regulator-min-microvolt = <1000000>;
669 regulator-max-microvolt = <1000000>;
670 regulator-boot-on;
671 regulator-always-on;
672 regulator-state-mem {
673 regulator-on-in-suspend;
674 };
675 };
676
677 dcdc6: regulator-dcdc6 {
678 regulator-name = "v1_8bat";
679 regulator-min-microvolt = <1800000>;
680 regulator-max-microvolt = <1800000>;
681 regulator-boot-on;
682 regulator-always-on;
683 regulator-state-mem {
684 regulator-on-in-suspend;
685 };
686 };
687
688 ldo1: regulator-ldo1 {
689 regulator-min-microvolt = <1800000>;
690 regulator-max-microvolt = <1800000>;
691 regulator-boot-on;
692 regulator-always-on;
693 };
694 };
695
696 ov2659@30 {
697 compatible = "ovti,ov2659";
698 reg = <0x30>;
699
700 clocks = <&refclk 0>;
701 clock-names = "xvclk";
702
703 port {
704 ov2659_0: endpoint {
705 remote-endpoint = <&vpfe1_ep>;
706 link-frequencies = /bits/ 64 <70000000>;
707 };
708 };
709 };
710};
711
712&i2c1 {
713 status = "okay";
714 pinctrl-names = "default";
715 pinctrl-0 = <&i2c1_pins>;
716 pixcir_ts@5c {
717 compatible = "pixcir,pixcir_tangoc";
718 pinctrl-names = "default";
719 pinctrl-0 = <&pixcir_ts_pins>;
720 reg = <0x5c>;
721
722 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
723
724 /*
725 * 0x264 represents the offset of padconf register of
726 * gpio3_22 from am43xx_pinmux base.
727 */
728 interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
729 <&am43xx_pinmux 0x264>;
730 interrupt-names = "tsc", "wakeup";
731
732 touchscreen-size-x = <1024>;
733 touchscreen-size-y = <600>;
734 wakeup-source;
735 };
736
737 ov2659@30 {
738 compatible = "ovti,ov2659";
739 reg = <0x30>;
740
741 clocks = <&refclk 0>;
742 clock-names = "xvclk";
743
744 port {
745 ov2659_1: endpoint {
746 remote-endpoint = <&vpfe0_ep>;
747 link-frequencies = /bits/ 64 <70000000>;
748 };
749 };
750 };
751
752 tlv320aic3106: tlv320aic3106@1b {
753 #sound-dai-cells = <0>;
754 compatible = "ti,tlv320aic3106";
755 reg = <0x1b>;
756 status = "okay";
757
758 /* Regulators */
759 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
760 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
761 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
762 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
763 };
764};
765
766&epwmss0 {
767 status = "okay";
768};
769
770&tscadc {
771 status = "okay";
772
773 adc {
774 ti,adc-channels = <0 1 2 3 4 5 6 7>;
775 };
776};
777
778&magadc {
779 status = "okay";
780
781 adc {
782 ti,adc-channels = <0 1 2 3 4 5 6 7>;
783 };
784};
785
786&ecap0 {
787 status = "okay";
788 pinctrl-names = "default";
789 pinctrl-0 = <&ecap0_pins>;
790};
791
792&gpio0 {
793 pinctrl-names = "default";
794 pinctrl-0 = <&gpio0_pins>;
795 status = "okay";
796
797 sel-emmc-nand-hog {
798 gpio-hog;
799 gpios = <23 GPIO_ACTIVE_HIGH>;
800 /* SelEMMCorNAND selects between eMMC and NAND:
801 * Low: NAND
802 * High: eMMC
803 * When changing this line make sure the newly
804 * selected device node is enabled and the previously
805 * selected device node is disabled.
806 */
807 output-low;
808 line-name = "SelEMMCorNAND";
809 };
810};
811
812&gpio1 {
813 status = "okay";
814};
815
816&gpio3 {
817 status = "okay";
818};
819
820&gpio4 {
821 status = "okay";
822};
823
824&gpio5_target {
825 ti,no-reset-on-init;
826};
827
828&gpio5 {
829 pinctrl-names = "default";
830 pinctrl-0 = <&display_mux_pins>;
831 status = "okay";
832
833 sel-lcd-hdmi-hog {
834 /*
835 * SelLCDorHDMI selects between display and audio paths:
836 * Low: HDMI display with audio via HDMI
837 * High: LCD display with analog audio via aic3111 codec
838 */
839 gpio-hog;
840 gpios = <8 GPIO_ACTIVE_HIGH>;
841 output-high;
842 line-name = "SelLCDorHDMI";
843 };
844};
845
846&mmc1 {
847 status = "okay";
848 vmmc-supply = <&evm_v3_3d>;
849 bus-width = <4>;
850 pinctrl-names = "default";
851 pinctrl-0 = <&mmc1_pins>;
852 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
853};
854
855/* eMMC sits on mmc2 */
856&mmc2 {
857 /*
858 * When enabling eMMC, disable GPMC/NAND and set
859 * SelEMMCorNAND to output-high
860 */
861 status = "disabled";
862 vmmc-supply = <&evm_v3_3d>;
863 bus-width = <8>;
864 pinctrl-names = "default", "sleep";
865 pinctrl-0 = <&emmc_pins_default>;
866 pinctrl-1 = <&emmc_pins_sleep>;
867 non-removable;
868};
869
870&mmc3 {
871 status = "okay";
872 /* these are on the crossbar and are outlined in the
873 xbar-event-map element */
874 dmas = <&edma_xbar 30 0 1>,
875 <&edma_xbar 31 0 2>;
876 dma-names = "tx", "rx";
877 vmmc-supply = <&vmmcwl_fixed>;
878 bus-width = <4>;
879 pinctrl-names = "default", "sleep";
880 pinctrl-0 = <&mmc3_pins_default>;
881 pinctrl-1 = <&mmc3_pins_sleep>;
882 cap-power-off-card;
883 keep-power-in-suspend;
884 non-removable;
885
886 #address-cells = <1>;
887 #size-cells = <0>;
888 wlcore: wlcore@0 {
889 compatible = "ti,wl1835";
890 reg = <2>;
891 interrupt-parent = <&gpio1>;
892 interrupts = <23 IRQ_TYPE_EDGE_RISING>;
893 };
894};
895
896&uart3 {
897 status = "okay";
898 pinctrl-names = "default";
899 pinctrl-0 = <&uart3_pins>;
900};
901
902&usb2_phy1 {
903 status = "okay";
904};
905
906&usb1 {
907 dr_mode = "otg";
908 status = "okay";
909};
910
911&usb2_phy2 {
912 status = "okay";
913};
914
915&usb2 {
916 dr_mode = "host";
917 status = "okay";
918};
919
920&mac_sw {
921 pinctrl-names = "default", "sleep";
922 pinctrl-0 = <&cpsw_default>;
923 pinctrl-1 = <&cpsw_sleep>;
924 status = "okay";
925};
926
927&davinci_mdio_sw {
928 pinctrl-names = "default", "sleep";
929 pinctrl-0 = <&davinci_mdio_default>;
930 pinctrl-1 = <&davinci_mdio_sleep>;
931
932 ethphy0: ethernet-phy@0 {
933 reg = <0>;
934 };
935};
936
937&cpsw_port1 {
938 phy-handle = <ðphy0>;
939 phy-mode = "rgmii-rxid";
940 ti,dual-emac-pvid = <1>;
941};
942
943&cpsw_port2 {
944 status = "disabled";
945};
946
947&elm {
948 status = "okay";
949};
950
951&gpmc {
952 /*
953 * When enabling GPMC, disable eMMC and set
954 * SelEMMCorNAND to output-low
955 */
956 status = "okay";
957 pinctrl-names = "default";
958 pinctrl-0 = <&nand_flash_x8>;
959 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
960 nand@0,0 {
961 compatible = "ti,omap2-nand";
962 reg = <0 0 4>; /* device IO registers */
963 interrupt-parent = <&gpmc>;
964 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
965 <1 IRQ_TYPE_NONE>; /* termcount */
966 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
967 ti,nand-xfer-type = "prefetch-dma";
968 ti,nand-ecc-opt = "bch16";
969 ti,elm-id = <&elm>;
970 nand-bus-width = <8>;
971 gpmc,device-width = <1>;
972 gpmc,sync-clk-ps = <0>;
973 gpmc,cs-on-ns = <0>;
974 gpmc,cs-rd-off-ns = <40>;
975 gpmc,cs-wr-off-ns = <40>;
976 gpmc,adv-on-ns = <0>;
977 gpmc,adv-rd-off-ns = <25>;
978 gpmc,adv-wr-off-ns = <25>;
979 gpmc,we-on-ns = <0>;
980 gpmc,we-off-ns = <20>;
981 gpmc,oe-on-ns = <3>;
982 gpmc,oe-off-ns = <30>;
983 gpmc,access-ns = <30>;
984 gpmc,rd-cycle-ns = <40>;
985 gpmc,wr-cycle-ns = <40>;
986 gpmc,bus-turnaround-ns = <0>;
987 gpmc,cycle2cycle-delay-ns = <0>;
988 gpmc,clk-activation-ns = <0>;
989 gpmc,wr-access-ns = <40>;
990 gpmc,wr-data-mux-bus-ns = <0>;
991 /* MTD partition table */
992 /* All SPL-* partitions are sized to minimal length
993 * which can be independently programmable. For
994 * NAND flash this is equal to size of erase-block */
995 #address-cells = <1>;
996 #size-cells = <1>;
997 partition@0 {
998 label = "NAND.SPL";
999 reg = <0x00000000 0x00040000>;
1000 };
1001 partition@1 {
1002 label = "NAND.SPL.backup1";
1003 reg = <0x00040000 0x00040000>;
1004 };
1005 partition@2 {
1006 label = "NAND.SPL.backup2";
1007 reg = <0x00080000 0x00040000>;
1008 };
1009 partition@3 {
1010 label = "NAND.SPL.backup3";
1011 reg = <0x000c0000 0x00040000>;
1012 };
1013 partition@4 {
1014 label = "NAND.u-boot-spl-os";
1015 reg = <0x00100000 0x00080000>;
1016 };
1017 partition@5 {
1018 label = "NAND.u-boot";
1019 reg = <0x00180000 0x00100000>;
1020 };
1021 partition@6 {
1022 label = "NAND.u-boot-env";
1023 reg = <0x00280000 0x00040000>;
1024 };
1025 partition@7 {
1026 label = "NAND.u-boot-env.backup1";
1027 reg = <0x002c0000 0x00040000>;
1028 };
1029 partition@8 {
1030 label = "NAND.kernel";
1031 reg = <0x00300000 0x00700000>;
1032 };
1033 partition@9 {
1034 label = "NAND.file-system";
1035 reg = <0x00a00000 0x1f600000>;
1036 };
1037 };
1038};
1039
1040&dss {
1041 status = "okay";
1042
1043 pinctrl-names = "default";
1044 pinctrl-0 = <&dss_pins>;
1045
1046 port {
1047 dpi_out: endpoint {
1048 remote-endpoint = <&lcd_in>;
1049 data-lines = <24>;
1050 };
1051 };
1052};
1053
1054&dcan0 {
1055 pinctrl-names = "default", "sleep";
1056 pinctrl-0 = <&dcan0_default>;
1057 pinctrl-1 = <&dcan0_sleep>;
1058 status = "okay";
1059};
1060
1061&dcan1 {
1062 pinctrl-names = "default", "sleep";
1063 pinctrl-0 = <&dcan1_default>;
1064 pinctrl-1 = <&dcan1_sleep>;
1065 status = "okay";
1066};
1067
1068&vpfe0 {
1069 status = "okay";
1070 pinctrl-names = "default", "sleep";
1071 pinctrl-0 = <&vpfe0_pins_default>;
1072 pinctrl-1 = <&vpfe0_pins_sleep>;
1073
1074 port {
1075 vpfe0_ep: endpoint {
1076 remote-endpoint = <&ov2659_1>;
1077 ti,am437x-vpfe-interface = <0>;
1078 bus-width = <8>;
1079 hsync-active = <0>;
1080 vsync-active = <0>;
1081 };
1082 };
1083};
1084
1085&vpfe1 {
1086 status = "okay";
1087 pinctrl-names = "default", "sleep";
1088 pinctrl-0 = <&vpfe1_pins_default>;
1089 pinctrl-1 = <&vpfe1_pins_sleep>;
1090
1091 port {
1092 vpfe1_ep: endpoint {
1093 remote-endpoint = <&ov2659_0>;
1094 ti,am437x-vpfe-interface = <0>;
1095 bus-width = <8>;
1096 hsync-active = <0>;
1097 vsync-active = <0>;
1098 };
1099 };
1100};
1101
1102&mcasp1 {
1103 #sound-dai-cells = <0>;
1104 pinctrl-names = "default", "sleep";
1105 pinctrl-0 = <&mcasp1_pins>;
1106 pinctrl-1 = <&mcasp1_sleep_pins>;
1107
1108 status = "okay";
1109
1110 op-mode = <0>; /* MCASP_IIS_MODE */
1111 tdm-slots = <2>;
1112 /* 4 serializers */
1113 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1114 0 0 1 2
1115 >;
1116 tx-num-evt = <32>;
1117 rx-num-evt = <32>;
1118};
1119
1120&rtc {
1121 clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
1122 clock-names = "ext-clk", "int-clk";
1123 status = "okay";
1124};
1125
1126&cpu {
1127 cpu0-supply = <&dcdc2>;
1128};
1129
1130&wkup_m3_ipc {
1131 ti,set-io-isolation;
1132 firmware-name = "am43x-evm-scale-data.bin";
1133};
1134
1135&pruss1_mdio {
1136 status = "disabled";
1137};
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM437x GP EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h>
15#include <dt-bindings/pwm/pwm.h>
16#include <dt-bindings/gpio/gpio.h>
17
18/ {
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
21
22 aliases {
23 display0 = &lcd0;
24 };
25
26 evm_v3_3d: fixedregulator-v3_3d {
27 compatible = "regulator-fixed";
28 regulator-name = "evm_v3_3d";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 enable-active-high;
32 };
33
34 vtt_fixed: fixedregulator-vtt {
35 compatible = "regulator-fixed";
36 regulator-name = "vtt_fixed";
37 regulator-min-microvolt = <1500000>;
38 regulator-max-microvolt = <1500000>;
39 regulator-always-on;
40 regulator-boot-on;
41 enable-active-high;
42 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
43 };
44
45 vmmcwl_fixed: fixedregulator-mmcwl {
46 compatible = "regulator-fixed";
47 regulator-name = "vmmcwl_fixed";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
50 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
51 enable-active-high;
52 };
53
54 backlight {
55 compatible = "pwm-backlight";
56 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
57 brightness-levels = <0 51 53 56 62 75 101 152 255>;
58 default-brightness-level = <8>;
59 };
60
61 matrix_keypad: matrix_keypad@0 {
62 compatible = "gpio-matrix-keypad";
63 debounce-delay-ms = <5>;
64 col-scan-delay-us = <2>;
65
66 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
67 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
68 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
69
70 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
71 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
72
73 linux,keymap = <0x00000201 /* P1 */
74 0x00010202 /* P2 */
75 0x01000067 /* UP */
76 0x0101006a /* RIGHT */
77 0x02000069 /* LEFT */
78 0x0201006c>; /* DOWN */
79 };
80
81 lcd0: display {
82 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
83 label = "lcd";
84
85 panel-timing {
86 clock-frequency = <33000000>;
87 hactive = <800>;
88 vactive = <480>;
89 hfront-porch = <210>;
90 hback-porch = <16>;
91 hsync-len = <30>;
92 vback-porch = <10>;
93 vfront-porch = <22>;
94 vsync-len = <13>;
95 hsync-active = <0>;
96 vsync-active = <0>;
97 de-active = <1>;
98 pixelclk-active = <1>;
99 };
100
101 port {
102 lcd_in: endpoint {
103 remote-endpoint = <&dpi_out>;
104 };
105 };
106 };
107
108 /* fixed 12MHz oscillator */
109 refclk: oscillator {
110 #clock-cells = <0>;
111 compatible = "fixed-clock";
112 clock-frequency = <12000000>;
113 };
114
115 /* fixed 32k external oscillator clock */
116 clk_32k_rtc: clk_32k_rtc {
117 #clock-cells = <0>;
118 compatible = "fixed-clock";
119 clock-frequency = <32768>;
120 };
121
122 sound0: sound@0 {
123 compatible = "simple-audio-card";
124 simple-audio-card,name = "AM437x-GP-EVM";
125 simple-audio-card,widgets =
126 "Headphone", "Headphone Jack",
127 "Line", "Line In";
128 simple-audio-card,routing =
129 "Headphone Jack", "HPLOUT",
130 "Headphone Jack", "HPROUT",
131 "LINE1L", "Line In",
132 "LINE1R", "Line In";
133 simple-audio-card,format = "dsp_b";
134 simple-audio-card,bitclock-master = <&sound0_master>;
135 simple-audio-card,frame-master = <&sound0_master>;
136 simple-audio-card,bitclock-inversion;
137
138 simple-audio-card,cpu {
139 sound-dai = <&mcasp1>;
140 system-clock-frequency = <12000000>;
141 };
142
143 sound0_master: simple-audio-card,codec {
144 sound-dai = <&tlv320aic3106>;
145 system-clock-frequency = <12000000>;
146 };
147 };
148};
149
150&am43xx_pinmux {
151 pinctrl-names = "default", "sleep";
152 pinctrl-0 = <&wlan_pins_default>;
153 pinctrl-1 = <&wlan_pins_sleep>;
154
155 i2c0_pins: i2c0_pins {
156 pinctrl-single,pins = <
157 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
158 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
159 >;
160 };
161
162 i2c1_pins: i2c1_pins {
163 pinctrl-single,pins = <
164 AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
165 AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
166 >;
167 };
168
169 mmc1_pins: pinmux_mmc1_pins {
170 pinctrl-single,pins = <
171 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
172 >;
173 };
174
175 ecap0_pins: backlight_pins {
176 pinctrl-single,pins = <
177 AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
178 >;
179 };
180
181 pixcir_ts_pins: pixcir_ts_pins {
182 pinctrl-single,pins = <
183 AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
184 >;
185 };
186
187 cpsw_default: cpsw_default {
188 pinctrl-single,pins = <
189 /* Slave 1 */
190 AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
191 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
192 AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
193 AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
194 AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
195 AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
196 AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
197 AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
198 AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
199 AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
200 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
201 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
202 >;
203 };
204
205 cpsw_sleep: cpsw_sleep {
206 pinctrl-single,pins = <
207 /* Slave 1 reset value */
208 AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
209 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
210 AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
211 AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
212 AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
213 AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
214 AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
215 AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
216 AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
217 AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
218 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
219 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
220 >;
221 };
222
223 davinci_mdio_default: davinci_mdio_default {
224 pinctrl-single,pins = <
225 /* MDIO */
226 AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
227 AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
228 >;
229 };
230
231 davinci_mdio_sleep: davinci_mdio_sleep {
232 pinctrl-single,pins = <
233 /* MDIO reset value */
234 AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
235 AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
236 >;
237 };
238
239 nand_flash_x8: nand_flash_x8 {
240 pinctrl-single,pins = <
241 AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
242 AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
243 AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
244 AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
245 AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
246 AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
247 AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
248 AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
249 AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
250 AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
251 AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
252 AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
253 AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
254 AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
255 AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
256 >;
257 };
258
259 dss_pins: dss_pins {
260 pinctrl-single,pins = <
261 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
262 AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
263 AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
264 AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
265 AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
266 AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
267 AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
268 AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
269 AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
270 AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
271 AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
272 AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
273 AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
274 AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
275 AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
276 AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
277 AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
278 AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
279 AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
280 AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
281 AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
282 AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
283 AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
284 AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
285 AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
286 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
287 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
288 AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
289
290 >;
291 };
292
293 display_mux_pins: display_mux_pins {
294 pinctrl-single,pins = <
295 /* GPIO 5_8 to select LCD / HDMI */
296 AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
297 >;
298 };
299
300 dcan0_default: dcan0_default_pins {
301 pinctrl-single,pins = <
302 AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
303 AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
304 >;
305 };
306
307 dcan0_sleep: dcan0_sleep_pins {
308 pinctrl-single,pins = <
309 AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */
310 AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */
311 >;
312 };
313
314 dcan1_default: dcan1_default_pins {
315 pinctrl-single,pins = <
316 AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
317 AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
318 >;
319 };
320
321 dcan1_sleep: dcan1_sleep_pins {
322 pinctrl-single,pins = <
323 AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */
324 AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */
325 >;
326 };
327
328 vpfe0_pins_default: vpfe0_pins_default {
329 pinctrl-single,pins = <
330 AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
331 AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
332 AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
333 AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
334 AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
335 AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
336 AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
337 AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
338 AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
339 AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
340 AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
341 AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
342 AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
343 >;
344 };
345
346 vpfe0_pins_sleep: vpfe0_pins_sleep {
347 pinctrl-single,pins = <
348 AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
349 AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
350 AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
351 AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
352 AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
353 AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
354 AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
355 AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
356 AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
357 AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
358 AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
359 AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
360 AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
361 >;
362 };
363
364 vpfe1_pins_default: vpfe1_pins_default {
365 pinctrl-single,pins = <
366 AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
367 AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
368 AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
369 AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
370 AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
371 AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
372 AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
373 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
374 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
375 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
376 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
377 AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
378 AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
379 >;
380 };
381
382 vpfe1_pins_sleep: vpfe1_pins_sleep {
383 pinctrl-single,pins = <
384 AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
385 AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
386 AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
387 AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
388 AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
389 AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
390 AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
391 AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
392 AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
393 AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
394 AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
395 AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
396 AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
397 >;
398 };
399
400 mmc3_pins_default: pinmux_mmc3_pins_default {
401 pinctrl-single,pins = <
402 AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
403 AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
404 AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
405 AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
406 AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
407 AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
408 >;
409 };
410
411 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
412 pinctrl-single,pins = <
413 AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
414 AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
415 AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
416 AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
417 AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
418 AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
419 >;
420 };
421
422 wlan_pins_default: pinmux_wlan_pins_default {
423 pinctrl-single,pins = <
424 AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
425 AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
426 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
427 >;
428 };
429
430 wlan_pins_sleep: pinmux_wlan_pins_sleep {
431 pinctrl-single,pins = <
432 AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
433 AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
434 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
435 >;
436 };
437
438 uart3_pins: uart3_pins {
439 pinctrl-single,pins = <
440 AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
441 AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
442 AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
443 AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
444 >;
445 };
446
447 mcasp1_pins: mcasp1_pins {
448 pinctrl-single,pins = <
449 AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
450 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
451 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
452 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
453 >;
454 };
455
456 mcasp1_sleep_pins: mcasp1_sleep_pins {
457 pinctrl-single,pins = <
458 AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
459 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
460 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
461 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
462 >;
463 };
464
465 gpio0_pins: gpio0_pins {
466 pinctrl-single,pins = <
467 AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
468 >;
469 };
470
471 emmc_pins_default: emmc_pins_default {
472 pinctrl-single,pins = <
473 AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
474 AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
475 AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
476 AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
477 AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
478 AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
479 AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
480 AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
481 AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
482 AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
483 >;
484 };
485
486 emmc_pins_sleep: emmc_pins_sleep {
487 pinctrl-single,pins = <
488 AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
489 AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
490 AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
491 AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
492 AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
493 AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
494 AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
495 AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
496 AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
497 AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
498 >;
499 };
500};
501
502&i2c0 {
503 status = "okay";
504 pinctrl-names = "default";
505 pinctrl-0 = <&i2c0_pins>;
506 clock-frequency = <100000>;
507
508 tps65218: tps65218@24 {
509 reg = <0x24>;
510 compatible = "ti,tps65218";
511 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
512 interrupt-controller;
513 #interrupt-cells = <2>;
514
515 dcdc1: regulator-dcdc1 {
516 compatible = "ti,tps65218-dcdc1";
517 regulator-name = "vdd_core";
518 regulator-min-microvolt = <912000>;
519 regulator-max-microvolt = <1144000>;
520 regulator-boot-on;
521 regulator-always-on;
522 };
523
524 dcdc2: regulator-dcdc2 {
525 compatible = "ti,tps65218-dcdc2";
526 regulator-name = "vdd_mpu";
527 regulator-min-microvolt = <912000>;
528 regulator-max-microvolt = <1378000>;
529 regulator-boot-on;
530 regulator-always-on;
531 };
532
533 dcdc3: regulator-dcdc3 {
534 compatible = "ti,tps65218-dcdc3";
535 regulator-name = "vdcdc3";
536 regulator-min-microvolt = <1500000>;
537 regulator-max-microvolt = <1500000>;
538 regulator-boot-on;
539 regulator-always-on;
540 };
541 dcdc5: regulator-dcdc5 {
542 compatible = "ti,tps65218-dcdc5";
543 regulator-name = "v1_0bat";
544 regulator-min-microvolt = <1000000>;
545 regulator-max-microvolt = <1000000>;
546 regulator-boot-on;
547 regulator-always-on;
548 };
549
550 dcdc6: regulator-dcdc6 {
551 compatible = "ti,tps65218-dcdc6";
552 regulator-name = "v1_8bat";
553 regulator-min-microvolt = <1800000>;
554 regulator-max-microvolt = <1800000>;
555 regulator-boot-on;
556 regulator-always-on;
557 };
558
559 ldo1: regulator-ldo1 {
560 compatible = "ti,tps65218-ldo1";
561 regulator-min-microvolt = <1800000>;
562 regulator-max-microvolt = <1800000>;
563 regulator-boot-on;
564 regulator-always-on;
565 };
566 };
567
568 ov2659@30 {
569 compatible = "ovti,ov2659";
570 reg = <0x30>;
571
572 clocks = <&refclk 0>;
573 clock-names = "xvclk";
574
575 port {
576 ov2659_0: endpoint {
577 remote-endpoint = <&vpfe1_ep>;
578 link-frequencies = /bits/ 64 <70000000>;
579 };
580 };
581 };
582};
583
584&i2c1 {
585 status = "okay";
586 pinctrl-names = "default";
587 pinctrl-0 = <&i2c1_pins>;
588 pixcir_ts@5c {
589 compatible = "pixcir,pixcir_tangoc";
590 pinctrl-names = "default";
591 pinctrl-0 = <&pixcir_ts_pins>;
592 reg = <0x5c>;
593
594 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
595
596 /*
597 * 0x264 represents the offset of padconf register of
598 * gpio3_22 from am43xx_pinmux base.
599 */
600 interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
601 <&am43xx_pinmux 0x264>;
602 interrupt-names = "tsc", "wakeup";
603
604 touchscreen-size-x = <1024>;
605 touchscreen-size-y = <600>;
606 wakeup-source;
607 };
608
609 ov2659@30 {
610 compatible = "ovti,ov2659";
611 reg = <0x30>;
612
613 clocks = <&refclk 0>;
614 clock-names = "xvclk";
615
616 port {
617 ov2659_1: endpoint {
618 remote-endpoint = <&vpfe0_ep>;
619 link-frequencies = /bits/ 64 <70000000>;
620 };
621 };
622 };
623
624 tlv320aic3106: tlv320aic3106@1b {
625 #sound-dai-cells = <0>;
626 compatible = "ti,tlv320aic3106";
627 reg = <0x1b>;
628 status = "okay";
629
630 /* Regulators */
631 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
632 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
633 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
634 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
635 };
636};
637
638&epwmss0 {
639 status = "okay";
640};
641
642&tscadc {
643 status = "okay";
644
645 adc {
646 ti,adc-channels = <0 1 2 3 4 5 6 7>;
647 };
648};
649
650&ecap0 {
651 status = "okay";
652 pinctrl-names = "default";
653 pinctrl-0 = <&ecap0_pins>;
654};
655
656&gpio0 {
657 pinctrl-names = "default";
658 pinctrl-0 = <&gpio0_pins>;
659 status = "okay";
660
661 p23 {
662 gpio-hog;
663 gpios = <23 GPIO_ACTIVE_HIGH>;
664 /* SelEMMCorNAND selects between eMMC and NAND:
665 * Low: NAND
666 * High: eMMC
667 * When changing this line make sure the newly
668 * selected device node is enabled and the previously
669 * selected device node is disabled.
670 */
671 output-low;
672 line-name = "SelEMMCorNAND";
673 };
674};
675
676&gpio1 {
677 status = "okay";
678};
679
680&gpio3 {
681 status = "okay";
682};
683
684&gpio4 {
685 status = "okay";
686};
687
688&gpio5 {
689 pinctrl-names = "default";
690 pinctrl-0 = <&display_mux_pins>;
691 status = "okay";
692 ti,no-reset-on-init;
693
694 p8 {
695 /*
696 * SelLCDorHDMI selects between display and audio paths:
697 * Low: HDMI display with audio via HDMI
698 * High: LCD display with analog audio via aic3111 codec
699 */
700 gpio-hog;
701 gpios = <8 GPIO_ACTIVE_HIGH>;
702 output-high;
703 line-name = "SelLCDorHDMI";
704 };
705};
706
707&mmc1 {
708 status = "okay";
709 vmmc-supply = <&evm_v3_3d>;
710 bus-width = <4>;
711 pinctrl-names = "default";
712 pinctrl-0 = <&mmc1_pins>;
713 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
714};
715
716/* eMMC sits on mmc2 */
717&mmc2 {
718 /*
719 * When enabling eMMC, disable GPMC/NAND and set
720 * SelEMMCorNAND to output-high
721 */
722 status = "disabled";
723 vmmc-supply = <&evm_v3_3d>;
724 bus-width = <8>;
725 pinctrl-names = "default", "sleep";
726 pinctrl-0 = <&emmc_pins_default>;
727 pinctrl-1 = <&emmc_pins_sleep>;
728 ti,non-removable;
729};
730
731&mmc3 {
732 status = "okay";
733 /* these are on the crossbar and are outlined in the
734 xbar-event-map element */
735 dmas = <&edma_xbar 30 0 1>,
736 <&edma_xbar 31 0 2>;
737 dma-names = "tx", "rx";
738 vmmc-supply = <&vmmcwl_fixed>;
739 bus-width = <4>;
740 pinctrl-names = "default", "sleep";
741 pinctrl-0 = <&mmc3_pins_default>;
742 pinctrl-1 = <&mmc3_pins_sleep>;
743 cap-power-off-card;
744 keep-power-in-suspend;
745 ti,non-removable;
746
747 #address-cells = <1>;
748 #size-cells = <0>;
749 wlcore: wlcore@0 {
750 compatible = "ti,wl1835";
751 reg = <2>;
752 interrupt-parent = <&gpio1>;
753 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
754 };
755};
756
757&uart3 {
758 status = "okay";
759 pinctrl-names = "default";
760 pinctrl-0 = <&uart3_pins>;
761};
762
763&usb2_phy1 {
764 status = "okay";
765};
766
767&usb1 {
768 dr_mode = "peripheral";
769 status = "okay";
770};
771
772&usb2_phy2 {
773 status = "okay";
774};
775
776&usb2 {
777 dr_mode = "host";
778 status = "okay";
779};
780
781&mac {
782 slaves = <1>;
783 pinctrl-names = "default", "sleep";
784 pinctrl-0 = <&cpsw_default>;
785 pinctrl-1 = <&cpsw_sleep>;
786 status = "okay";
787};
788
789&davinci_mdio {
790 pinctrl-names = "default", "sleep";
791 pinctrl-0 = <&davinci_mdio_default>;
792 pinctrl-1 = <&davinci_mdio_sleep>;
793 status = "okay";
794};
795
796&cpsw_emac0 {
797 phy_id = <&davinci_mdio>, <0>;
798 phy-mode = "rgmii";
799};
800
801&elm {
802 status = "okay";
803};
804
805&gpmc {
806 /*
807 * When enabling GPMC, disable eMMC and set
808 * SelEMMCorNAND to output-low
809 */
810 status = "okay";
811 pinctrl-names = "default";
812 pinctrl-0 = <&nand_flash_x8>;
813 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
814 nand@0,0 {
815 compatible = "ti,omap2-nand";
816 reg = <0 0 4>; /* device IO registers */
817 interrupt-parent = <&gpmc>;
818 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
819 <1 IRQ_TYPE_NONE>; /* termcount */
820 ti,nand-ecc-opt = "bch16";
821 ti,elm-id = <&elm>;
822 nand-bus-width = <8>;
823 gpmc,device-width = <1>;
824 gpmc,sync-clk-ps = <0>;
825 gpmc,cs-on-ns = <0>;
826 gpmc,cs-rd-off-ns = <40>;
827 gpmc,cs-wr-off-ns = <40>;
828 gpmc,adv-on-ns = <0>;
829 gpmc,adv-rd-off-ns = <25>;
830 gpmc,adv-wr-off-ns = <25>;
831 gpmc,we-on-ns = <0>;
832 gpmc,we-off-ns = <20>;
833 gpmc,oe-on-ns = <3>;
834 gpmc,oe-off-ns = <30>;
835 gpmc,access-ns = <30>;
836 gpmc,rd-cycle-ns = <40>;
837 gpmc,wr-cycle-ns = <40>;
838 gpmc,bus-turnaround-ns = <0>;
839 gpmc,cycle2cycle-delay-ns = <0>;
840 gpmc,clk-activation-ns = <0>;
841 gpmc,wr-access-ns = <40>;
842 gpmc,wr-data-mux-bus-ns = <0>;
843 /* MTD partition table */
844 /* All SPL-* partitions are sized to minimal length
845 * which can be independently programmable. For
846 * NAND flash this is equal to size of erase-block */
847 #address-cells = <1>;
848 #size-cells = <1>;
849 partition@0 {
850 label = "NAND.SPL";
851 reg = <0x00000000 0x00040000>;
852 };
853 partition@1 {
854 label = "NAND.SPL.backup1";
855 reg = <0x00040000 0x00040000>;
856 };
857 partition@2 {
858 label = "NAND.SPL.backup2";
859 reg = <0x00080000 0x00040000>;
860 };
861 partition@3 {
862 label = "NAND.SPL.backup3";
863 reg = <0x000c0000 0x00040000>;
864 };
865 partition@4 {
866 label = "NAND.u-boot-spl-os";
867 reg = <0x00100000 0x00080000>;
868 };
869 partition@5 {
870 label = "NAND.u-boot";
871 reg = <0x00180000 0x00100000>;
872 };
873 partition@6 {
874 label = "NAND.u-boot-env";
875 reg = <0x00280000 0x00040000>;
876 };
877 partition@7 {
878 label = "NAND.u-boot-env.backup1";
879 reg = <0x002c0000 0x00040000>;
880 };
881 partition@8 {
882 label = "NAND.kernel";
883 reg = <0x00300000 0x00700000>;
884 };
885 partition@9 {
886 label = "NAND.file-system";
887 reg = <0x00a00000 0x1f600000>;
888 };
889 };
890};
891
892&dss {
893 status = "ok";
894
895 pinctrl-names = "default";
896 pinctrl-0 = <&dss_pins>;
897
898 port {
899 dpi_out: endpoint@0 {
900 remote-endpoint = <&lcd_in>;
901 data-lines = <24>;
902 };
903 };
904};
905
906&dcan0 {
907 pinctrl-names = "default", "sleep";
908 pinctrl-0 = <&dcan0_default>;
909 pinctrl-1 = <&dcan0_sleep>;
910 status = "okay";
911};
912
913&dcan1 {
914 pinctrl-names = "default", "sleep";
915 pinctrl-0 = <&dcan1_default>;
916 pinctrl-1 = <&dcan1_sleep>;
917 status = "okay";
918};
919
920&vpfe0 {
921 status = "okay";
922 pinctrl-names = "default", "sleep";
923 pinctrl-0 = <&vpfe0_pins_default>;
924 pinctrl-1 = <&vpfe0_pins_sleep>;
925
926 port {
927 vpfe0_ep: endpoint {
928 remote-endpoint = <&ov2659_1>;
929 ti,am437x-vpfe-interface = <0>;
930 bus-width = <8>;
931 hsync-active = <0>;
932 vsync-active = <0>;
933 };
934 };
935};
936
937&vpfe1 {
938 status = "okay";
939 pinctrl-names = "default", "sleep";
940 pinctrl-0 = <&vpfe1_pins_default>;
941 pinctrl-1 = <&vpfe1_pins_sleep>;
942
943 port {
944 vpfe1_ep: endpoint {
945 remote-endpoint = <&ov2659_0>;
946 ti,am437x-vpfe-interface = <0>;
947 bus-width = <8>;
948 hsync-active = <0>;
949 vsync-active = <0>;
950 };
951 };
952};
953
954&mcasp1 {
955 #sound-dai-cells = <0>;
956 pinctrl-names = "default", "sleep";
957 pinctrl-0 = <&mcasp1_pins>;
958 pinctrl-1 = <&mcasp1_sleep_pins>;
959
960 status = "okay";
961
962 op-mode = <0>; /* MCASP_IIS_MODE */
963 tdm-slots = <2>;
964 /* 4 serializers */
965 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
966 0 0 1 2
967 >;
968 tx-num-evt = <32>;
969 rx-num-evt = <32>;
970};
971
972&rtc {
973 clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
974 clock-names = "ext-clk", "int-clk";
975 status = "okay";
976};