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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * AMD Platform Management Framework Driver
4 *
5 * Copyright (c) 2022, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11#ifndef PMF_H
12#define PMF_H
13
14#include <linux/acpi.h>
15#include <linux/platform_profile.h>
16
17/* APMF Functions */
18#define APMF_FUNC_VERIFY_INTERFACE 0
19#define APMF_FUNC_GET_SYS_PARAMS 1
20#define APMF_FUNC_SBIOS_REQUESTS 2
21#define APMF_FUNC_SBIOS_HEARTBEAT 4
22#define APMF_FUNC_AUTO_MODE 5
23#define APMF_FUNC_SET_FAN_IDX 7
24#define APMF_FUNC_STATIC_SLIDER_GRANULAR 9
25#define APMF_FUNC_DYN_SLIDER_AC 11
26#define APMF_FUNC_DYN_SLIDER_DC 12
27
28/* Message Definitions */
29#define SET_SPL 0x03 /* SPL: Sustained Power Limit */
30#define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */
31#define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */
32#define GET_SPL 0x0B
33#define GET_SPPT 0x0D
34#define GET_FPPT 0x0F
35#define SET_DRAM_ADDR_HIGH 0x14
36#define SET_DRAM_ADDR_LOW 0x15
37#define SET_TRANSFER_TABLE 0x16
38#define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */
39#define SET_STT_LIMIT_APU 0x19
40#define SET_STT_LIMIT_HS2 0x1A
41#define SET_SPPT_APU_ONLY 0x1D
42#define GET_SPPT_APU_ONLY 0x1E
43#define GET_STT_MIN_LIMIT 0x1F
44#define GET_STT_LIMIT_APU 0x20
45#define GET_STT_LIMIT_HS2 0x21
46
47/* Fan Index for Auto Mode */
48#define FAN_INDEX_AUTO 0xFFFFFFFF
49
50#define ARG_NONE 0
51#define AVG_SAMPLE_SIZE 3
52
53/* AMD PMF BIOS interfaces */
54struct apmf_verify_interface {
55 u16 size;
56 u16 version;
57 u32 notification_mask;
58 u32 supported_functions;
59} __packed;
60
61struct apmf_system_params {
62 u16 size;
63 u32 valid_mask;
64 u32 flags;
65 u8 command_code;
66 u32 heartbeat_int;
67} __packed;
68
69struct apmf_sbios_req {
70 u16 size;
71 u32 pending_req;
72 u8 rsd;
73 u8 cql_event;
74 u8 amt_event;
75 u32 fppt;
76 u32 sppt;
77 u32 fppt_apu_only;
78 u32 spl;
79 u32 stt_min_limit;
80 u8 skin_temp_apu;
81 u8 skin_temp_hs2;
82} __packed;
83
84struct apmf_fan_idx {
85 u16 size;
86 u8 fan_ctl_mode;
87 u32 fan_ctl_idx;
88} __packed;
89
90struct smu_pmf_metrics {
91 u16 gfxclk_freq; /* in MHz */
92 u16 socclk_freq; /* in MHz */
93 u16 vclk_freq; /* in MHz */
94 u16 dclk_freq; /* in MHz */
95 u16 memclk_freq; /* in MHz */
96 u16 spare;
97 u16 gfx_activity; /* in Centi */
98 u16 uvd_activity; /* in Centi */
99 u16 voltage[2]; /* in mV */
100 u16 currents[2]; /* in mA */
101 u16 power[2];/* in mW */
102 u16 core_freq[8]; /* in MHz */
103 u16 core_power[8]; /* in mW */
104 u16 core_temp[8]; /* in centi-Celsius */
105 u16 l3_freq; /* in MHz */
106 u16 l3_temp; /* in centi-Celsius */
107 u16 gfx_temp; /* in centi-Celsius */
108 u16 soc_temp; /* in centi-Celsius */
109 u16 throttler_status;
110 u16 current_socketpower; /* in mW */
111 u16 stapm_orig_limit; /* in W */
112 u16 stapm_cur_limit; /* in W */
113 u32 apu_power; /* in mW */
114 u32 dgpu_power; /* in mW */
115 u16 vdd_tdc_val; /* in mA */
116 u16 soc_tdc_val; /* in mA */
117 u16 vdd_edc_val; /* in mA */
118 u16 soc_edcv_al; /* in mA */
119 u16 infra_cpu_maxfreq; /* in MHz */
120 u16 infra_gfx_maxfreq; /* in MHz */
121 u16 skin_temp; /* in centi-Celsius */
122 u16 device_state;
123} __packed;
124
125enum amd_stt_skin_temp {
126 STT_TEMP_APU,
127 STT_TEMP_HS2,
128 STT_TEMP_COUNT,
129};
130
131enum amd_slider_op {
132 SLIDER_OP_GET,
133 SLIDER_OP_SET,
134};
135
136enum power_source {
137 POWER_SOURCE_AC,
138 POWER_SOURCE_DC,
139 POWER_SOURCE_MAX,
140};
141
142enum power_modes {
143 POWER_MODE_PERFORMANCE,
144 POWER_MODE_BALANCED_POWER,
145 POWER_MODE_POWER_SAVER,
146 POWER_MODE_MAX,
147};
148
149struct amd_pmf_dev {
150 void __iomem *regbase;
151 void __iomem *smu_virt_addr;
152 void *buf;
153 u32 base_addr;
154 u32 cpu_id;
155 struct device *dev;
156 struct mutex lock; /* protects the PMF interface */
157 u32 supported_func;
158 enum platform_profile_option current_profile;
159 struct platform_profile_handler pprof;
160 struct dentry *dbgfs_dir;
161 int hb_interval; /* SBIOS heartbeat interval */
162 struct delayed_work heart_beat;
163 struct smu_pmf_metrics m_table;
164 struct delayed_work work_buffer;
165 ktime_t start_time;
166 int socket_power_history[AVG_SAMPLE_SIZE];
167 int socket_power_history_idx;
168 bool amt_enabled;
169 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */
170 bool cnqf_enabled;
171 bool cnqf_supported;
172 struct notifier_block pwr_src_notifier;
173};
174
175struct apmf_sps_prop_granular {
176 u32 fppt;
177 u32 sppt;
178 u32 sppt_apu_only;
179 u32 spl;
180 u32 stt_min;
181 u8 stt_skin_temp[STT_TEMP_COUNT];
182 u32 fan_id;
183} __packed;
184
185/* Static Slider */
186struct apmf_static_slider_granular_output {
187 u16 size;
188 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX];
189} __packed;
190
191struct amd_pmf_static_slider_granular {
192 u16 size;
193 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX];
194};
195
196struct fan_table_control {
197 bool manual;
198 unsigned long fan_id;
199};
200
201struct power_table_control {
202 u32 spl;
203 u32 sppt;
204 u32 fppt;
205 u32 sppt_apu_only;
206 u32 stt_min;
207 u32 stt_skin_temp[STT_TEMP_COUNT];
208 u32 reserved[16];
209};
210
211/* Auto Mode Layer */
212enum auto_mode_transition_priority {
213 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */
214 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
215 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
216 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */
217 AUTO_TRANSITION_MAX,
218};
219
220enum auto_mode_mode {
221 AUTO_QUIET,
222 AUTO_BALANCE,
223 AUTO_PERFORMANCE_ON_LAP,
224 AUTO_PERFORMANCE,
225 AUTO_MODE_MAX,
226};
227
228struct auto_mode_trans_params {
229 u32 time_constant; /* minimum time required to switch to next mode */
230 u32 power_delta; /* delta power to shift mode */
231 u32 power_threshold;
232 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */
233 u32 applied;
234 enum auto_mode_mode target_mode;
235 u32 shifting_up;
236};
237
238struct auto_mode_mode_settings {
239 struct power_table_control power_control;
240 struct fan_table_control fan_control;
241 u32 power_floor;
242};
243
244struct auto_mode_mode_config {
245 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX];
246 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX];
247 enum auto_mode_mode current_mode;
248};
249
250struct apmf_auto_mode {
251 u16 size;
252 /* time constant */
253 u32 balanced_to_perf;
254 u32 perf_to_balanced;
255 u32 quiet_to_balanced;
256 u32 balanced_to_quiet;
257 /* power floor */
258 u32 pfloor_perf;
259 u32 pfloor_balanced;
260 u32 pfloor_quiet;
261 /* Power delta for mode change */
262 u32 pd_balanced_to_perf;
263 u32 pd_perf_to_balanced;
264 u32 pd_quiet_to_balanced;
265 u32 pd_balanced_to_quiet;
266 /* skin temperature limits */
267 u8 stt_apu_perf_on_lap; /* CQL ON */
268 u8 stt_hs2_perf_on_lap; /* CQL ON */
269 u8 stt_apu_perf;
270 u8 stt_hs2_perf;
271 u8 stt_apu_balanced;
272 u8 stt_hs2_balanced;
273 u8 stt_apu_quiet;
274 u8 stt_hs2_quiet;
275 u32 stt_min_limit_perf_on_lap; /* CQL ON */
276 u32 stt_min_limit_perf;
277 u32 stt_min_limit_balanced;
278 u32 stt_min_limit_quiet;
279 /* SPL based */
280 u32 fppt_perf_on_lap; /* CQL ON */
281 u32 sppt_perf_on_lap; /* CQL ON */
282 u32 spl_perf_on_lap; /* CQL ON */
283 u32 sppt_apu_only_perf_on_lap; /* CQL ON */
284 u32 fppt_perf;
285 u32 sppt_perf;
286 u32 spl_perf;
287 u32 sppt_apu_only_perf;
288 u32 fppt_balanced;
289 u32 sppt_balanced;
290 u32 spl_balanced;
291 u32 sppt_apu_only_balanced;
292 u32 fppt_quiet;
293 u32 sppt_quiet;
294 u32 spl_quiet;
295 u32 sppt_apu_only_quiet;
296 /* Fan ID */
297 u32 fan_id_perf;
298 u32 fan_id_balanced;
299 u32 fan_id_quiet;
300} __packed;
301
302/* CnQF Layer */
303enum cnqf_trans_priority {
304 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */
305 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */
306 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */
307 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */
308 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */
309 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */
310 CNQF_TRANSITION_MAX,
311};
312
313enum cnqf_mode {
314 CNQF_MODE_QUIET,
315 CNQF_MODE_BALANCE,
316 CNQF_MODE_PERFORMANCE,
317 CNQF_MODE_TURBO,
318 CNQF_MODE_MAX,
319};
320
321enum apmf_cnqf_pos {
322 APMF_CNQF_TURBO,
323 APMF_CNQF_PERFORMANCE,
324 APMF_CNQF_BALANCE,
325 APMF_CNQF_QUIET,
326 APMF_CNQF_MAX,
327};
328
329struct cnqf_mode_settings {
330 struct power_table_control power_control;
331 struct fan_table_control fan_control;
332 u32 power_floor;
333};
334
335struct cnqf_tran_params {
336 u32 time_constant; /* minimum time required to switch to next mode */
337 u32 power_threshold;
338 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */
339 u32 total_power;
340 u32 count;
341 bool priority;
342 bool shifting_up;
343 enum cnqf_mode target_mode;
344};
345
346struct cnqf_config {
347 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX];
348 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX];
349 struct power_table_control defaults;
350 enum cnqf_mode current_mode;
351 u32 power_src;
352 u32 avg_power;
353};
354
355struct apmf_cnqf_power_set {
356 u32 pfloor;
357 u32 fppt;
358 u32 sppt;
359 u32 sppt_apu_only;
360 u32 spl;
361 u32 stt_min_limit;
362 u8 stt_skintemp[STT_TEMP_COUNT];
363 u32 fan_id;
364} __packed;
365
366struct apmf_dyn_slider_output {
367 u16 size;
368 u16 flags;
369 u32 t_perf_to_turbo;
370 u32 t_balanced_to_perf;
371 u32 t_quiet_to_balanced;
372 u32 t_balanced_to_quiet;
373 u32 t_perf_to_balanced;
374 u32 t_turbo_to_perf;
375 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX];
376} __packed;
377
378/* Core Layer */
379int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);
380void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev);
381int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);
382int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);
383int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev);
384int amd_pmf_get_power_source(void);
385int apmf_install_handler(struct amd_pmf_dev *pmf_dev);
386
387/* SPS Layer */
388int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf);
389void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
390 struct amd_pmf_static_slider_granular *table);
391int amd_pmf_init_sps(struct amd_pmf_dev *dev);
392void amd_pmf_deinit_sps(struct amd_pmf_dev *dev);
393int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev,
394 struct apmf_static_slider_granular_output *output);
395bool is_pprof_balanced(struct amd_pmf_dev *pmf);
396
397
398int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx);
399int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf);
400
401/* Auto Mode Layer */
402int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data);
403void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev);
404void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev);
405void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms);
406int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req);
407
408void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event);
409int amd_pmf_reset_amt(struct amd_pmf_dev *dev);
410void amd_pmf_handle_amt(struct amd_pmf_dev *dev);
411
412/* CnQF Layer */
413int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
414int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data);
415int amd_pmf_init_cnqf(struct amd_pmf_dev *dev);
416void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev);
417int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms);
418extern const struct attribute_group cnqf_feature_attribute_group;
419
420#endif /* PMF_H */