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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2016 Marvell, All Rights Reserved.
4 *
5 * Author: Hu Ziji <huziji@marvell.com>
6 * Date: 2016-8-24
7 */
8#ifndef SDHCI_XENON_H_
9#define SDHCI_XENON_H_
10
11/* Register Offset of Xenon SDHC self-defined register */
12#define XENON_SYS_CFG_INFO 0x0104
13#define XENON_SLOT_TYPE_SDIO_SHIFT 24
14#define XENON_NR_SUPPORTED_SLOT_MASK 0x7
15
16#define XENON_SYS_OP_CTRL 0x0108
17#define XENON_AUTO_CLKGATE_DISABLE_MASK BIT(20)
18#define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT 8
19#define XENON_SLOT_ENABLE_SHIFT 0
20
21#define XENON_SYS_EXT_OP_CTRL 0x010C
22#define XENON_MASK_CMD_CONFLICT_ERR BIT(8)
23
24#define XENON_SLOT_OP_STATUS_CTRL 0x0128
25#define XENON_TUN_CONSECUTIVE_TIMES_SHIFT 16
26#define XENON_TUN_CONSECUTIVE_TIMES_MASK 0x7
27#define XENON_TUN_CONSECUTIVE_TIMES 0x4
28#define XENON_TUNING_STEP_SHIFT 12
29#define XENON_TUNING_STEP_MASK 0xF
30#define XENON_TUNING_STEP_DIVIDER BIT(6)
31
32#define XENON_SLOT_EMMC_CTRL 0x0130
33#define XENON_ENABLE_RESP_STROBE BIT(25)
34#define XENON_ENABLE_DATA_STROBE BIT(24)
35
36#define XENON_SLOT_RETUNING_REQ_CTRL 0x0144
37/* retuning compatible */
38#define XENON_RETUNING_COMPATIBLE 0x1
39
40#define XENON_SLOT_EXT_PRESENT_STATE 0x014C
41#define XENON_DLL_LOCK_STATE 0x1
42
43#define XENON_SLOT_DLL_CUR_DLY_VAL 0x0150
44
45/* Tuning Parameter */
46#define XENON_TMR_RETUN_NO_PRESENT 0xF
47#define XENON_DEF_TUNING_COUNT 0x9
48
49#define XENON_DEFAULT_SDCLK_FREQ 400000
50#define XENON_LOWEST_SDCLK_FREQ 100000
51
52/* Xenon specific Mode Select value */
53#define XENON_CTRL_HS200 0x5
54#define XENON_CTRL_HS400 0x6
55
56enum xenon_variant {
57 XENON_A3700,
58 XENON_AP806,
59 XENON_AP807,
60 XENON_CP110
61};
62
63struct xenon_priv {
64 unsigned char tuning_count;
65 /* idx of SDHC */
66 u8 sdhc_id;
67
68 /*
69 * eMMC/SD/SDIO require different register settings.
70 * Xenon driver has to recognize card type
71 * before mmc_host->card is not available.
72 * This field records the card type during init.
73 * It is updated in xenon_init_card().
74 *
75 * It is only valid during initialization after it is updated.
76 * Do not access this variable in normal transfers after
77 * initialization completes.
78 */
79 unsigned int init_card_type;
80
81 /*
82 * The bus_width, timing, and clock fields in below
83 * record the current ios setting of Xenon SDHC.
84 * Driver will adjust PHY setting if any change to
85 * ios affects PHY timing.
86 */
87 unsigned char bus_width;
88 unsigned char timing;
89 unsigned int clock;
90 struct clk *axi_clk;
91
92 int phy_type;
93 /*
94 * Contains board-specific PHY parameters
95 * passed from device tree.
96 */
97 void *phy_params;
98 struct xenon_emmc_phy_regs *emmc_phy_regs;
99 bool restore_needed;
100 enum xenon_variant hw_version;
101};
102
103int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
104int xenon_phy_parse_params(struct device *dev,
105 struct sdhci_host *host);
106void xenon_soc_pad_ctrl(struct sdhci_host *host,
107 unsigned char signal_voltage);
108#endif
1/*
2 * Copyright (C) 2016 Marvell, All Rights Reserved.
3 *
4 * Author: Hu Ziji <huziji@marvell.com>
5 * Date: 2016-8-24
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 */
11#ifndef SDHCI_XENON_H_
12#define SDHCI_XENON_H_
13
14/* Register Offset of Xenon SDHC self-defined register */
15#define XENON_SYS_CFG_INFO 0x0104
16#define XENON_SLOT_TYPE_SDIO_SHIFT 24
17#define XENON_NR_SUPPORTED_SLOT_MASK 0x7
18
19#define XENON_SYS_OP_CTRL 0x0108
20#define XENON_AUTO_CLKGATE_DISABLE_MASK BIT(20)
21#define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT 8
22#define XENON_SLOT_ENABLE_SHIFT 0
23
24#define XENON_SYS_EXT_OP_CTRL 0x010C
25#define XENON_MASK_CMD_CONFLICT_ERR BIT(8)
26
27#define XENON_SLOT_OP_STATUS_CTRL 0x0128
28#define XENON_TUN_CONSECUTIVE_TIMES_SHIFT 16
29#define XENON_TUN_CONSECUTIVE_TIMES_MASK 0x7
30#define XENON_TUN_CONSECUTIVE_TIMES 0x4
31#define XENON_TUNING_STEP_SHIFT 12
32#define XENON_TUNING_STEP_MASK 0xF
33#define XENON_TUNING_STEP_DIVIDER BIT(6)
34
35#define XENON_SLOT_EMMC_CTRL 0x0130
36#define XENON_ENABLE_RESP_STROBE BIT(25)
37#define XENON_ENABLE_DATA_STROBE BIT(24)
38
39#define XENON_SLOT_RETUNING_REQ_CTRL 0x0144
40/* retuning compatible */
41#define XENON_RETUNING_COMPATIBLE 0x1
42
43#define XENON_SLOT_EXT_PRESENT_STATE 0x014C
44#define XENON_DLL_LOCK_STATE 0x1
45
46#define XENON_SLOT_DLL_CUR_DLY_VAL 0x0150
47
48/* Tuning Parameter */
49#define XENON_TMR_RETUN_NO_PRESENT 0xF
50#define XENON_DEF_TUNING_COUNT 0x9
51
52#define XENON_DEFAULT_SDCLK_FREQ 400000
53#define XENON_LOWEST_SDCLK_FREQ 100000
54
55/* Xenon specific Mode Select value */
56#define XENON_CTRL_HS200 0x5
57#define XENON_CTRL_HS400 0x6
58
59struct xenon_priv {
60 unsigned char tuning_count;
61 /* idx of SDHC */
62 u8 sdhc_id;
63
64 /*
65 * eMMC/SD/SDIO require different register settings.
66 * Xenon driver has to recognize card type
67 * before mmc_host->card is not available.
68 * This field records the card type during init.
69 * It is updated in xenon_init_card().
70 *
71 * It is only valid during initialization after it is updated.
72 * Do not access this variable in normal transfers after
73 * initialization completes.
74 */
75 unsigned int init_card_type;
76
77 /*
78 * The bus_width, timing, and clock fields in below
79 * record the current ios setting of Xenon SDHC.
80 * Driver will adjust PHY setting if any change to
81 * ios affects PHY timing.
82 */
83 unsigned char bus_width;
84 unsigned char timing;
85 unsigned int clock;
86 struct clk *axi_clk;
87
88 int phy_type;
89 /*
90 * Contains board-specific PHY parameters
91 * passed from device tree.
92 */
93 void *phy_params;
94 struct xenon_emmc_phy_regs *emmc_phy_regs;
95 bool restore_needed;
96};
97
98int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
99int xenon_phy_parse_dt(struct device_node *np,
100 struct sdhci_host *host);
101void xenon_soc_pad_ctrl(struct sdhci_host *host,
102 unsigned char signal_voltage);
103#endif