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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2021-2022, NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <soc/tegra/mc.h>
7
8#include <dt-bindings/memory/tegra234-mc.h>
9
10#include "mc.h"
11
12static const struct tegra_mc_client tegra234_mc_clients[] = {
13 {
14 .id = TEGRA234_MEMORY_CLIENT_MGBEARD,
15 .name = "mgbeard",
16 .sid = TEGRA234_SID_MGBE,
17 .regs = {
18 .sid = {
19 .override = 0x2c0,
20 .security = 0x2c4,
21 },
22 },
23 }, {
24 .id = TEGRA234_MEMORY_CLIENT_MGBEBRD,
25 .name = "mgbebrd",
26 .sid = TEGRA234_SID_MGBE_VF1,
27 .regs = {
28 .sid = {
29 .override = 0x2c8,
30 .security = 0x2cc,
31 },
32 },
33 }, {
34 .id = TEGRA234_MEMORY_CLIENT_MGBECRD,
35 .name = "mgbecrd",
36 .sid = TEGRA234_SID_MGBE_VF2,
37 .regs = {
38 .sid = {
39 .override = 0x2d0,
40 .security = 0x2d4,
41 },
42 },
43 }, {
44 .id = TEGRA234_MEMORY_CLIENT_MGBEDRD,
45 .name = "mgbedrd",
46 .sid = TEGRA234_SID_MGBE_VF3,
47 .regs = {
48 .sid = {
49 .override = 0x2d8,
50 .security = 0x2dc,
51 },
52 },
53 }, {
54 .id = TEGRA234_MEMORY_CLIENT_MGBEAWR,
55 .name = "mgbeawr",
56 .sid = TEGRA234_SID_MGBE,
57 .regs = {
58 .sid = {
59 .override = 0x2e0,
60 .security = 0x2e4,
61 },
62 },
63 }, {
64 .id = TEGRA234_MEMORY_CLIENT_MGBEBWR,
65 .name = "mgbebwr",
66 .sid = TEGRA234_SID_MGBE_VF1,
67 .regs = {
68 .sid = {
69 .override = 0x2f8,
70 .security = 0x2fc,
71 },
72 },
73 }, {
74 .id = TEGRA234_MEMORY_CLIENT_MGBECWR,
75 .name = "mgbecwr",
76 .sid = TEGRA234_SID_MGBE_VF2,
77 .regs = {
78 .sid = {
79 .override = 0x308,
80 .security = 0x30c,
81 },
82 },
83 }, {
84 .id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
85 .name = "sdmmcrab",
86 .sid = TEGRA234_SID_SDMMC4,
87 .regs = {
88 .sid = {
89 .override = 0x318,
90 .security = 0x31c,
91 },
92 },
93 }, {
94 .id = TEGRA234_MEMORY_CLIENT_MGBEDWR,
95 .name = "mgbedwr",
96 .sid = TEGRA234_SID_MGBE_VF3,
97 .regs = {
98 .sid = {
99 .override = 0x328,
100 .security = 0x32c,
101 },
102 },
103 }, {
104 .id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
105 .name = "sdmmcwab",
106 .sid = TEGRA234_SID_SDMMC4,
107 .regs = {
108 .sid = {
109 .override = 0x338,
110 .security = 0x33c,
111 },
112 },
113 }, {
114 .id = TEGRA234_MEMORY_CLIENT_BPMPR,
115 .name = "bpmpr",
116 .sid = TEGRA234_SID_BPMP,
117 .regs = {
118 .sid = {
119 .override = 0x498,
120 .security = 0x49c,
121 },
122 },
123 }, {
124 .id = TEGRA234_MEMORY_CLIENT_BPMPW,
125 .name = "bpmpw",
126 .sid = TEGRA234_SID_BPMP,
127 .regs = {
128 .sid = {
129 .override = 0x4a0,
130 .security = 0x4a4,
131 },
132 },
133 }, {
134 .id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,
135 .name = "bpmpdmar",
136 .sid = TEGRA234_SID_BPMP,
137 .regs = {
138 .sid = {
139 .override = 0x4a8,
140 .security = 0x4ac,
141 },
142 },
143 }, {
144 .id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,
145 .name = "bpmpdmaw",
146 .sid = TEGRA234_SID_BPMP,
147 .regs = {
148 .sid = {
149 .override = 0x4b0,
150 .security = 0x4b4,
151 },
152 },
153 }, {
154 .id = TEGRA234_MEMORY_CLIENT_APEDMAR,
155 .name = "apedmar",
156 .sid = TEGRA234_SID_APE,
157 .regs = {
158 .sid = {
159 .override = 0x4f8,
160 .security = 0x4fc,
161 },
162 },
163 }, {
164 .id = TEGRA234_MEMORY_CLIENT_APEDMAW,
165 .name = "apedmaw",
166 .sid = TEGRA234_SID_APE,
167 .regs = {
168 .sid = {
169 .override = 0x500,
170 .security = 0x504,
171 },
172 },
173 }, {
174 .id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
175 .name = "dla0rda",
176 .sid = TEGRA234_SID_NVDLA0,
177 .regs = {
178 .sid = {
179 .override = 0x5f0,
180 .security = 0x5f4,
181 },
182 },
183 }, {
184 .id = TEGRA234_MEMORY_CLIENT_DLA0FALRDB,
185 .name = "dla0falrdb",
186 .sid = TEGRA234_SID_NVDLA0,
187 .regs = {
188 .sid = {
189 .override = 0x5f8,
190 .security = 0x5fc,
191 },
192 },
193 }, {
194 .id = TEGRA234_MEMORY_CLIENT_DLA0WRA,
195 .name = "dla0wra",
196 .sid = TEGRA234_SID_NVDLA0,
197 .regs = {
198 .sid = {
199 .override = 0x600,
200 .security = 0x604,
201 },
202 },
203 }, {
204 .id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
205 .name = "dla0rdb",
206 .sid = TEGRA234_SID_NVDLA0,
207 .regs = {
208 .sid = {
209 .override = 0x160,
210 .security = 0x164,
211 },
212 },
213 }, {
214 .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
215 .name = "dla0rda1",
216 .sid = TEGRA234_SID_NVDLA0,
217 .regs = {
218 .sid = {
219 .override = 0x748,
220 .security = 0x74c,
221 },
222 },
223 }, {
224 .id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
225 .name = "dla0falwrb",
226 .sid = TEGRA234_SID_NVDLA0,
227 .regs = {
228 .sid = {
229 .override = 0x608,
230 .security = 0x60c,
231 },
232 },
233 }, {
234 .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
235 .name = "dla0rdb1",
236 .sid = TEGRA234_SID_NVDLA0,
237 .regs = {
238 .sid = {
239 .override = 0x168,
240 .security = 0x16c,
241 },
242 },
243 }, {
244 .id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
245 .name = "dla0wrb",
246 .sid = TEGRA234_SID_NVDLA0,
247 .regs = {
248 .sid = {
249 .override = 0x170,
250 .security = 0x174,
251 },
252 },
253 }, {
254 .id = TEGRA234_MEMORY_CLIENT_DLA1RDA,
255 .name = "dla0rda",
256 .sid = TEGRA234_SID_NVDLA1,
257 .regs = {
258 .sid = {
259 .override = 0x610,
260 .security = 0x614,
261 },
262 },
263 }, {
264 .id = TEGRA234_MEMORY_CLIENT_DLA1FALRDB,
265 .name = "dla0falrdb",
266 .sid = TEGRA234_SID_NVDLA1,
267 .regs = {
268 .sid = {
269 .override = 0x618,
270 .security = 0x61c,
271 },
272 },
273 }, {
274 .id = TEGRA234_MEMORY_CLIENT_DLA1WRA,
275 .name = "dla0wra",
276 .sid = TEGRA234_SID_NVDLA1,
277 .regs = {
278 .sid = {
279 .override = 0x620,
280 .security = 0x624,
281 },
282 },
283 }, {
284 .id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
285 .name = "dla0rdb",
286 .sid = TEGRA234_SID_NVDLA1,
287 .regs = {
288 .sid = {
289 .override = 0x178,
290 .security = 0x17c,
291 },
292 },
293 }, {
294 .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
295 .name = "dla0rda1",
296 .sid = TEGRA234_SID_NVDLA1,
297 .regs = {
298 .sid = {
299 .override = 0x750,
300 .security = 0x754,
301 },
302 },
303 }, {
304 .id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
305 .name = "dla0falwrb",
306 .sid = TEGRA234_SID_NVDLA1,
307 .regs = {
308 .sid = {
309 .override = 0x628,
310 .security = 0x62c,
311 },
312 },
313 }, {
314 .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
315 .name = "dla0rdb1",
316 .sid = TEGRA234_SID_NVDLA1,
317 .regs = {
318 .sid = {
319 .override = 0x370,
320 .security = 0x374,
321 },
322 },
323 }, {
324 .id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
325 .name = "dla0wrb",
326 .sid = TEGRA234_SID_NVDLA1,
327 .regs = {
328 .sid = {
329 .override = 0x378,
330 .security = 0x37c,
331 },
332 },
333 },
334};
335
336const struct tegra_mc_soc tegra234_mc_soc = {
337 .num_clients = ARRAY_SIZE(tegra234_mc_clients),
338 .clients = tegra234_mc_clients,
339 .num_address_bits = 40,
340 .num_channels = 16,
341 .client_id_mask = 0x1ff,
342 .intmask = MC_INT_DECERR_ROUTE_SANITY |
343 MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
344 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
345 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
346 .has_addr_hi_reg = true,
347 .ops = &tegra186_mc_ops,
348 .ch_intmask = 0x0000ff00,
349 .global_intstatus_channel_shift = 8,
350 /*
351 * Additionally, there are lite carveouts but those are not currently
352 * supported.
353 */
354 .num_carveouts = 32,
355};