Loading...
Note: File does not exist in v6.2.
1/*
2 * SGI UltraViolet TLB flush routines.
3 *
4 * (c) 2008-2014 Cliff Wickman <cpw@sgi.com>, SGI.
5 *
6 * This code is released under the GNU General Public License version 2 or
7 * later.
8 */
9#include <linux/seq_file.h>
10#include <linux/proc_fs.h>
11#include <linux/debugfs.h>
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/delay.h>
15
16#include <asm/mmu_context.h>
17#include <asm/uv/uv.h>
18#include <asm/uv/uv_mmrs.h>
19#include <asm/uv/uv_hub.h>
20#include <asm/uv/uv_bau.h>
21#include <asm/apic.h>
22#include <asm/tsc.h>
23#include <asm/irq_vectors.h>
24#include <asm/timer.h>
25
26static struct bau_operations ops __ro_after_init;
27
28/* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */
29static const int timeout_base_ns[] = {
30 20,
31 160,
32 1280,
33 10240,
34 81920,
35 655360,
36 5242880,
37 167772160
38};
39
40static int timeout_us;
41static bool nobau = true;
42static int nobau_perm;
43
44/* tunables: */
45static int max_concurr = MAX_BAU_CONCURRENT;
46static int max_concurr_const = MAX_BAU_CONCURRENT;
47static int plugged_delay = PLUGGED_DELAY;
48static int plugsb4reset = PLUGSB4RESET;
49static int giveup_limit = GIVEUP_LIMIT;
50static int timeoutsb4reset = TIMEOUTSB4RESET;
51static int ipi_reset_limit = IPI_RESET_LIMIT;
52static int complete_threshold = COMPLETE_THRESHOLD;
53static int congested_respns_us = CONGESTED_RESPONSE_US;
54static int congested_reps = CONGESTED_REPS;
55static int disabled_period = DISABLED_PERIOD;
56
57static struct tunables tunables[] = {
58 {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */
59 {&plugged_delay, PLUGGED_DELAY},
60 {&plugsb4reset, PLUGSB4RESET},
61 {&timeoutsb4reset, TIMEOUTSB4RESET},
62 {&ipi_reset_limit, IPI_RESET_LIMIT},
63 {&complete_threshold, COMPLETE_THRESHOLD},
64 {&congested_respns_us, CONGESTED_RESPONSE_US},
65 {&congested_reps, CONGESTED_REPS},
66 {&disabled_period, DISABLED_PERIOD},
67 {&giveup_limit, GIVEUP_LIMIT}
68};
69
70static struct dentry *tunables_dir;
71static struct dentry *tunables_file;
72
73/* these correspond to the statistics printed by ptc_seq_show() */
74static char *stat_description[] = {
75 "sent: number of shootdown messages sent",
76 "stime: time spent sending messages",
77 "numuvhubs: number of hubs targeted with shootdown",
78 "numuvhubs16: number times 16 or more hubs targeted",
79 "numuvhubs8: number times 8 or more hubs targeted",
80 "numuvhubs4: number times 4 or more hubs targeted",
81 "numuvhubs2: number times 2 or more hubs targeted",
82 "numuvhubs1: number times 1 hub targeted",
83 "numcpus: number of cpus targeted with shootdown",
84 "dto: number of destination timeouts",
85 "retries: destination timeout retries sent",
86 "rok: : destination timeouts successfully retried",
87 "resetp: ipi-style resource resets for plugs",
88 "resett: ipi-style resource resets for timeouts",
89 "giveup: fall-backs to ipi-style shootdowns",
90 "sto: number of source timeouts",
91 "bz: number of stay-busy's",
92 "throt: number times spun in throttle",
93 "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE",
94 "recv: shootdown messages received",
95 "rtime: time spent processing messages",
96 "all: shootdown all-tlb messages",
97 "one: shootdown one-tlb messages",
98 "mult: interrupts that found multiple messages",
99 "none: interrupts that found no messages",
100 "retry: number of retry messages processed",
101 "canc: number messages canceled by retries",
102 "nocan: number retries that found nothing to cancel",
103 "reset: number of ipi-style reset requests processed",
104 "rcan: number messages canceled by reset requests",
105 "disable: number times use of the BAU was disabled",
106 "enable: number times use of the BAU was re-enabled"
107};
108
109static int __init setup_bau(char *arg)
110{
111 int result;
112
113 if (!arg)
114 return -EINVAL;
115
116 result = strtobool(arg, &nobau);
117 if (result)
118 return result;
119
120 /* we need to flip the logic here, so that bau=y sets nobau to false */
121 nobau = !nobau;
122
123 if (!nobau)
124 pr_info("UV BAU Enabled\n");
125 else
126 pr_info("UV BAU Disabled\n");
127
128 return 0;
129}
130early_param("bau", setup_bau);
131
132/* base pnode in this partition */
133static int uv_base_pnode __read_mostly;
134
135static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
136static DEFINE_PER_CPU(struct bau_control, bau_control);
137static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask);
138
139static void
140set_bau_on(void)
141{
142 int cpu;
143 struct bau_control *bcp;
144
145 if (nobau_perm) {
146 pr_info("BAU not initialized; cannot be turned on\n");
147 return;
148 }
149 nobau = false;
150 for_each_present_cpu(cpu) {
151 bcp = &per_cpu(bau_control, cpu);
152 bcp->nobau = false;
153 }
154 pr_info("BAU turned on\n");
155 return;
156}
157
158static void
159set_bau_off(void)
160{
161 int cpu;
162 struct bau_control *bcp;
163
164 nobau = true;
165 for_each_present_cpu(cpu) {
166 bcp = &per_cpu(bau_control, cpu);
167 bcp->nobau = true;
168 }
169 pr_info("BAU turned off\n");
170 return;
171}
172
173/*
174 * Determine the first node on a uvhub. 'Nodes' are used for kernel
175 * memory allocation.
176 */
177static int __init uvhub_to_first_node(int uvhub)
178{
179 int node, b;
180
181 for_each_online_node(node) {
182 b = uv_node_to_blade_id(node);
183 if (uvhub == b)
184 return node;
185 }
186 return -1;
187}
188
189/*
190 * Determine the apicid of the first cpu on a uvhub.
191 */
192static int __init uvhub_to_first_apicid(int uvhub)
193{
194 int cpu;
195
196 for_each_present_cpu(cpu)
197 if (uvhub == uv_cpu_to_blade_id(cpu))
198 return per_cpu(x86_cpu_to_apicid, cpu);
199 return -1;
200}
201
202/*
203 * Free a software acknowledge hardware resource by clearing its Pending
204 * bit. This will return a reply to the sender.
205 * If the message has timed out, a reply has already been sent by the
206 * hardware but the resource has not been released. In that case our
207 * clear of the Timeout bit (as well) will free the resource. No reply will
208 * be sent (the hardware will only do one reply per message).
209 */
210static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp,
211 int do_acknowledge)
212{
213 unsigned long dw;
214 struct bau_pq_entry *msg;
215
216 msg = mdp->msg;
217 if (!msg->canceled && do_acknowledge) {
218 dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec;
219 ops.write_l_sw_ack(dw);
220 }
221 msg->replied_to = 1;
222 msg->swack_vec = 0;
223}
224
225/*
226 * Process the receipt of a RETRY message
227 */
228static void bau_process_retry_msg(struct msg_desc *mdp,
229 struct bau_control *bcp)
230{
231 int i;
232 int cancel_count = 0;
233 unsigned long msg_res;
234 unsigned long mmr = 0;
235 struct bau_pq_entry *msg = mdp->msg;
236 struct bau_pq_entry *msg2;
237 struct ptc_stats *stat = bcp->statp;
238
239 stat->d_retries++;
240 /*
241 * cancel any message from msg+1 to the retry itself
242 */
243 for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) {
244 if (msg2 > mdp->queue_last)
245 msg2 = mdp->queue_first;
246 if (msg2 == msg)
247 break;
248
249 /* same conditions for cancellation as do_reset */
250 if ((msg2->replied_to == 0) && (msg2->canceled == 0) &&
251 (msg2->swack_vec) && ((msg2->swack_vec &
252 msg->swack_vec) == 0) &&
253 (msg2->sending_cpu == msg->sending_cpu) &&
254 (msg2->msg_type != MSG_NOOP)) {
255 mmr = ops.read_l_sw_ack();
256 msg_res = msg2->swack_vec;
257 /*
258 * This is a message retry; clear the resources held
259 * by the previous message only if they timed out.
260 * If it has not timed out we have an unexpected
261 * situation to report.
262 */
263 if (mmr & (msg_res << UV_SW_ACK_NPENDING)) {
264 unsigned long mr;
265 /*
266 * Is the resource timed out?
267 * Make everyone ignore the cancelled message.
268 */
269 msg2->canceled = 1;
270 stat->d_canceled++;
271 cancel_count++;
272 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
273 ops.write_l_sw_ack(mr);
274 }
275 }
276 }
277 if (!cancel_count)
278 stat->d_nocanceled++;
279}
280
281/*
282 * Do all the things a cpu should do for a TLB shootdown message.
283 * Other cpu's may come here at the same time for this message.
284 */
285static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
286 int do_acknowledge)
287{
288 short socket_ack_count = 0;
289 short *sp;
290 struct atomic_short *asp;
291 struct ptc_stats *stat = bcp->statp;
292 struct bau_pq_entry *msg = mdp->msg;
293 struct bau_control *smaster = bcp->socket_master;
294
295 /*
296 * This must be a normal message, or retry of a normal message
297 */
298 if (msg->address == TLB_FLUSH_ALL) {
299 local_flush_tlb();
300 stat->d_alltlb++;
301 } else {
302 __flush_tlb_one_user(msg->address);
303 stat->d_onetlb++;
304 }
305 stat->d_requestee++;
306
307 /*
308 * One cpu on each uvhub has the additional job on a RETRY
309 * of releasing the resource held by the message that is
310 * being retried. That message is identified by sending
311 * cpu number.
312 */
313 if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master)
314 bau_process_retry_msg(mdp, bcp);
315
316 /*
317 * This is a swack message, so we have to reply to it.
318 * Count each responding cpu on the socket. This avoids
319 * pinging the count's cache line back and forth between
320 * the sockets.
321 */
322 sp = &smaster->socket_acknowledge_count[mdp->msg_slot];
323 asp = (struct atomic_short *)sp;
324 socket_ack_count = atom_asr(1, asp);
325 if (socket_ack_count == bcp->cpus_in_socket) {
326 int msg_ack_count;
327 /*
328 * Both sockets dump their completed count total into
329 * the message's count.
330 */
331 *sp = 0;
332 asp = (struct atomic_short *)&msg->acknowledge_count;
333 msg_ack_count = atom_asr(socket_ack_count, asp);
334
335 if (msg_ack_count == bcp->cpus_in_uvhub) {
336 /*
337 * All cpus in uvhub saw it; reply
338 * (unless we are in the UV2 workaround)
339 */
340 reply_to_message(mdp, bcp, do_acknowledge);
341 }
342 }
343
344 return;
345}
346
347/*
348 * Determine the first cpu on a pnode.
349 */
350static int pnode_to_first_cpu(int pnode, struct bau_control *smaster)
351{
352 int cpu;
353 struct hub_and_pnode *hpp;
354
355 for_each_present_cpu(cpu) {
356 hpp = &smaster->thp[cpu];
357 if (pnode == hpp->pnode)
358 return cpu;
359 }
360 return -1;
361}
362
363/*
364 * Last resort when we get a large number of destination timeouts is
365 * to clear resources held by a given cpu.
366 * Do this with IPI so that all messages in the BAU message queue
367 * can be identified by their nonzero swack_vec field.
368 *
369 * This is entered for a single cpu on the uvhub.
370 * The sender want's this uvhub to free a specific message's
371 * swack resources.
372 */
373static void do_reset(void *ptr)
374{
375 int i;
376 struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id());
377 struct reset_args *rap = (struct reset_args *)ptr;
378 struct bau_pq_entry *msg;
379 struct ptc_stats *stat = bcp->statp;
380
381 stat->d_resets++;
382 /*
383 * We're looking for the given sender, and
384 * will free its swack resource.
385 * If all cpu's finally responded after the timeout, its
386 * message 'replied_to' was set.
387 */
388 for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
389 unsigned long msg_res;
390 /* do_reset: same conditions for cancellation as
391 bau_process_retry_msg() */
392 if ((msg->replied_to == 0) &&
393 (msg->canceled == 0) &&
394 (msg->sending_cpu == rap->sender) &&
395 (msg->swack_vec) &&
396 (msg->msg_type != MSG_NOOP)) {
397 unsigned long mmr;
398 unsigned long mr;
399 /*
400 * make everyone else ignore this message
401 */
402 msg->canceled = 1;
403 /*
404 * only reset the resource if it is still pending
405 */
406 mmr = ops.read_l_sw_ack();
407 msg_res = msg->swack_vec;
408 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
409 if (mmr & msg_res) {
410 stat->d_rcanceled++;
411 ops.write_l_sw_ack(mr);
412 }
413 }
414 }
415 return;
416}
417
418/*
419 * Use IPI to get all target uvhubs to release resources held by
420 * a given sending cpu number.
421 */
422static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp)
423{
424 int pnode;
425 int apnode;
426 int maskbits;
427 int sender = bcp->cpu;
428 cpumask_t *mask = bcp->uvhub_master->cpumask;
429 struct bau_control *smaster = bcp->socket_master;
430 struct reset_args reset_args;
431
432 reset_args.sender = sender;
433 cpumask_clear(mask);
434 /* find a single cpu for each uvhub in this distribution mask */
435 maskbits = sizeof(struct pnmask) * BITSPERBYTE;
436 /* each bit is a pnode relative to the partition base pnode */
437 for (pnode = 0; pnode < maskbits; pnode++) {
438 int cpu;
439 if (!bau_uvhub_isset(pnode, distribution))
440 continue;
441 apnode = pnode + bcp->partition_base_pnode;
442 cpu = pnode_to_first_cpu(apnode, smaster);
443 cpumask_set_cpu(cpu, mask);
444 }
445
446 /* IPI all cpus; preemption is already disabled */
447 smp_call_function_many(mask, do_reset, (void *)&reset_args, 1);
448 return;
449}
450
451/*
452 * Not to be confused with cycles_2_ns() from tsc.c; this gives a relative
453 * number, not an absolute. It converts a duration in cycles to a duration in
454 * ns.
455 */
456static inline unsigned long long cycles_2_ns(unsigned long long cyc)
457{
458 struct cyc2ns_data data;
459 unsigned long long ns;
460
461 cyc2ns_read_begin(&data);
462 ns = mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift);
463 cyc2ns_read_end();
464
465 return ns;
466}
467
468/*
469 * The reverse of the above; converts a duration in ns to a duration in cycles.
470 */
471static inline unsigned long long ns_2_cycles(unsigned long long ns)
472{
473 struct cyc2ns_data data;
474 unsigned long long cyc;
475
476 cyc2ns_read_begin(&data);
477 cyc = (ns << data.cyc2ns_shift) / data.cyc2ns_mul;
478 cyc2ns_read_end();
479
480 return cyc;
481}
482
483static inline unsigned long cycles_2_us(unsigned long long cyc)
484{
485 return cycles_2_ns(cyc) / NSEC_PER_USEC;
486}
487
488static inline cycles_t sec_2_cycles(unsigned long sec)
489{
490 return ns_2_cycles(sec * NSEC_PER_SEC);
491}
492
493static inline unsigned long long usec_2_cycles(unsigned long usec)
494{
495 return ns_2_cycles(usec * NSEC_PER_USEC);
496}
497
498/*
499 * wait for all cpus on this hub to finish their sends and go quiet
500 * leaves uvhub_quiesce set so that no new broadcasts are started by
501 * bau_flush_send_and_wait()
502 */
503static inline void quiesce_local_uvhub(struct bau_control *hmaster)
504{
505 atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce);
506}
507
508/*
509 * mark this quiet-requestor as done
510 */
511static inline void end_uvhub_quiesce(struct bau_control *hmaster)
512{
513 atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce);
514}
515
516static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift)
517{
518 unsigned long descriptor_status;
519
520 descriptor_status = uv_read_local_mmr(mmr_offset);
521 descriptor_status >>= right_shift;
522 descriptor_status &= UV_ACT_STATUS_MASK;
523 return descriptor_status;
524}
525
526/*
527 * Wait for completion of a broadcast software ack message
528 * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
529 */
530static int uv1_wait_completion(struct bau_desc *bau_desc,
531 struct bau_control *bcp, long try)
532{
533 unsigned long descriptor_status;
534 cycles_t ttm;
535 u64 mmr_offset = bcp->status_mmr;
536 int right_shift = bcp->status_index;
537 struct ptc_stats *stat = bcp->statp;
538
539 descriptor_status = uv1_read_status(mmr_offset, right_shift);
540 /* spin on the status MMR, waiting for it to go idle */
541 while ((descriptor_status != DS_IDLE)) {
542 /*
543 * Our software ack messages may be blocked because
544 * there are no swack resources available. As long
545 * as none of them has timed out hardware will NACK
546 * our message and its state will stay IDLE.
547 */
548 if (descriptor_status == DS_SOURCE_TIMEOUT) {
549 stat->s_stimeout++;
550 return FLUSH_GIVEUP;
551 } else if (descriptor_status == DS_DESTINATION_TIMEOUT) {
552 stat->s_dtimeout++;
553 ttm = get_cycles();
554
555 /*
556 * Our retries may be blocked by all destination
557 * swack resources being consumed, and a timeout
558 * pending. In that case hardware returns the
559 * ERROR that looks like a destination timeout.
560 */
561 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
562 bcp->conseccompletes = 0;
563 return FLUSH_RETRY_PLUGGED;
564 }
565
566 bcp->conseccompletes = 0;
567 return FLUSH_RETRY_TIMEOUT;
568 } else {
569 /*
570 * descriptor_status is still BUSY
571 */
572 cpu_relax();
573 }
574 descriptor_status = uv1_read_status(mmr_offset, right_shift);
575 }
576 bcp->conseccompletes++;
577 return FLUSH_COMPLETE;
578}
579
580/*
581 * UV2 could have an extra bit of status in the ACTIVATION_STATUS_2 register.
582 * But not currently used.
583 */
584static unsigned long uv2_3_read_status(unsigned long offset, int rshft, int desc)
585{
586 return ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK) << 1;
587}
588
589/*
590 * Entered when a bau descriptor has gone into a permanent busy wait because
591 * of a hardware bug.
592 * Workaround the bug.
593 */
594static int handle_uv2_busy(struct bau_control *bcp)
595{
596 struct ptc_stats *stat = bcp->statp;
597
598 stat->s_uv2_wars++;
599 bcp->busy = 1;
600 return FLUSH_GIVEUP;
601}
602
603static int uv2_3_wait_completion(struct bau_desc *bau_desc,
604 struct bau_control *bcp, long try)
605{
606 unsigned long descriptor_stat;
607 cycles_t ttm;
608 u64 mmr_offset = bcp->status_mmr;
609 int right_shift = bcp->status_index;
610 int desc = bcp->uvhub_cpu;
611 long busy_reps = 0;
612 struct ptc_stats *stat = bcp->statp;
613
614 descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
615
616 /* spin on the status MMR, waiting for it to go idle */
617 while (descriptor_stat != UV2H_DESC_IDLE) {
618 if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT)) {
619 /*
620 * A h/w bug on the destination side may
621 * have prevented the message being marked
622 * pending, thus it doesn't get replied to
623 * and gets continually nacked until it times
624 * out with a SOURCE_TIMEOUT.
625 */
626 stat->s_stimeout++;
627 return FLUSH_GIVEUP;
628 } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) {
629 ttm = get_cycles();
630
631 /*
632 * Our retries may be blocked by all destination
633 * swack resources being consumed, and a timeout
634 * pending. In that case hardware returns the
635 * ERROR that looks like a destination timeout.
636 * Without using the extended status we have to
637 * deduce from the short time that this was a
638 * strong nack.
639 */
640 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
641 bcp->conseccompletes = 0;
642 stat->s_plugged++;
643 /* FLUSH_RETRY_PLUGGED causes hang on boot */
644 return FLUSH_GIVEUP;
645 }
646 stat->s_dtimeout++;
647 bcp->conseccompletes = 0;
648 /* FLUSH_RETRY_TIMEOUT causes hang on boot */
649 return FLUSH_GIVEUP;
650 } else {
651 busy_reps++;
652 if (busy_reps > 1000000) {
653 /* not to hammer on the clock */
654 busy_reps = 0;
655 ttm = get_cycles();
656 if ((ttm - bcp->send_message) > bcp->timeout_interval)
657 return handle_uv2_busy(bcp);
658 }
659 /*
660 * descriptor_stat is still BUSY
661 */
662 cpu_relax();
663 }
664 descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
665 }
666 bcp->conseccompletes++;
667 return FLUSH_COMPLETE;
668}
669
670/*
671 * Returns the status of current BAU message for cpu desc as a bit field
672 * [Error][Busy][Aux]
673 */
674static u64 read_status(u64 status_mmr, int index, int desc)
675{
676 u64 stat;
677
678 stat = ((read_lmmr(status_mmr) >> index) & UV_ACT_STATUS_MASK) << 1;
679 stat |= (read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_2) >> desc) & 0x1;
680
681 return stat;
682}
683
684static int uv4_wait_completion(struct bau_desc *bau_desc,
685 struct bau_control *bcp, long try)
686{
687 struct ptc_stats *stat = bcp->statp;
688 u64 descriptor_stat;
689 u64 mmr = bcp->status_mmr;
690 int index = bcp->status_index;
691 int desc = bcp->uvhub_cpu;
692
693 descriptor_stat = read_status(mmr, index, desc);
694
695 /* spin on the status MMR, waiting for it to go idle */
696 while (descriptor_stat != UV2H_DESC_IDLE) {
697 switch (descriptor_stat) {
698 case UV2H_DESC_SOURCE_TIMEOUT:
699 stat->s_stimeout++;
700 return FLUSH_GIVEUP;
701
702 case UV2H_DESC_DEST_TIMEOUT:
703 stat->s_dtimeout++;
704 bcp->conseccompletes = 0;
705 return FLUSH_RETRY_TIMEOUT;
706
707 case UV2H_DESC_DEST_STRONG_NACK:
708 stat->s_plugged++;
709 bcp->conseccompletes = 0;
710 return FLUSH_RETRY_PLUGGED;
711
712 case UV2H_DESC_DEST_PUT_ERR:
713 bcp->conseccompletes = 0;
714 return FLUSH_GIVEUP;
715
716 default:
717 /* descriptor_stat is still BUSY */
718 cpu_relax();
719 }
720 descriptor_stat = read_status(mmr, index, desc);
721 }
722 bcp->conseccompletes++;
723 return FLUSH_COMPLETE;
724}
725
726/*
727 * Our retries are blocked by all destination sw ack resources being
728 * in use, and a timeout is pending. In that case hardware immediately
729 * returns the ERROR that looks like a destination timeout.
730 */
731static void destination_plugged(struct bau_desc *bau_desc,
732 struct bau_control *bcp,
733 struct bau_control *hmaster, struct ptc_stats *stat)
734{
735 udelay(bcp->plugged_delay);
736 bcp->plugged_tries++;
737
738 if (bcp->plugged_tries >= bcp->plugsb4reset) {
739 bcp->plugged_tries = 0;
740
741 quiesce_local_uvhub(hmaster);
742
743 spin_lock(&hmaster->queue_lock);
744 reset_with_ipi(&bau_desc->distribution, bcp);
745 spin_unlock(&hmaster->queue_lock);
746
747 end_uvhub_quiesce(hmaster);
748
749 bcp->ipi_attempts++;
750 stat->s_resets_plug++;
751 }
752}
753
754static void destination_timeout(struct bau_desc *bau_desc,
755 struct bau_control *bcp, struct bau_control *hmaster,
756 struct ptc_stats *stat)
757{
758 hmaster->max_concurr = 1;
759 bcp->timeout_tries++;
760 if (bcp->timeout_tries >= bcp->timeoutsb4reset) {
761 bcp->timeout_tries = 0;
762
763 quiesce_local_uvhub(hmaster);
764
765 spin_lock(&hmaster->queue_lock);
766 reset_with_ipi(&bau_desc->distribution, bcp);
767 spin_unlock(&hmaster->queue_lock);
768
769 end_uvhub_quiesce(hmaster);
770
771 bcp->ipi_attempts++;
772 stat->s_resets_timeout++;
773 }
774}
775
776/*
777 * Stop all cpus on a uvhub from using the BAU for a period of time.
778 * This is reversed by check_enable.
779 */
780static void disable_for_period(struct bau_control *bcp, struct ptc_stats *stat)
781{
782 int tcpu;
783 struct bau_control *tbcp;
784 struct bau_control *hmaster;
785 cycles_t tm1;
786
787 hmaster = bcp->uvhub_master;
788 spin_lock(&hmaster->disable_lock);
789 if (!bcp->baudisabled) {
790 stat->s_bau_disabled++;
791 tm1 = get_cycles();
792 for_each_present_cpu(tcpu) {
793 tbcp = &per_cpu(bau_control, tcpu);
794 if (tbcp->uvhub_master == hmaster) {
795 tbcp->baudisabled = 1;
796 tbcp->set_bau_on_time =
797 tm1 + bcp->disabled_period;
798 }
799 }
800 }
801 spin_unlock(&hmaster->disable_lock);
802}
803
804static void count_max_concurr(int stat, struct bau_control *bcp,
805 struct bau_control *hmaster)
806{
807 bcp->plugged_tries = 0;
808 bcp->timeout_tries = 0;
809 if (stat != FLUSH_COMPLETE)
810 return;
811 if (bcp->conseccompletes <= bcp->complete_threshold)
812 return;
813 if (hmaster->max_concurr >= hmaster->max_concurr_const)
814 return;
815 hmaster->max_concurr++;
816}
817
818static void record_send_stats(cycles_t time1, cycles_t time2,
819 struct bau_control *bcp, struct ptc_stats *stat,
820 int completion_status, int try)
821{
822 cycles_t elapsed;
823
824 if (time2 > time1) {
825 elapsed = time2 - time1;
826 stat->s_time += elapsed;
827
828 if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
829 bcp->period_requests++;
830 bcp->period_time += elapsed;
831 if ((elapsed > usec_2_cycles(bcp->cong_response_us)) &&
832 (bcp->period_requests > bcp->cong_reps) &&
833 ((bcp->period_time / bcp->period_requests) >
834 usec_2_cycles(bcp->cong_response_us))) {
835 stat->s_congested++;
836 disable_for_period(bcp, stat);
837 }
838 }
839 } else
840 stat->s_requestor--;
841
842 if (completion_status == FLUSH_COMPLETE && try > 1)
843 stat->s_retriesok++;
844 else if (completion_status == FLUSH_GIVEUP) {
845 stat->s_giveup++;
846 if (get_cycles() > bcp->period_end)
847 bcp->period_giveups = 0;
848 bcp->period_giveups++;
849 if (bcp->period_giveups == 1)
850 bcp->period_end = get_cycles() + bcp->disabled_period;
851 if (bcp->period_giveups > bcp->giveup_limit) {
852 disable_for_period(bcp, stat);
853 stat->s_giveuplimit++;
854 }
855 }
856}
857
858/*
859 * Because of a uv1 hardware bug only a limited number of concurrent
860 * requests can be made.
861 */
862static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat)
863{
864 spinlock_t *lock = &hmaster->uvhub_lock;
865 atomic_t *v;
866
867 v = &hmaster->active_descriptor_count;
868 if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) {
869 stat->s_throttles++;
870 do {
871 cpu_relax();
872 } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr));
873 }
874}
875
876/*
877 * Handle the completion status of a message send.
878 */
879static void handle_cmplt(int completion_status, struct bau_desc *bau_desc,
880 struct bau_control *bcp, struct bau_control *hmaster,
881 struct ptc_stats *stat)
882{
883 if (completion_status == FLUSH_RETRY_PLUGGED)
884 destination_plugged(bau_desc, bcp, hmaster, stat);
885 else if (completion_status == FLUSH_RETRY_TIMEOUT)
886 destination_timeout(bau_desc, bcp, hmaster, stat);
887}
888
889/*
890 * Send a broadcast and wait for it to complete.
891 *
892 * The flush_mask contains the cpus the broadcast is to be sent to including
893 * cpus that are on the local uvhub.
894 *
895 * Returns 0 if all flushing represented in the mask was done.
896 * Returns 1 if it gives up entirely and the original cpu mask is to be
897 * returned to the kernel.
898 */
899static int uv_flush_send_and_wait(struct cpumask *flush_mask,
900 struct bau_control *bcp,
901 struct bau_desc *bau_desc)
902{
903 int seq_number = 0;
904 int completion_stat = 0;
905 int uv1 = 0;
906 long try = 0;
907 unsigned long index;
908 cycles_t time1;
909 cycles_t time2;
910 struct ptc_stats *stat = bcp->statp;
911 struct bau_control *hmaster = bcp->uvhub_master;
912 struct uv1_bau_msg_header *uv1_hdr = NULL;
913 struct uv2_3_bau_msg_header *uv2_3_hdr = NULL;
914
915 if (bcp->uvhub_version == UV_BAU_V1) {
916 uv1 = 1;
917 uv1_throttle(hmaster, stat);
918 }
919
920 while (hmaster->uvhub_quiesce)
921 cpu_relax();
922
923 time1 = get_cycles();
924 if (uv1)
925 uv1_hdr = &bau_desc->header.uv1_hdr;
926 else
927 /* uv2 and uv3 */
928 uv2_3_hdr = &bau_desc->header.uv2_3_hdr;
929
930 do {
931 if (try == 0) {
932 if (uv1)
933 uv1_hdr->msg_type = MSG_REGULAR;
934 else
935 uv2_3_hdr->msg_type = MSG_REGULAR;
936 seq_number = bcp->message_number++;
937 } else {
938 if (uv1)
939 uv1_hdr->msg_type = MSG_RETRY;
940 else
941 uv2_3_hdr->msg_type = MSG_RETRY;
942 stat->s_retry_messages++;
943 }
944
945 if (uv1)
946 uv1_hdr->sequence = seq_number;
947 else
948 uv2_3_hdr->sequence = seq_number;
949 index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu;
950 bcp->send_message = get_cycles();
951
952 write_mmr_activation(index);
953
954 try++;
955 completion_stat = ops.wait_completion(bau_desc, bcp, try);
956
957 handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
958
959 if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
960 bcp->ipi_attempts = 0;
961 stat->s_overipilimit++;
962 completion_stat = FLUSH_GIVEUP;
963 break;
964 }
965 cpu_relax();
966 } while ((completion_stat == FLUSH_RETRY_PLUGGED) ||
967 (completion_stat == FLUSH_RETRY_TIMEOUT));
968
969 time2 = get_cycles();
970
971 count_max_concurr(completion_stat, bcp, hmaster);
972
973 while (hmaster->uvhub_quiesce)
974 cpu_relax();
975
976 atomic_dec(&hmaster->active_descriptor_count);
977
978 record_send_stats(time1, time2, bcp, stat, completion_stat, try);
979
980 if (completion_stat == FLUSH_GIVEUP)
981 /* FLUSH_GIVEUP will fall back to using IPI's for tlb flush */
982 return 1;
983 return 0;
984}
985
986/*
987 * The BAU is disabled for this uvhub. When the disabled time period has
988 * expired re-enable it.
989 * Return 0 if it is re-enabled for all cpus on this uvhub.
990 */
991static int check_enable(struct bau_control *bcp, struct ptc_stats *stat)
992{
993 int tcpu;
994 struct bau_control *tbcp;
995 struct bau_control *hmaster;
996
997 hmaster = bcp->uvhub_master;
998 spin_lock(&hmaster->disable_lock);
999 if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) {
1000 stat->s_bau_reenabled++;
1001 for_each_present_cpu(tcpu) {
1002 tbcp = &per_cpu(bau_control, tcpu);
1003 if (tbcp->uvhub_master == hmaster) {
1004 tbcp->baudisabled = 0;
1005 tbcp->period_requests = 0;
1006 tbcp->period_time = 0;
1007 tbcp->period_giveups = 0;
1008 }
1009 }
1010 spin_unlock(&hmaster->disable_lock);
1011 return 0;
1012 }
1013 spin_unlock(&hmaster->disable_lock);
1014 return -1;
1015}
1016
1017static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs,
1018 int remotes, struct bau_desc *bau_desc)
1019{
1020 stat->s_requestor++;
1021 stat->s_ntargcpu += remotes + locals;
1022 stat->s_ntargremotes += remotes;
1023 stat->s_ntarglocals += locals;
1024
1025 /* uvhub statistics */
1026 hubs = bau_uvhub_weight(&bau_desc->distribution);
1027 if (locals) {
1028 stat->s_ntarglocaluvhub++;
1029 stat->s_ntargremoteuvhub += (hubs - 1);
1030 } else
1031 stat->s_ntargremoteuvhub += hubs;
1032
1033 stat->s_ntarguvhub += hubs;
1034
1035 if (hubs >= 16)
1036 stat->s_ntarguvhub16++;
1037 else if (hubs >= 8)
1038 stat->s_ntarguvhub8++;
1039 else if (hubs >= 4)
1040 stat->s_ntarguvhub4++;
1041 else if (hubs >= 2)
1042 stat->s_ntarguvhub2++;
1043 else
1044 stat->s_ntarguvhub1++;
1045}
1046
1047/*
1048 * Translate a cpu mask to the uvhub distribution mask in the BAU
1049 * activation descriptor.
1050 */
1051static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
1052 struct bau_desc *bau_desc, int *localsp, int *remotesp)
1053{
1054 int cpu;
1055 int pnode;
1056 int cnt = 0;
1057 struct hub_and_pnode *hpp;
1058
1059 for_each_cpu(cpu, flush_mask) {
1060 /*
1061 * The distribution vector is a bit map of pnodes, relative
1062 * to the partition base pnode (and the partition base nasid
1063 * in the header).
1064 * Translate cpu to pnode and hub using a local memory array.
1065 */
1066 hpp = &bcp->socket_master->thp[cpu];
1067 pnode = hpp->pnode - bcp->partition_base_pnode;
1068 bau_uvhub_set(pnode, &bau_desc->distribution);
1069 cnt++;
1070 if (hpp->uvhub == bcp->uvhub)
1071 (*localsp)++;
1072 else
1073 (*remotesp)++;
1074 }
1075 if (!cnt)
1076 return 1;
1077 return 0;
1078}
1079
1080/*
1081 * globally purge translation cache of a virtual address or all TLB's
1082 * @cpumask: mask of all cpu's in which the address is to be removed
1083 * @mm: mm_struct containing virtual address range
1084 * @start: start virtual address to be removed from TLB
1085 * @end: end virtual address to be remove from TLB
1086 * @cpu: the current cpu
1087 *
1088 * This is the entry point for initiating any UV global TLB shootdown.
1089 *
1090 * Purges the translation caches of all specified processors of the given
1091 * virtual address, or purges all TLB's on specified processors.
1092 *
1093 * The caller has derived the cpumask from the mm_struct. This function
1094 * is called only if there are bits set in the mask. (e.g. flush_tlb_page())
1095 *
1096 * The cpumask is converted into a uvhubmask of the uvhubs containing
1097 * those cpus.
1098 *
1099 * Note that this function should be called with preemption disabled.
1100 *
1101 * Returns NULL if all remote flushing was done.
1102 * Returns pointer to cpumask if some remote flushing remains to be
1103 * done. The returned pointer is valid till preemption is re-enabled.
1104 */
1105const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
1106 const struct flush_tlb_info *info)
1107{
1108 unsigned int cpu = smp_processor_id();
1109 int locals = 0, remotes = 0, hubs = 0;
1110 struct bau_desc *bau_desc;
1111 struct cpumask *flush_mask;
1112 struct ptc_stats *stat;
1113 struct bau_control *bcp;
1114 unsigned long descriptor_status, status, address;
1115
1116 bcp = &per_cpu(bau_control, cpu);
1117
1118 if (bcp->nobau)
1119 return cpumask;
1120
1121 stat = bcp->statp;
1122 stat->s_enters++;
1123
1124 if (bcp->busy) {
1125 descriptor_status =
1126 read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_0);
1127 status = ((descriptor_status >> (bcp->uvhub_cpu *
1128 UV_ACT_STATUS_SIZE)) & UV_ACT_STATUS_MASK) << 1;
1129 if (status == UV2H_DESC_BUSY)
1130 return cpumask;
1131 bcp->busy = 0;
1132 }
1133
1134 /* bau was disabled due to slow response */
1135 if (bcp->baudisabled) {
1136 if (check_enable(bcp, stat)) {
1137 stat->s_ipifordisabled++;
1138 return cpumask;
1139 }
1140 }
1141
1142 /*
1143 * Each sending cpu has a per-cpu mask which it fills from the caller's
1144 * cpu mask. All cpus are converted to uvhubs and copied to the
1145 * activation descriptor.
1146 */
1147 flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu);
1148 /* don't actually do a shootdown of the local cpu */
1149 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
1150
1151 if (cpumask_test_cpu(cpu, cpumask))
1152 stat->s_ntargself++;
1153
1154 bau_desc = bcp->descriptor_base;
1155 bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu);
1156 bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
1157 if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes))
1158 return NULL;
1159
1160 record_send_statistics(stat, locals, hubs, remotes, bau_desc);
1161
1162 if (!info->end || (info->end - info->start) <= PAGE_SIZE)
1163 address = info->start;
1164 else
1165 address = TLB_FLUSH_ALL;
1166
1167 switch (bcp->uvhub_version) {
1168 case UV_BAU_V1:
1169 case UV_BAU_V2:
1170 case UV_BAU_V3:
1171 bau_desc->payload.uv1_2_3.address = address;
1172 bau_desc->payload.uv1_2_3.sending_cpu = cpu;
1173 break;
1174 case UV_BAU_V4:
1175 bau_desc->payload.uv4.address = address;
1176 bau_desc->payload.uv4.sending_cpu = cpu;
1177 bau_desc->payload.uv4.qualifier = BAU_DESC_QUALIFIER;
1178 break;
1179 }
1180
1181 /*
1182 * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
1183 * or 1 if it gave up and the original cpumask should be returned.
1184 */
1185 if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc))
1186 return NULL;
1187 else
1188 return cpumask;
1189}
1190
1191/*
1192 * Search the message queue for any 'other' unprocessed message with the
1193 * same software acknowledge resource bit vector as the 'msg' message.
1194 */
1195static struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg,
1196 struct bau_control *bcp)
1197{
1198 struct bau_pq_entry *msg_next = msg + 1;
1199 unsigned char swack_vec = msg->swack_vec;
1200
1201 if (msg_next > bcp->queue_last)
1202 msg_next = bcp->queue_first;
1203 while (msg_next != msg) {
1204 if ((msg_next->canceled == 0) && (msg_next->replied_to == 0) &&
1205 (msg_next->swack_vec == swack_vec))
1206 return msg_next;
1207 msg_next++;
1208 if (msg_next > bcp->queue_last)
1209 msg_next = bcp->queue_first;
1210 }
1211 return NULL;
1212}
1213
1214/*
1215 * UV2 needs to work around a bug in which an arriving message has not
1216 * set a bit in the UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE register.
1217 * Such a message must be ignored.
1218 */
1219static void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp)
1220{
1221 unsigned long mmr_image;
1222 unsigned char swack_vec;
1223 struct bau_pq_entry *msg = mdp->msg;
1224 struct bau_pq_entry *other_msg;
1225
1226 mmr_image = ops.read_l_sw_ack();
1227 swack_vec = msg->swack_vec;
1228
1229 if ((swack_vec & mmr_image) == 0) {
1230 /*
1231 * This message was assigned a swack resource, but no
1232 * reserved acknowlegment is pending.
1233 * The bug has prevented this message from setting the MMR.
1234 */
1235 /*
1236 * Some message has set the MMR 'pending' bit; it might have
1237 * been another message. Look for that message.
1238 */
1239 other_msg = find_another_by_swack(msg, bcp);
1240 if (other_msg) {
1241 /*
1242 * There is another. Process this one but do not
1243 * ack it.
1244 */
1245 bau_process_message(mdp, bcp, 0);
1246 /*
1247 * Let the natural processing of that other message
1248 * acknowledge it. Don't get the processing of sw_ack's
1249 * out of order.
1250 */
1251 return;
1252 }
1253 }
1254
1255 /*
1256 * Either the MMR shows this one pending a reply or there is no
1257 * other message using this sw_ack, so it is safe to acknowledge it.
1258 */
1259 bau_process_message(mdp, bcp, 1);
1260
1261 return;
1262}
1263
1264/*
1265 * The BAU message interrupt comes here. (registered by set_intr_gate)
1266 * See entry_64.S
1267 *
1268 * We received a broadcast assist message.
1269 *
1270 * Interrupts are disabled; this interrupt could represent
1271 * the receipt of several messages.
1272 *
1273 * All cores/threads on this hub get this interrupt.
1274 * The last one to see it does the software ack.
1275 * (the resource will not be freed until noninterruptable cpus see this
1276 * interrupt; hardware may timeout the s/w ack and reply ERROR)
1277 */
1278void uv_bau_message_interrupt(struct pt_regs *regs)
1279{
1280 int count = 0;
1281 cycles_t time_start;
1282 struct bau_pq_entry *msg;
1283 struct bau_control *bcp;
1284 struct ptc_stats *stat;
1285 struct msg_desc msgdesc;
1286
1287 ack_APIC_irq();
1288 time_start = get_cycles();
1289
1290 bcp = &per_cpu(bau_control, smp_processor_id());
1291 stat = bcp->statp;
1292
1293 msgdesc.queue_first = bcp->queue_first;
1294 msgdesc.queue_last = bcp->queue_last;
1295
1296 msg = bcp->bau_msg_head;
1297 while (msg->swack_vec) {
1298 count++;
1299
1300 msgdesc.msg_slot = msg - msgdesc.queue_first;
1301 msgdesc.msg = msg;
1302 if (bcp->uvhub_version == UV_BAU_V2)
1303 process_uv2_message(&msgdesc, bcp);
1304 else
1305 /* no error workaround for uv1 or uv3 */
1306 bau_process_message(&msgdesc, bcp, 1);
1307
1308 msg++;
1309 if (msg > msgdesc.queue_last)
1310 msg = msgdesc.queue_first;
1311 bcp->bau_msg_head = msg;
1312 }
1313 stat->d_time += (get_cycles() - time_start);
1314 if (!count)
1315 stat->d_nomsg++;
1316 else if (count > 1)
1317 stat->d_multmsg++;
1318}
1319
1320/*
1321 * Each target uvhub (i.e. a uvhub that has cpu's) needs to have
1322 * shootdown message timeouts enabled. The timeout does not cause
1323 * an interrupt, but causes an error message to be returned to
1324 * the sender.
1325 */
1326static void __init enable_timeouts(void)
1327{
1328 int uvhub;
1329 int nuvhubs;
1330 int pnode;
1331 unsigned long mmr_image;
1332
1333 nuvhubs = uv_num_possible_blades();
1334
1335 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
1336 if (!uv_blade_nr_possible_cpus(uvhub))
1337 continue;
1338
1339 pnode = uv_blade_to_pnode(uvhub);
1340 mmr_image = read_mmr_misc_control(pnode);
1341 /*
1342 * Set the timeout period and then lock it in, in three
1343 * steps; captures and locks in the period.
1344 *
1345 * To program the period, the SOFT_ACK_MODE must be off.
1346 */
1347 mmr_image &= ~(1L << SOFTACK_MSHIFT);
1348 write_mmr_misc_control(pnode, mmr_image);
1349 /*
1350 * Set the 4-bit period.
1351 */
1352 mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT);
1353 mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT);
1354 write_mmr_misc_control(pnode, mmr_image);
1355 /*
1356 * UV1:
1357 * Subsequent reversals of the timebase bit (3) cause an
1358 * immediate timeout of one or all INTD resources as
1359 * indicated in bits 2:0 (7 causes all of them to timeout).
1360 */
1361 mmr_image |= (1L << SOFTACK_MSHIFT);
1362 if (is_uv2_hub()) {
1363 /* do not touch the legacy mode bit */
1364 /* hw bug workaround; do not use extended status */
1365 mmr_image &= ~(1L << UV2_EXT_SHFT);
1366 } else if (is_uv3_hub()) {
1367 mmr_image &= ~(1L << PREFETCH_HINT_SHFT);
1368 mmr_image |= (1L << SB_STATUS_SHFT);
1369 }
1370 write_mmr_misc_control(pnode, mmr_image);
1371 }
1372}
1373
1374static void *ptc_seq_start(struct seq_file *file, loff_t *offset)
1375{
1376 if (*offset < num_possible_cpus())
1377 return offset;
1378 return NULL;
1379}
1380
1381static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
1382{
1383 (*offset)++;
1384 if (*offset < num_possible_cpus())
1385 return offset;
1386 return NULL;
1387}
1388
1389static void ptc_seq_stop(struct seq_file *file, void *data)
1390{
1391}
1392
1393/*
1394 * Display the statistics thru /proc/sgi_uv/ptc_statistics
1395 * 'data' points to the cpu number
1396 * Note: see the descriptions in stat_description[].
1397 */
1398static int ptc_seq_show(struct seq_file *file, void *data)
1399{
1400 struct ptc_stats *stat;
1401 struct bau_control *bcp;
1402 int cpu;
1403
1404 cpu = *(loff_t *)data;
1405 if (!cpu) {
1406 seq_puts(file,
1407 "# cpu bauoff sent stime self locals remotes ncpus localhub ");
1408 seq_puts(file, "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
1409 seq_puts(file,
1410 "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries ");
1411 seq_puts(file,
1412 "rok resetp resett giveup sto bz throt disable ");
1413 seq_puts(file,
1414 "enable wars warshw warwaits enters ipidis plugged ");
1415 seq_puts(file,
1416 "ipiover glim cong swack recv rtime all one mult ");
1417 seq_puts(file, "none retry canc nocan reset rcan\n");
1418 }
1419 if (cpu < num_possible_cpus() && cpu_online(cpu)) {
1420 bcp = &per_cpu(bau_control, cpu);
1421 if (bcp->nobau) {
1422 seq_printf(file, "cpu %d bau disabled\n", cpu);
1423 return 0;
1424 }
1425 stat = bcp->statp;
1426 /* source side statistics */
1427 seq_printf(file,
1428 "cpu %d %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
1429 cpu, bcp->nobau, stat->s_requestor,
1430 cycles_2_us(stat->s_time),
1431 stat->s_ntargself, stat->s_ntarglocals,
1432 stat->s_ntargremotes, stat->s_ntargcpu,
1433 stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub,
1434 stat->s_ntarguvhub, stat->s_ntarguvhub16);
1435 seq_printf(file, "%ld %ld %ld %ld %ld %ld ",
1436 stat->s_ntarguvhub8, stat->s_ntarguvhub4,
1437 stat->s_ntarguvhub2, stat->s_ntarguvhub1,
1438 stat->s_dtimeout, stat->s_strongnacks);
1439 seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ",
1440 stat->s_retry_messages, stat->s_retriesok,
1441 stat->s_resets_plug, stat->s_resets_timeout,
1442 stat->s_giveup, stat->s_stimeout,
1443 stat->s_busy, stat->s_throttles);
1444 seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
1445 stat->s_bau_disabled, stat->s_bau_reenabled,
1446 stat->s_uv2_wars, stat->s_uv2_wars_hw,
1447 stat->s_uv2_war_waits, stat->s_enters,
1448 stat->s_ipifordisabled, stat->s_plugged,
1449 stat->s_overipilimit, stat->s_giveuplimit,
1450 stat->s_congested);
1451
1452 /* destination side statistics */
1453 seq_printf(file,
1454 "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n",
1455 ops.read_g_sw_ack(uv_cpu_to_pnode(cpu)),
1456 stat->d_requestee, cycles_2_us(stat->d_time),
1457 stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
1458 stat->d_nomsg, stat->d_retries, stat->d_canceled,
1459 stat->d_nocanceled, stat->d_resets,
1460 stat->d_rcanceled);
1461 }
1462 return 0;
1463}
1464
1465/*
1466 * Display the tunables thru debugfs
1467 */
1468static ssize_t tunables_read(struct file *file, char __user *userbuf,
1469 size_t count, loff_t *ppos)
1470{
1471 char *buf;
1472 int ret;
1473
1474 buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d %d\n",
1475 "max_concur plugged_delay plugsb4reset timeoutsb4reset",
1476 "ipi_reset_limit complete_threshold congested_response_us",
1477 "congested_reps disabled_period giveup_limit",
1478 max_concurr, plugged_delay, plugsb4reset,
1479 timeoutsb4reset, ipi_reset_limit, complete_threshold,
1480 congested_respns_us, congested_reps, disabled_period,
1481 giveup_limit);
1482
1483 if (!buf)
1484 return -ENOMEM;
1485
1486 ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
1487 kfree(buf);
1488 return ret;
1489}
1490
1491/*
1492 * handle a write to /proc/sgi_uv/ptc_statistics
1493 * -1: reset the statistics
1494 * 0: display meaning of the statistics
1495 */
1496static ssize_t ptc_proc_write(struct file *file, const char __user *user,
1497 size_t count, loff_t *data)
1498{
1499 int cpu;
1500 int i;
1501 int elements;
1502 long input_arg;
1503 char optstr[64];
1504 struct ptc_stats *stat;
1505
1506 if (count == 0 || count > sizeof(optstr))
1507 return -EINVAL;
1508 if (copy_from_user(optstr, user, count))
1509 return -EFAULT;
1510 optstr[count - 1] = '\0';
1511
1512 if (!strcmp(optstr, "on")) {
1513 set_bau_on();
1514 return count;
1515 } else if (!strcmp(optstr, "off")) {
1516 set_bau_off();
1517 return count;
1518 }
1519
1520 if (kstrtol(optstr, 10, &input_arg) < 0) {
1521 pr_debug("%s is invalid\n", optstr);
1522 return -EINVAL;
1523 }
1524
1525 if (input_arg == 0) {
1526 elements = ARRAY_SIZE(stat_description);
1527 pr_debug("# cpu: cpu number\n");
1528 pr_debug("Sender statistics:\n");
1529 for (i = 0; i < elements; i++)
1530 pr_debug("%s\n", stat_description[i]);
1531 } else if (input_arg == -1) {
1532 for_each_present_cpu(cpu) {
1533 stat = &per_cpu(ptcstats, cpu);
1534 memset(stat, 0, sizeof(struct ptc_stats));
1535 }
1536 }
1537
1538 return count;
1539}
1540
1541static int local_atoi(const char *name)
1542{
1543 int val = 0;
1544
1545 for (;; name++) {
1546 switch (*name) {
1547 case '0' ... '9':
1548 val = 10*val+(*name-'0');
1549 break;
1550 default:
1551 return val;
1552 }
1553 }
1554}
1555
1556/*
1557 * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables.
1558 * Zero values reset them to defaults.
1559 */
1560static int parse_tunables_write(struct bau_control *bcp, char *instr,
1561 int count)
1562{
1563 char *p;
1564 char *q;
1565 int cnt = 0;
1566 int val;
1567 int e = ARRAY_SIZE(tunables);
1568
1569 p = instr + strspn(instr, WHITESPACE);
1570 q = p;
1571 for (; *p; p = q + strspn(q, WHITESPACE)) {
1572 q = p + strcspn(p, WHITESPACE);
1573 cnt++;
1574 if (q == p)
1575 break;
1576 }
1577 if (cnt != e) {
1578 pr_info("bau tunable error: should be %d values\n", e);
1579 return -EINVAL;
1580 }
1581
1582 p = instr + strspn(instr, WHITESPACE);
1583 q = p;
1584 for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) {
1585 q = p + strcspn(p, WHITESPACE);
1586 val = local_atoi(p);
1587 switch (cnt) {
1588 case 0:
1589 if (val == 0) {
1590 max_concurr = MAX_BAU_CONCURRENT;
1591 max_concurr_const = MAX_BAU_CONCURRENT;
1592 continue;
1593 }
1594 if (val < 1 || val > bcp->cpus_in_uvhub) {
1595 pr_debug(
1596 "Error: BAU max concurrent %d is invalid\n",
1597 val);
1598 return -EINVAL;
1599 }
1600 max_concurr = val;
1601 max_concurr_const = val;
1602 continue;
1603 default:
1604 if (val == 0)
1605 *tunables[cnt].tunp = tunables[cnt].deflt;
1606 else
1607 *tunables[cnt].tunp = val;
1608 continue;
1609 }
1610 if (q == p)
1611 break;
1612 }
1613 return 0;
1614}
1615
1616/*
1617 * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables)
1618 */
1619static ssize_t tunables_write(struct file *file, const char __user *user,
1620 size_t count, loff_t *data)
1621{
1622 int cpu;
1623 int ret;
1624 char instr[100];
1625 struct bau_control *bcp;
1626
1627 if (count == 0 || count > sizeof(instr)-1)
1628 return -EINVAL;
1629 if (copy_from_user(instr, user, count))
1630 return -EFAULT;
1631
1632 instr[count] = '\0';
1633
1634 cpu = get_cpu();
1635 bcp = &per_cpu(bau_control, cpu);
1636 ret = parse_tunables_write(bcp, instr, count);
1637 put_cpu();
1638 if (ret)
1639 return ret;
1640
1641 for_each_present_cpu(cpu) {
1642 bcp = &per_cpu(bau_control, cpu);
1643 bcp->max_concurr = max_concurr;
1644 bcp->max_concurr_const = max_concurr;
1645 bcp->plugged_delay = plugged_delay;
1646 bcp->plugsb4reset = plugsb4reset;
1647 bcp->timeoutsb4reset = timeoutsb4reset;
1648 bcp->ipi_reset_limit = ipi_reset_limit;
1649 bcp->complete_threshold = complete_threshold;
1650 bcp->cong_response_us = congested_respns_us;
1651 bcp->cong_reps = congested_reps;
1652 bcp->disabled_period = sec_2_cycles(disabled_period);
1653 bcp->giveup_limit = giveup_limit;
1654 }
1655 return count;
1656}
1657
1658static const struct seq_operations uv_ptc_seq_ops = {
1659 .start = ptc_seq_start,
1660 .next = ptc_seq_next,
1661 .stop = ptc_seq_stop,
1662 .show = ptc_seq_show
1663};
1664
1665static int ptc_proc_open(struct inode *inode, struct file *file)
1666{
1667 return seq_open(file, &uv_ptc_seq_ops);
1668}
1669
1670static int tunables_open(struct inode *inode, struct file *file)
1671{
1672 return 0;
1673}
1674
1675static const struct file_operations proc_uv_ptc_operations = {
1676 .open = ptc_proc_open,
1677 .read = seq_read,
1678 .write = ptc_proc_write,
1679 .llseek = seq_lseek,
1680 .release = seq_release,
1681};
1682
1683static const struct file_operations tunables_fops = {
1684 .open = tunables_open,
1685 .read = tunables_read,
1686 .write = tunables_write,
1687 .llseek = default_llseek,
1688};
1689
1690static int __init uv_ptc_init(void)
1691{
1692 struct proc_dir_entry *proc_uv_ptc;
1693
1694 if (!is_uv_system())
1695 return 0;
1696
1697 proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL,
1698 &proc_uv_ptc_operations);
1699 if (!proc_uv_ptc) {
1700 pr_err("unable to create %s proc entry\n",
1701 UV_PTC_BASENAME);
1702 return -EINVAL;
1703 }
1704
1705 tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL);
1706 if (!tunables_dir) {
1707 pr_err("unable to create debugfs directory %s\n",
1708 UV_BAU_TUNABLES_DIR);
1709 return -EINVAL;
1710 }
1711 tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600,
1712 tunables_dir, NULL, &tunables_fops);
1713 if (!tunables_file) {
1714 pr_err("unable to create debugfs file %s\n",
1715 UV_BAU_TUNABLES_FILE);
1716 return -EINVAL;
1717 }
1718 return 0;
1719}
1720
1721/*
1722 * Initialize the sending side's sending buffers.
1723 */
1724static void activation_descriptor_init(int node, int pnode, int base_pnode)
1725{
1726 int i;
1727 int cpu;
1728 int uv1 = 0;
1729 unsigned long gpa;
1730 unsigned long m;
1731 unsigned long n;
1732 size_t dsize;
1733 struct bau_desc *bau_desc;
1734 struct bau_desc *bd2;
1735 struct uv1_bau_msg_header *uv1_hdr;
1736 struct uv2_3_bau_msg_header *uv2_3_hdr;
1737 struct bau_control *bcp;
1738
1739 /*
1740 * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC)
1741 * per cpu; and one per cpu on the uvhub (ADP_SZ)
1742 */
1743 dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC;
1744 bau_desc = kmalloc_node(dsize, GFP_KERNEL, node);
1745 BUG_ON(!bau_desc);
1746
1747 gpa = uv_gpa(bau_desc);
1748 n = uv_gpa_to_gnode(gpa);
1749 m = ops.bau_gpa_to_offset(gpa);
1750 if (is_uv1_hub())
1751 uv1 = 1;
1752
1753 /* the 14-bit pnode */
1754 write_mmr_descriptor_base(pnode,
1755 (n << UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT | m));
1756 /*
1757 * Initializing all 8 (ITEMS_PER_DESC) descriptors for each
1758 * cpu even though we only use the first one; one descriptor can
1759 * describe a broadcast to 256 uv hubs.
1760 */
1761 for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) {
1762 memset(bd2, 0, sizeof(struct bau_desc));
1763 if (uv1) {
1764 uv1_hdr = &bd2->header.uv1_hdr;
1765 uv1_hdr->swack_flag = 1;
1766 /*
1767 * The base_dest_nasid set in the message header
1768 * is the nasid of the first uvhub in the partition.
1769 * The bit map will indicate destination pnode numbers
1770 * relative to that base. They may not be consecutive
1771 * if nasid striding is being used.
1772 */
1773 uv1_hdr->base_dest_nasid =
1774 UV_PNODE_TO_NASID(base_pnode);
1775 uv1_hdr->dest_subnodeid = UV_LB_SUBNODEID;
1776 uv1_hdr->command = UV_NET_ENDPOINT_INTD;
1777 uv1_hdr->int_both = 1;
1778 /*
1779 * all others need to be set to zero:
1780 * fairness chaining multilevel count replied_to
1781 */
1782 } else {
1783 /*
1784 * BIOS uses legacy mode, but uv2 and uv3 hardware always
1785 * uses native mode for selective broadcasts.
1786 */
1787 uv2_3_hdr = &bd2->header.uv2_3_hdr;
1788 uv2_3_hdr->swack_flag = 1;
1789 uv2_3_hdr->base_dest_nasid =
1790 UV_PNODE_TO_NASID(base_pnode);
1791 uv2_3_hdr->dest_subnodeid = UV_LB_SUBNODEID;
1792 uv2_3_hdr->command = UV_NET_ENDPOINT_INTD;
1793 }
1794 }
1795 for_each_present_cpu(cpu) {
1796 if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu)))
1797 continue;
1798 bcp = &per_cpu(bau_control, cpu);
1799 bcp->descriptor_base = bau_desc;
1800 }
1801}
1802
1803/*
1804 * initialize the destination side's receiving buffers
1805 * entered for each uvhub in the partition
1806 * - node is first node (kernel memory notion) on the uvhub
1807 * - pnode is the uvhub's physical identifier
1808 */
1809static void pq_init(int node, int pnode)
1810{
1811 int cpu;
1812 size_t plsize;
1813 char *cp;
1814 void *vp;
1815 unsigned long gnode, first, last, tail;
1816 struct bau_pq_entry *pqp;
1817 struct bau_control *bcp;
1818
1819 plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry);
1820 vp = kmalloc_node(plsize, GFP_KERNEL, node);
1821 pqp = (struct bau_pq_entry *)vp;
1822 BUG_ON(!pqp);
1823
1824 cp = (char *)pqp + 31;
1825 pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5);
1826
1827 for_each_present_cpu(cpu) {
1828 if (pnode != uv_cpu_to_pnode(cpu))
1829 continue;
1830 /* for every cpu on this pnode: */
1831 bcp = &per_cpu(bau_control, cpu);
1832 bcp->queue_first = pqp;
1833 bcp->bau_msg_head = pqp;
1834 bcp->queue_last = pqp + (DEST_Q_SIZE - 1);
1835 }
1836
1837 first = ops.bau_gpa_to_offset(uv_gpa(pqp));
1838 last = ops.bau_gpa_to_offset(uv_gpa(pqp + (DEST_Q_SIZE - 1)));
1839
1840 /*
1841 * Pre UV4, the gnode is required to locate the payload queue
1842 * and the payload queue tail must be maintained by the kernel.
1843 */
1844 bcp = &per_cpu(bau_control, smp_processor_id());
1845 if (bcp->uvhub_version <= UV_BAU_V3) {
1846 tail = first;
1847 gnode = uv_gpa_to_gnode(uv_gpa(pqp));
1848 first = (gnode << UV_PAYLOADQ_GNODE_SHIFT) | tail;
1849 write_mmr_payload_tail(pnode, tail);
1850 }
1851
1852 ops.write_payload_first(pnode, first);
1853 ops.write_payload_last(pnode, last);
1854
1855 /* in effect, all msg_type's are set to MSG_NOOP */
1856 memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE);
1857}
1858
1859/*
1860 * Initialization of each UV hub's structures
1861 */
1862static void __init init_uvhub(int uvhub, int vector, int base_pnode)
1863{
1864 int node;
1865 int pnode;
1866 unsigned long apicid;
1867
1868 node = uvhub_to_first_node(uvhub);
1869 pnode = uv_blade_to_pnode(uvhub);
1870
1871 activation_descriptor_init(node, pnode, base_pnode);
1872
1873 pq_init(node, pnode);
1874 /*
1875 * The below initialization can't be in firmware because the
1876 * messaging IRQ will be determined by the OS.
1877 */
1878 apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
1879 write_mmr_data_config(pnode, ((apicid << 32) | vector));
1880}
1881
1882/*
1883 * We will set BAU_MISC_CONTROL with a timeout period.
1884 * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT.
1885 * So the destination timeout period has to be calculated from them.
1886 */
1887static int calculate_destination_timeout(void)
1888{
1889 unsigned long mmr_image;
1890 int mult1;
1891 int mult2;
1892 int index;
1893 int base;
1894 int ret;
1895 unsigned long ts_ns;
1896
1897 if (is_uv1_hub()) {
1898 mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK;
1899 mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
1900 index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
1901 mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
1902 mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
1903 ts_ns = timeout_base_ns[index];
1904 ts_ns *= (mult1 * mult2);
1905 ret = ts_ns / 1000;
1906 } else {
1907 /* same destination timeout for uv2 and uv3 */
1908 /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */
1909 mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL);
1910 mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT;
1911 if (mmr_image & (1L << UV2_ACK_UNITS_SHFT))
1912 base = 80;
1913 else
1914 base = 10;
1915 mult1 = mmr_image & UV2_ACK_MASK;
1916 ret = mult1 * base;
1917 }
1918 return ret;
1919}
1920
1921static void __init init_per_cpu_tunables(void)
1922{
1923 int cpu;
1924 struct bau_control *bcp;
1925
1926 for_each_present_cpu(cpu) {
1927 bcp = &per_cpu(bau_control, cpu);
1928 bcp->baudisabled = 0;
1929 if (nobau)
1930 bcp->nobau = true;
1931 bcp->statp = &per_cpu(ptcstats, cpu);
1932 /* time interval to catch a hardware stay-busy bug */
1933 bcp->timeout_interval = usec_2_cycles(2*timeout_us);
1934 bcp->max_concurr = max_concurr;
1935 bcp->max_concurr_const = max_concurr;
1936 bcp->plugged_delay = plugged_delay;
1937 bcp->plugsb4reset = plugsb4reset;
1938 bcp->timeoutsb4reset = timeoutsb4reset;
1939 bcp->ipi_reset_limit = ipi_reset_limit;
1940 bcp->complete_threshold = complete_threshold;
1941 bcp->cong_response_us = congested_respns_us;
1942 bcp->cong_reps = congested_reps;
1943 bcp->disabled_period = sec_2_cycles(disabled_period);
1944 bcp->giveup_limit = giveup_limit;
1945 spin_lock_init(&bcp->queue_lock);
1946 spin_lock_init(&bcp->uvhub_lock);
1947 spin_lock_init(&bcp->disable_lock);
1948 }
1949}
1950
1951/*
1952 * Scan all cpus to collect blade and socket summaries.
1953 */
1954static int __init get_cpu_topology(int base_pnode,
1955 struct uvhub_desc *uvhub_descs,
1956 unsigned char *uvhub_mask)
1957{
1958 int cpu;
1959 int pnode;
1960 int uvhub;
1961 int socket;
1962 struct bau_control *bcp;
1963 struct uvhub_desc *bdp;
1964 struct socket_desc *sdp;
1965
1966 for_each_present_cpu(cpu) {
1967 bcp = &per_cpu(bau_control, cpu);
1968
1969 memset(bcp, 0, sizeof(struct bau_control));
1970
1971 pnode = uv_cpu_hub_info(cpu)->pnode;
1972 if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) {
1973 pr_emerg(
1974 "cpu %d pnode %d-%d beyond %d; BAU disabled\n",
1975 cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE);
1976 return 1;
1977 }
1978
1979 bcp->osnode = cpu_to_node(cpu);
1980 bcp->partition_base_pnode = base_pnode;
1981
1982 uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
1983 *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
1984 bdp = &uvhub_descs[uvhub];
1985
1986 bdp->num_cpus++;
1987 bdp->uvhub = uvhub;
1988 bdp->pnode = pnode;
1989
1990 /* kludge: 'assuming' one node per socket, and assuming that
1991 disabling a socket just leaves a gap in node numbers */
1992 socket = bcp->osnode & 1;
1993 bdp->socket_mask |= (1 << socket);
1994 sdp = &bdp->socket[socket];
1995 sdp->cpu_number[sdp->num_cpus] = cpu;
1996 sdp->num_cpus++;
1997 if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
1998 pr_emerg("%d cpus per socket invalid\n",
1999 sdp->num_cpus);
2000 return 1;
2001 }
2002 }
2003 return 0;
2004}
2005
2006/*
2007 * Each socket is to get a local array of pnodes/hubs.
2008 */
2009static void make_per_cpu_thp(struct bau_control *smaster)
2010{
2011 int cpu;
2012 size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus();
2013
2014 smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode);
2015 memset(smaster->thp, 0, hpsz);
2016 for_each_present_cpu(cpu) {
2017 smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode;
2018 smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
2019 }
2020}
2021
2022/*
2023 * Each uvhub is to get a local cpumask.
2024 */
2025static void make_per_hub_cpumask(struct bau_control *hmaster)
2026{
2027 int sz = sizeof(cpumask_t);
2028
2029 hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode);
2030}
2031
2032/*
2033 * Initialize all the per_cpu information for the cpu's on a given socket,
2034 * given what has been gathered into the socket_desc struct.
2035 * And reports the chosen hub and socket masters back to the caller.
2036 */
2037static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
2038 struct bau_control **smasterp,
2039 struct bau_control **hmasterp)
2040{
2041 int i, cpu, uvhub_cpu;
2042 struct bau_control *bcp;
2043
2044 for (i = 0; i < sdp->num_cpus; i++) {
2045 cpu = sdp->cpu_number[i];
2046 bcp = &per_cpu(bau_control, cpu);
2047 bcp->cpu = cpu;
2048 if (i == 0) {
2049 *smasterp = bcp;
2050 if (!(*hmasterp))
2051 *hmasterp = bcp;
2052 }
2053 bcp->cpus_in_uvhub = bdp->num_cpus;
2054 bcp->cpus_in_socket = sdp->num_cpus;
2055 bcp->socket_master = *smasterp;
2056 bcp->uvhub = bdp->uvhub;
2057 if (is_uv1_hub())
2058 bcp->uvhub_version = UV_BAU_V1;
2059 else if (is_uv2_hub())
2060 bcp->uvhub_version = UV_BAU_V2;
2061 else if (is_uv3_hub())
2062 bcp->uvhub_version = UV_BAU_V3;
2063 else if (is_uv4_hub())
2064 bcp->uvhub_version = UV_BAU_V4;
2065 else {
2066 pr_emerg("uvhub version not 1, 2, 3, or 4\n");
2067 return 1;
2068 }
2069 bcp->uvhub_master = *hmasterp;
2070 uvhub_cpu = uv_cpu_blade_processor_id(cpu);
2071 bcp->uvhub_cpu = uvhub_cpu;
2072
2073 /*
2074 * The ERROR and BUSY status registers are located pairwise over
2075 * the STATUS_0 and STATUS_1 mmrs; each an array[32] of 2 bits.
2076 */
2077 if (uvhub_cpu < UV_CPUS_PER_AS) {
2078 bcp->status_mmr = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
2079 bcp->status_index = uvhub_cpu * UV_ACT_STATUS_SIZE;
2080 } else {
2081 bcp->status_mmr = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
2082 bcp->status_index = (uvhub_cpu - UV_CPUS_PER_AS)
2083 * UV_ACT_STATUS_SIZE;
2084 }
2085
2086 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
2087 pr_emerg("%d cpus per uvhub invalid\n",
2088 bcp->uvhub_cpu);
2089 return 1;
2090 }
2091 }
2092 return 0;
2093}
2094
2095/*
2096 * Summarize the blade and socket topology into the per_cpu structures.
2097 */
2098static int __init summarize_uvhub_sockets(int nuvhubs,
2099 struct uvhub_desc *uvhub_descs,
2100 unsigned char *uvhub_mask)
2101{
2102 int socket;
2103 int uvhub;
2104 unsigned short socket_mask;
2105
2106 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
2107 struct uvhub_desc *bdp;
2108 struct bau_control *smaster = NULL;
2109 struct bau_control *hmaster = NULL;
2110
2111 if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
2112 continue;
2113
2114 bdp = &uvhub_descs[uvhub];
2115 socket_mask = bdp->socket_mask;
2116 socket = 0;
2117 while (socket_mask) {
2118 struct socket_desc *sdp;
2119 if ((socket_mask & 1)) {
2120 sdp = &bdp->socket[socket];
2121 if (scan_sock(sdp, bdp, &smaster, &hmaster))
2122 return 1;
2123 make_per_cpu_thp(smaster);
2124 }
2125 socket++;
2126 socket_mask = (socket_mask >> 1);
2127 }
2128 make_per_hub_cpumask(hmaster);
2129 }
2130 return 0;
2131}
2132
2133/*
2134 * initialize the bau_control structure for each cpu
2135 */
2136static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
2137{
2138 unsigned char *uvhub_mask;
2139 void *vp;
2140 struct uvhub_desc *uvhub_descs;
2141
2142 if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub())
2143 timeout_us = calculate_destination_timeout();
2144
2145 vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
2146 uvhub_descs = (struct uvhub_desc *)vp;
2147 memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
2148 uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
2149
2150 if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
2151 goto fail;
2152
2153 if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
2154 goto fail;
2155
2156 kfree(uvhub_descs);
2157 kfree(uvhub_mask);
2158 init_per_cpu_tunables();
2159 return 0;
2160
2161fail:
2162 kfree(uvhub_descs);
2163 kfree(uvhub_mask);
2164 return 1;
2165}
2166
2167static const struct bau_operations uv1_bau_ops __initconst = {
2168 .bau_gpa_to_offset = uv_gpa_to_offset,
2169 .read_l_sw_ack = read_mmr_sw_ack,
2170 .read_g_sw_ack = read_gmmr_sw_ack,
2171 .write_l_sw_ack = write_mmr_sw_ack,
2172 .write_g_sw_ack = write_gmmr_sw_ack,
2173 .write_payload_first = write_mmr_payload_first,
2174 .write_payload_last = write_mmr_payload_last,
2175 .wait_completion = uv1_wait_completion,
2176};
2177
2178static const struct bau_operations uv2_3_bau_ops __initconst = {
2179 .bau_gpa_to_offset = uv_gpa_to_offset,
2180 .read_l_sw_ack = read_mmr_sw_ack,
2181 .read_g_sw_ack = read_gmmr_sw_ack,
2182 .write_l_sw_ack = write_mmr_sw_ack,
2183 .write_g_sw_ack = write_gmmr_sw_ack,
2184 .write_payload_first = write_mmr_payload_first,
2185 .write_payload_last = write_mmr_payload_last,
2186 .wait_completion = uv2_3_wait_completion,
2187};
2188
2189static const struct bau_operations uv4_bau_ops __initconst = {
2190 .bau_gpa_to_offset = uv_gpa_to_soc_phys_ram,
2191 .read_l_sw_ack = read_mmr_proc_sw_ack,
2192 .read_g_sw_ack = read_gmmr_proc_sw_ack,
2193 .write_l_sw_ack = write_mmr_proc_sw_ack,
2194 .write_g_sw_ack = write_gmmr_proc_sw_ack,
2195 .write_payload_first = write_mmr_proc_payload_first,
2196 .write_payload_last = write_mmr_proc_payload_last,
2197 .wait_completion = uv4_wait_completion,
2198};
2199
2200/*
2201 * Initialization of BAU-related structures
2202 */
2203static int __init uv_bau_init(void)
2204{
2205 int uvhub;
2206 int pnode;
2207 int nuvhubs;
2208 int cur_cpu;
2209 int cpus;
2210 int vector;
2211 cpumask_var_t *mask;
2212
2213 if (!is_uv_system())
2214 return 0;
2215
2216 if (is_uv4_hub())
2217 ops = uv4_bau_ops;
2218 else if (is_uv3_hub())
2219 ops = uv2_3_bau_ops;
2220 else if (is_uv2_hub())
2221 ops = uv2_3_bau_ops;
2222 else if (is_uv1_hub())
2223 ops = uv1_bau_ops;
2224
2225 nuvhubs = uv_num_possible_blades();
2226 if (nuvhubs < 2) {
2227 pr_crit("UV: BAU disabled - insufficient hub count\n");
2228 goto err_bau_disable;
2229 }
2230
2231 for_each_possible_cpu(cur_cpu) {
2232 mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
2233 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu));
2234 }
2235
2236 uv_base_pnode = 0x7fffffff;
2237 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
2238 cpus = uv_blade_nr_possible_cpus(uvhub);
2239 if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode))
2240 uv_base_pnode = uv_blade_to_pnode(uvhub);
2241 }
2242
2243 /* software timeouts are not supported on UV4 */
2244 if (is_uv3_hub() || is_uv2_hub() || is_uv1_hub())
2245 enable_timeouts();
2246
2247 if (init_per_cpu(nuvhubs, uv_base_pnode)) {
2248 pr_crit("UV: BAU disabled - per CPU init failed\n");
2249 goto err_bau_disable;
2250 }
2251
2252 vector = UV_BAU_MESSAGE;
2253 for_each_possible_blade(uvhub) {
2254 if (uv_blade_nr_possible_cpus(uvhub))
2255 init_uvhub(uvhub, vector, uv_base_pnode);
2256 }
2257
2258 for_each_possible_blade(uvhub) {
2259 if (uv_blade_nr_possible_cpus(uvhub)) {
2260 unsigned long val;
2261 unsigned long mmr;
2262 pnode = uv_blade_to_pnode(uvhub);
2263 /* INIT the bau */
2264 val = 1L << 63;
2265 write_gmmr_activation(pnode, val);
2266 mmr = 1; /* should be 1 to broadcast to both sockets */
2267 if (!is_uv1_hub())
2268 write_mmr_data_broadcast(pnode, mmr);
2269 }
2270 }
2271
2272 return 0;
2273
2274err_bau_disable:
2275
2276 for_each_possible_cpu(cur_cpu)
2277 free_cpumask_var(per_cpu(uv_flush_tlb_mask, cur_cpu));
2278
2279 set_bau_off();
2280 nobau_perm = 1;
2281
2282 return -EINVAL;
2283}
2284core_initcall(uv_bau_init);
2285fs_initcall(uv_ptc_init);