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1// SPDX-License-Identifier: GPL-2.0
2#include <linux/kernel.h>
3#include <linux/pgtable.h>
4
5#include <linux/string.h>
6#include <linux/bitops.h>
7#include <linux/smp.h>
8#include <linux/sched.h>
9#include <linux/sched/clock.h>
10#include <linux/semaphore.h>
11#include <linux/thread_info.h>
12#include <linux/init.h>
13#include <linux/uaccess.h>
14#include <linux/workqueue.h>
15#include <linux/delay.h>
16#include <linux/cpuhotplug.h>
17
18#include <asm/cpufeature.h>
19#include <asm/msr.h>
20#include <asm/bugs.h>
21#include <asm/cpu.h>
22#include <asm/intel-family.h>
23#include <asm/microcode_intel.h>
24#include <asm/hwcap2.h>
25#include <asm/elf.h>
26#include <asm/cpu_device_id.h>
27#include <asm/cmdline.h>
28#include <asm/traps.h>
29#include <asm/resctrl.h>
30#include <asm/numa.h>
31#include <asm/thermal.h>
32
33#ifdef CONFIG_X86_64
34#include <linux/topology.h>
35#endif
36
37#include "cpu.h"
38
39#ifdef CONFIG_X86_LOCAL_APIC
40#include <asm/mpspec.h>
41#include <asm/apic.h>
42#endif
43
44enum split_lock_detect_state {
45 sld_off = 0,
46 sld_warn,
47 sld_fatal,
48 sld_ratelimit,
49};
50
51/*
52 * Default to sld_off because most systems do not support split lock detection.
53 * sld_state_setup() will switch this to sld_warn on systems that support
54 * split lock/bus lock detect, unless there is a command line override.
55 */
56static enum split_lock_detect_state sld_state __ro_after_init = sld_off;
57static u64 msr_test_ctrl_cache __ro_after_init;
58
59/*
60 * With a name like MSR_TEST_CTL it should go without saying, but don't touch
61 * MSR_TEST_CTL unless the CPU is one of the whitelisted models. Writing it
62 * on CPUs that do not support SLD can cause fireworks, even when writing '0'.
63 */
64static bool cpu_model_supports_sld __ro_after_init;
65
66/*
67 * Processors which have self-snooping capability can handle conflicting
68 * memory type across CPUs by snooping its own cache. However, there exists
69 * CPU models in which having conflicting memory types still leads to
70 * unpredictable behavior, machine check errors, or hangs. Clear this
71 * feature to prevent its use on machines with known erratas.
72 */
73static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
74{
75 switch (c->x86_model) {
76 case INTEL_FAM6_CORE_YONAH:
77 case INTEL_FAM6_CORE2_MEROM:
78 case INTEL_FAM6_CORE2_MEROM_L:
79 case INTEL_FAM6_CORE2_PENRYN:
80 case INTEL_FAM6_CORE2_DUNNINGTON:
81 case INTEL_FAM6_NEHALEM:
82 case INTEL_FAM6_NEHALEM_G:
83 case INTEL_FAM6_NEHALEM_EP:
84 case INTEL_FAM6_NEHALEM_EX:
85 case INTEL_FAM6_WESTMERE:
86 case INTEL_FAM6_WESTMERE_EP:
87 case INTEL_FAM6_SANDYBRIDGE:
88 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
89 }
90}
91
92static bool ring3mwait_disabled __read_mostly;
93
94static int __init ring3mwait_disable(char *__unused)
95{
96 ring3mwait_disabled = true;
97 return 1;
98}
99__setup("ring3mwait=disable", ring3mwait_disable);
100
101static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
102{
103 /*
104 * Ring 3 MONITOR/MWAIT feature cannot be detected without
105 * cpu model and family comparison.
106 */
107 if (c->x86 != 6)
108 return;
109 switch (c->x86_model) {
110 case INTEL_FAM6_XEON_PHI_KNL:
111 case INTEL_FAM6_XEON_PHI_KNM:
112 break;
113 default:
114 return;
115 }
116
117 if (ring3mwait_disabled)
118 return;
119
120 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
121 this_cpu_or(msr_misc_features_shadow,
122 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
123
124 if (c == &boot_cpu_data)
125 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
126}
127
128/*
129 * Early microcode releases for the Spectre v2 mitigation were broken.
130 * Information taken from;
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132 * - https://kb.vmware.com/s/article/52345
133 * - Microcode revisions observed in the wild
134 * - Release note from 20180108 microcode release
135 */
136struct sku_microcode {
137 u8 model;
138 u8 stepping;
139 u32 microcode;
140};
141static const struct sku_microcode spectre_bad_microcodes[] = {
142 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
143 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
144 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
145 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
146 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
147 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
148 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
149 { INTEL_FAM6_BROADWELL, 0x04, 0x28 },
150 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
151 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
152 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
153 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
154 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
155 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
156 { INTEL_FAM6_HASWELL, 0x03, 0x23 },
157 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
158 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
159 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
160 /* Observed in the wild */
161 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
162 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
163};
164
165static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
166{
167 int i;
168
169 /*
170 * We know that the hypervisor lie to us on the microcode version so
171 * we may as well hope that it is running the correct version.
172 */
173 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
174 return false;
175
176 if (c->x86 != 6)
177 return false;
178
179 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
180 if (c->x86_model == spectre_bad_microcodes[i].model &&
181 c->x86_stepping == spectre_bad_microcodes[i].stepping)
182 return (c->microcode <= spectre_bad_microcodes[i].microcode);
183 }
184 return false;
185}
186
187int intel_cpu_collect_info(struct ucode_cpu_info *uci)
188{
189 unsigned int val[2];
190 unsigned int family, model;
191 struct cpu_signature csig = { 0 };
192 unsigned int eax, ebx, ecx, edx;
193
194 memset(uci, 0, sizeof(*uci));
195
196 eax = 0x00000001;
197 ecx = 0;
198 native_cpuid(&eax, &ebx, &ecx, &edx);
199 csig.sig = eax;
200
201 family = x86_family(eax);
202 model = x86_model(eax);
203
204 if (model >= 5 || family > 6) {
205 /* get processor flags from MSR 0x17 */
206 native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
207 csig.pf = 1 << ((val[1] >> 18) & 7);
208 }
209
210 csig.rev = intel_get_microcode_revision();
211
212 uci->cpu_sig = csig;
213
214 return 0;
215}
216EXPORT_SYMBOL_GPL(intel_cpu_collect_info);
217
218/*
219 * Returns 1 if update has been found, 0 otherwise.
220 */
221int intel_find_matching_signature(void *mc, unsigned int csig, int cpf)
222{
223 struct microcode_header_intel *mc_hdr = mc;
224 struct extended_sigtable *ext_hdr;
225 struct extended_signature *ext_sig;
226 int i;
227
228 if (intel_cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf))
229 return 1;
230
231 /* Look for ext. headers: */
232 if (get_totalsize(mc_hdr) <= get_datasize(mc_hdr) + MC_HEADER_SIZE)
233 return 0;
234
235 ext_hdr = mc + get_datasize(mc_hdr) + MC_HEADER_SIZE;
236 ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE;
237
238 for (i = 0; i < ext_hdr->count; i++) {
239 if (intel_cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf))
240 return 1;
241 ext_sig++;
242 }
243 return 0;
244}
245EXPORT_SYMBOL_GPL(intel_find_matching_signature);
246
247/**
248 * intel_microcode_sanity_check() - Sanity check microcode file.
249 * @mc: Pointer to the microcode file contents.
250 * @print_err: Display failure reason if true, silent if false.
251 * @hdr_type: Type of file, i.e. normal microcode file or In Field Scan file.
252 * Validate if the microcode header type matches with the type
253 * specified here.
254 *
255 * Validate certain header fields and verify if computed checksum matches
256 * with the one specified in the header.
257 *
258 * Return: 0 if the file passes all the checks, -EINVAL if any of the checks
259 * fail.
260 */
261int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type)
262{
263 unsigned long total_size, data_size, ext_table_size;
264 struct microcode_header_intel *mc_header = mc;
265 struct extended_sigtable *ext_header = NULL;
266 u32 sum, orig_sum, ext_sigcount = 0, i;
267 struct extended_signature *ext_sig;
268
269 total_size = get_totalsize(mc_header);
270 data_size = get_datasize(mc_header);
271
272 if (data_size + MC_HEADER_SIZE > total_size) {
273 if (print_err)
274 pr_err("Error: bad microcode data file size.\n");
275 return -EINVAL;
276 }
277
278 if (mc_header->ldrver != 1 || mc_header->hdrver != hdr_type) {
279 if (print_err)
280 pr_err("Error: invalid/unknown microcode update format. Header type %d\n",
281 mc_header->hdrver);
282 return -EINVAL;
283 }
284
285 ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
286 if (ext_table_size) {
287 u32 ext_table_sum = 0;
288 u32 *ext_tablep;
289
290 if (ext_table_size < EXT_HEADER_SIZE ||
291 ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
292 if (print_err)
293 pr_err("Error: truncated extended signature table.\n");
294 return -EINVAL;
295 }
296
297 ext_header = mc + MC_HEADER_SIZE + data_size;
298 if (ext_table_size != exttable_size(ext_header)) {
299 if (print_err)
300 pr_err("Error: extended signature table size mismatch.\n");
301 return -EFAULT;
302 }
303
304 ext_sigcount = ext_header->count;
305
306 /*
307 * Check extended table checksum: the sum of all dwords that
308 * comprise a valid table must be 0.
309 */
310 ext_tablep = (u32 *)ext_header;
311
312 i = ext_table_size / sizeof(u32);
313 while (i--)
314 ext_table_sum += ext_tablep[i];
315
316 if (ext_table_sum) {
317 if (print_err)
318 pr_warn("Bad extended signature table checksum, aborting.\n");
319 return -EINVAL;
320 }
321 }
322
323 /*
324 * Calculate the checksum of update data and header. The checksum of
325 * valid update data and header including the extended signature table
326 * must be 0.
327 */
328 orig_sum = 0;
329 i = (MC_HEADER_SIZE + data_size) / sizeof(u32);
330 while (i--)
331 orig_sum += ((u32 *)mc)[i];
332
333 if (orig_sum) {
334 if (print_err)
335 pr_err("Bad microcode data checksum, aborting.\n");
336 return -EINVAL;
337 }
338
339 if (!ext_table_size)
340 return 0;
341
342 /*
343 * Check extended signature checksum: 0 => valid.
344 */
345 for (i = 0; i < ext_sigcount; i++) {
346 ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
347 EXT_SIGNATURE_SIZE * i;
348
349 sum = (mc_header->sig + mc_header->pf + mc_header->cksum) -
350 (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
351 if (sum) {
352 if (print_err)
353 pr_err("Bad extended signature checksum, aborting.\n");
354 return -EINVAL;
355 }
356 }
357 return 0;
358}
359EXPORT_SYMBOL_GPL(intel_microcode_sanity_check);
360
361static void early_init_intel(struct cpuinfo_x86 *c)
362{
363 u64 misc_enable;
364
365 /* Unmask CPUID levels if masked: */
366 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
367 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
368 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
369 c->cpuid_level = cpuid_eax(0);
370 get_cpu_cap(c);
371 }
372 }
373
374 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
375 (c->x86 == 0x6 && c->x86_model >= 0x0e))
376 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
377
378 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
379 c->microcode = intel_get_microcode_revision();
380
381 /* Now if any of them are set, check the blacklist and clear the lot */
382 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
383 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
384 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
385 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
386 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
387 setup_clear_cpu_cap(X86_FEATURE_IBRS);
388 setup_clear_cpu_cap(X86_FEATURE_IBPB);
389 setup_clear_cpu_cap(X86_FEATURE_STIBP);
390 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
391 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
392 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
393 setup_clear_cpu_cap(X86_FEATURE_SSBD);
394 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
395 }
396
397 /*
398 * Atom erratum AAE44/AAF40/AAG38/AAH41:
399 *
400 * A race condition between speculative fetches and invalidating
401 * a large page. This is worked around in microcode, but we
402 * need the microcode to have already been loaded... so if it is
403 * not, recommend a BIOS update and disable large pages.
404 */
405 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
406 c->microcode < 0x20e) {
407 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
408 clear_cpu_cap(c, X86_FEATURE_PSE);
409 }
410
411#ifdef CONFIG_X86_64
412 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
413#else
414 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
415 if (c->x86 == 15 && c->x86_cache_alignment == 64)
416 c->x86_cache_alignment = 128;
417#endif
418
419 /* CPUID workaround for 0F33/0F34 CPU */
420 if (c->x86 == 0xF && c->x86_model == 0x3
421 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
422 c->x86_phys_bits = 36;
423
424 /*
425 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
426 * with P/T states and does not stop in deep C-states.
427 *
428 * It is also reliable across cores and sockets. (but not across
429 * cabinets - we turn it off in that case explicitly.)
430 */
431 if (c->x86_power & (1 << 8)) {
432 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
433 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
434 }
435
436 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
437 if (c->x86 == 6) {
438 switch (c->x86_model) {
439 case INTEL_FAM6_ATOM_SALTWELL_MID:
440 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
441 case INTEL_FAM6_ATOM_SILVERMONT_MID:
442 case INTEL_FAM6_ATOM_AIRMONT_NP:
443 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
444 break;
445 default:
446 break;
447 }
448 }
449
450 /*
451 * There is a known erratum on Pentium III and Core Solo
452 * and Core Duo CPUs.
453 * " Page with PAT set to WC while associated MTRR is UC
454 * may consolidate to UC "
455 * Because of this erratum, it is better to stick with
456 * setting WC in MTRR rather than using PAT on these CPUs.
457 *
458 * Enable PAT WC only on P4, Core 2 or later CPUs.
459 */
460 if (c->x86 == 6 && c->x86_model < 15)
461 clear_cpu_cap(c, X86_FEATURE_PAT);
462
463 /*
464 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
465 * clear the fast string and enhanced fast string CPU capabilities.
466 */
467 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
468 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
469 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
470 pr_info("Disabled fast string operations\n");
471 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
472 setup_clear_cpu_cap(X86_FEATURE_ERMS);
473 }
474 }
475
476 /*
477 * Intel Quark Core DevMan_001.pdf section 6.4.11
478 * "The operating system also is required to invalidate (i.e., flush)
479 * the TLB when any changes are made to any of the page table entries.
480 * The operating system must reload CR3 to cause the TLB to be flushed"
481 *
482 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
483 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE
484 * to be modified.
485 */
486 if (c->x86 == 5 && c->x86_model == 9) {
487 pr_info("Disabling PGE capability bit\n");
488 setup_clear_cpu_cap(X86_FEATURE_PGE);
489 }
490
491 if (c->cpuid_level >= 0x00000001) {
492 u32 eax, ebx, ecx, edx;
493
494 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
495 /*
496 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
497 * apicids which are reserved per package. Store the resulting
498 * shift value for the package management code.
499 */
500 if (edx & (1U << 28))
501 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
502 }
503
504 check_memory_type_self_snoop_errata(c);
505
506 /*
507 * Get the number of SMT siblings early from the extended topology
508 * leaf, if available. Otherwise try the legacy SMT detection.
509 */
510 if (detect_extended_topology_early(c) < 0)
511 detect_ht_early(c);
512}
513
514static void bsp_init_intel(struct cpuinfo_x86 *c)
515{
516 resctrl_cpu_detect(c);
517}
518
519#ifdef CONFIG_X86_32
520/*
521 * Early probe support logic for ppro memory erratum #50
522 *
523 * This is called before we do cpu ident work
524 */
525
526int ppro_with_ram_bug(void)
527{
528 /* Uses data from early_cpu_detect now */
529 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
530 boot_cpu_data.x86 == 6 &&
531 boot_cpu_data.x86_model == 1 &&
532 boot_cpu_data.x86_stepping < 8) {
533 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
534 return 1;
535 }
536 return 0;
537}
538
539static void intel_smp_check(struct cpuinfo_x86 *c)
540{
541 /* calling is from identify_secondary_cpu() ? */
542 if (!c->cpu_index)
543 return;
544
545 /*
546 * Mask B, Pentium, but not Pentium MMX
547 */
548 if (c->x86 == 5 &&
549 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
550 c->x86_model <= 3) {
551 /*
552 * Remember we have B step Pentia with bugs
553 */
554 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
555 "with B stepping processors.\n");
556 }
557}
558
559static int forcepae;
560static int __init forcepae_setup(char *__unused)
561{
562 forcepae = 1;
563 return 1;
564}
565__setup("forcepae", forcepae_setup);
566
567static void intel_workarounds(struct cpuinfo_x86 *c)
568{
569#ifdef CONFIG_X86_F00F_BUG
570 /*
571 * All models of Pentium and Pentium with MMX technology CPUs
572 * have the F0 0F bug, which lets nonprivileged users lock up the
573 * system. Announce that the fault handler will be checking for it.
574 * The Quark is also family 5, but does not have the same bug.
575 */
576 clear_cpu_bug(c, X86_BUG_F00F);
577 if (c->x86 == 5 && c->x86_model < 9) {
578 static int f00f_workaround_enabled;
579
580 set_cpu_bug(c, X86_BUG_F00F);
581 if (!f00f_workaround_enabled) {
582 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
583 f00f_workaround_enabled = 1;
584 }
585 }
586#endif
587
588 /*
589 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
590 * model 3 mask 3
591 */
592 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
593 clear_cpu_cap(c, X86_FEATURE_SEP);
594
595 /*
596 * PAE CPUID issue: many Pentium M report no PAE but may have a
597 * functionally usable PAE implementation.
598 * Forcefully enable PAE if kernel parameter "forcepae" is present.
599 */
600 if (forcepae) {
601 pr_warn("PAE forced!\n");
602 set_cpu_cap(c, X86_FEATURE_PAE);
603 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
604 }
605
606 /*
607 * P4 Xeon erratum 037 workaround.
608 * Hardware prefetcher may cause stale data to be loaded into the cache.
609 */
610 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
611 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
612 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
613 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
614 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
615 }
616 }
617
618 /*
619 * See if we have a good local APIC by checking for buggy Pentia,
620 * i.e. all B steppings and the C2 stepping of P54C when using their
621 * integrated APIC (see 11AP erratum in "Pentium Processor
622 * Specification Update").
623 */
624 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
625 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
626 set_cpu_bug(c, X86_BUG_11AP);
627
628
629#ifdef CONFIG_X86_INTEL_USERCOPY
630 /*
631 * Set up the preferred alignment for movsl bulk memory moves
632 */
633 switch (c->x86) {
634 case 4: /* 486: untested */
635 break;
636 case 5: /* Old Pentia: untested */
637 break;
638 case 6: /* PII/PIII only like movsl with 8-byte alignment */
639 movsl_mask.mask = 7;
640 break;
641 case 15: /* P4 is OK down to 8-byte alignment */
642 movsl_mask.mask = 7;
643 break;
644 }
645#endif
646
647 intel_smp_check(c);
648}
649#else
650static void intel_workarounds(struct cpuinfo_x86 *c)
651{
652}
653#endif
654
655static void srat_detect_node(struct cpuinfo_x86 *c)
656{
657#ifdef CONFIG_NUMA
658 unsigned node;
659 int cpu = smp_processor_id();
660
661 /* Don't do the funky fallback heuristics the AMD version employs
662 for now. */
663 node = numa_cpu_node(cpu);
664 if (node == NUMA_NO_NODE || !node_online(node)) {
665 /* reuse the value from init_cpu_to_node() */
666 node = cpu_to_node(cpu);
667 }
668 numa_set_node(cpu, node);
669#endif
670}
671
672#define MSR_IA32_TME_ACTIVATE 0x982
673
674/* Helpers to access TME_ACTIVATE MSR */
675#define TME_ACTIVATE_LOCKED(x) (x & 0x1)
676#define TME_ACTIVATE_ENABLED(x) (x & 0x2)
677
678#define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
679#define TME_ACTIVATE_POLICY_AES_XTS_128 0
680
681#define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
682
683#define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
684#define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
685
686/* Values for mktme_status (SW only construct) */
687#define MKTME_ENABLED 0
688#define MKTME_DISABLED 1
689#define MKTME_UNINITIALIZED 2
690static int mktme_status = MKTME_UNINITIALIZED;
691
692static void detect_tme(struct cpuinfo_x86 *c)
693{
694 u64 tme_activate, tme_policy, tme_crypto_algs;
695 int keyid_bits = 0, nr_keyids = 0;
696 static u64 tme_activate_cpu0 = 0;
697
698 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
699
700 if (mktme_status != MKTME_UNINITIALIZED) {
701 if (tme_activate != tme_activate_cpu0) {
702 /* Broken BIOS? */
703 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
704 pr_err_once("x86/tme: MKTME is not usable\n");
705 mktme_status = MKTME_DISABLED;
706
707 /* Proceed. We may need to exclude bits from x86_phys_bits. */
708 }
709 } else {
710 tme_activate_cpu0 = tme_activate;
711 }
712
713 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
714 pr_info_once("x86/tme: not enabled by BIOS\n");
715 mktme_status = MKTME_DISABLED;
716 return;
717 }
718
719 if (mktme_status != MKTME_UNINITIALIZED)
720 goto detect_keyid_bits;
721
722 pr_info("x86/tme: enabled by BIOS\n");
723
724 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
725 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
726 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
727
728 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
729 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
730 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
731 tme_crypto_algs);
732 mktme_status = MKTME_DISABLED;
733 }
734detect_keyid_bits:
735 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
736 nr_keyids = (1UL << keyid_bits) - 1;
737 if (nr_keyids) {
738 pr_info_once("x86/mktme: enabled by BIOS\n");
739 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
740 } else {
741 pr_info_once("x86/mktme: disabled by BIOS\n");
742 }
743
744 if (mktme_status == MKTME_UNINITIALIZED) {
745 /* MKTME is usable */
746 mktme_status = MKTME_ENABLED;
747 }
748
749 /*
750 * KeyID bits effectively lower the number of physical address
751 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
752 */
753 c->x86_phys_bits -= keyid_bits;
754}
755
756static void init_cpuid_fault(struct cpuinfo_x86 *c)
757{
758 u64 msr;
759
760 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
761 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
762 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
763 }
764}
765
766static void init_intel_misc_features(struct cpuinfo_x86 *c)
767{
768 u64 msr;
769
770 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
771 return;
772
773 /* Clear all MISC features */
774 this_cpu_write(msr_misc_features_shadow, 0);
775
776 /* Check features and update capabilities and shadow control bits */
777 init_cpuid_fault(c);
778 probe_xeon_phi_r3mwait(c);
779
780 msr = this_cpu_read(msr_misc_features_shadow);
781 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
782}
783
784static void split_lock_init(void);
785static void bus_lock_init(void);
786
787static void init_intel(struct cpuinfo_x86 *c)
788{
789 early_init_intel(c);
790
791 intel_workarounds(c);
792
793 /*
794 * Detect the extended topology information if available. This
795 * will reinitialise the initial_apicid which will be used
796 * in init_intel_cacheinfo()
797 */
798 detect_extended_topology(c);
799
800 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
801 /*
802 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
803 * detection.
804 */
805 detect_num_cpu_cores(c);
806#ifdef CONFIG_X86_32
807 detect_ht(c);
808#endif
809 }
810
811 init_intel_cacheinfo(c);
812
813 if (c->cpuid_level > 9) {
814 unsigned eax = cpuid_eax(10);
815 /* Check for version and the number of counters */
816 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
817 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
818 }
819
820 if (cpu_has(c, X86_FEATURE_XMM2))
821 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
822
823 if (boot_cpu_has(X86_FEATURE_DS)) {
824 unsigned int l1, l2;
825
826 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
827 if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
828 set_cpu_cap(c, X86_FEATURE_BTS);
829 if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
830 set_cpu_cap(c, X86_FEATURE_PEBS);
831 }
832
833 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
834 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
835 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
836
837 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
838 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
839 set_cpu_bug(c, X86_BUG_MONITOR);
840
841#ifdef CONFIG_X86_64
842 if (c->x86 == 15)
843 c->x86_cache_alignment = c->x86_clflush_size * 2;
844 if (c->x86 == 6)
845 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
846#else
847 /*
848 * Names for the Pentium II/Celeron processors
849 * detectable only by also checking the cache size.
850 * Dixon is NOT a Celeron.
851 */
852 if (c->x86 == 6) {
853 unsigned int l2 = c->x86_cache_size;
854 char *p = NULL;
855
856 switch (c->x86_model) {
857 case 5:
858 if (l2 == 0)
859 p = "Celeron (Covington)";
860 else if (l2 == 256)
861 p = "Mobile Pentium II (Dixon)";
862 break;
863
864 case 6:
865 if (l2 == 128)
866 p = "Celeron (Mendocino)";
867 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
868 p = "Celeron-A";
869 break;
870
871 case 8:
872 if (l2 == 128)
873 p = "Celeron (Coppermine)";
874 break;
875 }
876
877 if (p)
878 strcpy(c->x86_model_id, p);
879 }
880
881 if (c->x86 == 15)
882 set_cpu_cap(c, X86_FEATURE_P4);
883 if (c->x86 == 6)
884 set_cpu_cap(c, X86_FEATURE_P3);
885#endif
886
887 /* Work around errata */
888 srat_detect_node(c);
889
890 init_ia32_feat_ctl(c);
891
892 if (cpu_has(c, X86_FEATURE_TME))
893 detect_tme(c);
894
895 init_intel_misc_features(c);
896
897 split_lock_init();
898 bus_lock_init();
899
900 intel_init_thermal(c);
901}
902
903#ifdef CONFIG_X86_32
904static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
905{
906 /*
907 * Intel PIII Tualatin. This comes in two flavours.
908 * One has 256kb of cache, the other 512. We have no way
909 * to determine which, so we use a boottime override
910 * for the 512kb model, and assume 256 otherwise.
911 */
912 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
913 size = 256;
914
915 /*
916 * Intel Quark SoC X1000 contains a 4-way set associative
917 * 16K cache with a 16 byte cache line and 256 lines per tag
918 */
919 if ((c->x86 == 5) && (c->x86_model == 9))
920 size = 16;
921 return size;
922}
923#endif
924
925#define TLB_INST_4K 0x01
926#define TLB_INST_4M 0x02
927#define TLB_INST_2M_4M 0x03
928
929#define TLB_INST_ALL 0x05
930#define TLB_INST_1G 0x06
931
932#define TLB_DATA_4K 0x11
933#define TLB_DATA_4M 0x12
934#define TLB_DATA_2M_4M 0x13
935#define TLB_DATA_4K_4M 0x14
936
937#define TLB_DATA_1G 0x16
938
939#define TLB_DATA0_4K 0x21
940#define TLB_DATA0_4M 0x22
941#define TLB_DATA0_2M_4M 0x23
942
943#define STLB_4K 0x41
944#define STLB_4K_2M 0x42
945
946static const struct _tlb_table intel_tlb_table[] = {
947 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
948 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
949 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
950 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
951 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
952 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
953 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
954 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
955 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
956 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
957 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
958 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
959 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
960 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
961 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
962 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
963 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
964 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
965 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
966 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
967 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
968 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
969 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
970 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
971 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
972 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
973 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
974 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
975 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
976 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
977 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
978 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
979 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
980 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
981 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
982 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
983 { 0x00, 0, 0 }
984};
985
986static void intel_tlb_lookup(const unsigned char desc)
987{
988 unsigned char k;
989 if (desc == 0)
990 return;
991
992 /* look up this descriptor in the table */
993 for (k = 0; intel_tlb_table[k].descriptor != desc &&
994 intel_tlb_table[k].descriptor != 0; k++)
995 ;
996
997 if (intel_tlb_table[k].tlb_type == 0)
998 return;
999
1000 switch (intel_tlb_table[k].tlb_type) {
1001 case STLB_4K:
1002 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
1003 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
1004 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
1005 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
1006 break;
1007 case STLB_4K_2M:
1008 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
1009 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
1010 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
1011 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
1012 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
1013 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
1014 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
1015 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
1016 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
1017 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
1018 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
1019 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
1020 break;
1021 case TLB_INST_ALL:
1022 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
1023 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
1024 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
1025 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
1026 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
1027 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
1028 break;
1029 case TLB_INST_4K:
1030 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
1031 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
1032 break;
1033 case TLB_INST_4M:
1034 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
1035 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
1036 break;
1037 case TLB_INST_2M_4M:
1038 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
1039 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
1040 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
1041 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
1042 break;
1043 case TLB_DATA_4K:
1044 case TLB_DATA0_4K:
1045 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
1046 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
1047 break;
1048 case TLB_DATA_4M:
1049 case TLB_DATA0_4M:
1050 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
1051 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
1052 break;
1053 case TLB_DATA_2M_4M:
1054 case TLB_DATA0_2M_4M:
1055 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
1056 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
1057 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
1058 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
1059 break;
1060 case TLB_DATA_4K_4M:
1061 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
1062 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
1063 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
1064 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
1065 break;
1066 case TLB_DATA_1G:
1067 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
1068 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
1069 break;
1070 }
1071}
1072
1073static void intel_detect_tlb(struct cpuinfo_x86 *c)
1074{
1075 int i, j, n;
1076 unsigned int regs[4];
1077 unsigned char *desc = (unsigned char *)regs;
1078
1079 if (c->cpuid_level < 2)
1080 return;
1081
1082 /* Number of times to iterate */
1083 n = cpuid_eax(2) & 0xFF;
1084
1085 for (i = 0 ; i < n ; i++) {
1086 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
1087
1088 /* If bit 31 is set, this is an unknown format */
1089 for (j = 0 ; j < 3 ; j++)
1090 if (regs[j] & (1 << 31))
1091 regs[j] = 0;
1092
1093 /* Byte 0 is level count, not a descriptor */
1094 for (j = 1 ; j < 16 ; j++)
1095 intel_tlb_lookup(desc[j]);
1096 }
1097}
1098
1099static const struct cpu_dev intel_cpu_dev = {
1100 .c_vendor = "Intel",
1101 .c_ident = { "GenuineIntel" },
1102#ifdef CONFIG_X86_32
1103 .legacy_models = {
1104 { .family = 4, .model_names =
1105 {
1106 [0] = "486 DX-25/33",
1107 [1] = "486 DX-50",
1108 [2] = "486 SX",
1109 [3] = "486 DX/2",
1110 [4] = "486 SL",
1111 [5] = "486 SX/2",
1112 [7] = "486 DX/2-WB",
1113 [8] = "486 DX/4",
1114 [9] = "486 DX/4-WB"
1115 }
1116 },
1117 { .family = 5, .model_names =
1118 {
1119 [0] = "Pentium 60/66 A-step",
1120 [1] = "Pentium 60/66",
1121 [2] = "Pentium 75 - 200",
1122 [3] = "OverDrive PODP5V83",
1123 [4] = "Pentium MMX",
1124 [7] = "Mobile Pentium 75 - 200",
1125 [8] = "Mobile Pentium MMX",
1126 [9] = "Quark SoC X1000",
1127 }
1128 },
1129 { .family = 6, .model_names =
1130 {
1131 [0] = "Pentium Pro A-step",
1132 [1] = "Pentium Pro",
1133 [3] = "Pentium II (Klamath)",
1134 [4] = "Pentium II (Deschutes)",
1135 [5] = "Pentium II (Deschutes)",
1136 [6] = "Mobile Pentium II",
1137 [7] = "Pentium III (Katmai)",
1138 [8] = "Pentium III (Coppermine)",
1139 [10] = "Pentium III (Cascades)",
1140 [11] = "Pentium III (Tualatin)",
1141 }
1142 },
1143 { .family = 15, .model_names =
1144 {
1145 [0] = "Pentium 4 (Unknown)",
1146 [1] = "Pentium 4 (Willamette)",
1147 [2] = "Pentium 4 (Northwood)",
1148 [4] = "Pentium 4 (Foster)",
1149 [5] = "Pentium 4 (Foster)",
1150 }
1151 },
1152 },
1153 .legacy_cache_size = intel_size_cache,
1154#endif
1155 .c_detect_tlb = intel_detect_tlb,
1156 .c_early_init = early_init_intel,
1157 .c_bsp_init = bsp_init_intel,
1158 .c_init = init_intel,
1159 .c_x86_vendor = X86_VENDOR_INTEL,
1160};
1161
1162cpu_dev_register(intel_cpu_dev);
1163
1164#undef pr_fmt
1165#define pr_fmt(fmt) "x86/split lock detection: " fmt
1166
1167static const struct {
1168 const char *option;
1169 enum split_lock_detect_state state;
1170} sld_options[] __initconst = {
1171 { "off", sld_off },
1172 { "warn", sld_warn },
1173 { "fatal", sld_fatal },
1174 { "ratelimit:", sld_ratelimit },
1175};
1176
1177static struct ratelimit_state bld_ratelimit;
1178
1179static unsigned int sysctl_sld_mitigate = 1;
1180static DEFINE_SEMAPHORE(buslock_sem);
1181
1182#ifdef CONFIG_PROC_SYSCTL
1183static struct ctl_table sld_sysctls[] = {
1184 {
1185 .procname = "split_lock_mitigate",
1186 .data = &sysctl_sld_mitigate,
1187 .maxlen = sizeof(unsigned int),
1188 .mode = 0644,
1189 .proc_handler = proc_douintvec_minmax,
1190 .extra1 = SYSCTL_ZERO,
1191 .extra2 = SYSCTL_ONE,
1192 },
1193 {}
1194};
1195
1196static int __init sld_mitigate_sysctl_init(void)
1197{
1198 register_sysctl_init("kernel", sld_sysctls);
1199 return 0;
1200}
1201
1202late_initcall(sld_mitigate_sysctl_init);
1203#endif
1204
1205static inline bool match_option(const char *arg, int arglen, const char *opt)
1206{
1207 int len = strlen(opt), ratelimit;
1208
1209 if (strncmp(arg, opt, len))
1210 return false;
1211
1212 /*
1213 * Min ratelimit is 1 bus lock/sec.
1214 * Max ratelimit is 1000 bus locks/sec.
1215 */
1216 if (sscanf(arg, "ratelimit:%d", &ratelimit) == 1 &&
1217 ratelimit > 0 && ratelimit <= 1000) {
1218 ratelimit_state_init(&bld_ratelimit, HZ, ratelimit);
1219 ratelimit_set_flags(&bld_ratelimit, RATELIMIT_MSG_ON_RELEASE);
1220 return true;
1221 }
1222
1223 return len == arglen;
1224}
1225
1226static bool split_lock_verify_msr(bool on)
1227{
1228 u64 ctrl, tmp;
1229
1230 if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl))
1231 return false;
1232 if (on)
1233 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1234 else
1235 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1236 if (wrmsrl_safe(MSR_TEST_CTRL, ctrl))
1237 return false;
1238 rdmsrl(MSR_TEST_CTRL, tmp);
1239 return ctrl == tmp;
1240}
1241
1242static void __init sld_state_setup(void)
1243{
1244 enum split_lock_detect_state state = sld_warn;
1245 char arg[20];
1246 int i, ret;
1247
1248 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1249 !boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1250 return;
1251
1252 ret = cmdline_find_option(boot_command_line, "split_lock_detect",
1253 arg, sizeof(arg));
1254 if (ret >= 0) {
1255 for (i = 0; i < ARRAY_SIZE(sld_options); i++) {
1256 if (match_option(arg, ret, sld_options[i].option)) {
1257 state = sld_options[i].state;
1258 break;
1259 }
1260 }
1261 }
1262 sld_state = state;
1263}
1264
1265static void __init __split_lock_setup(void)
1266{
1267 if (!split_lock_verify_msr(false)) {
1268 pr_info("MSR access failed: Disabled\n");
1269 return;
1270 }
1271
1272 rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1273
1274 if (!split_lock_verify_msr(true)) {
1275 pr_info("MSR access failed: Disabled\n");
1276 return;
1277 }
1278
1279 /* Restore the MSR to its cached value. */
1280 wrmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1281
1282 setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
1283}
1284
1285/*
1286 * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking
1287 * is not implemented as one thread could undo the setting of the other
1288 * thread immediately after dropping the lock anyway.
1289 */
1290static void sld_update_msr(bool on)
1291{
1292 u64 test_ctrl_val = msr_test_ctrl_cache;
1293
1294 if (on)
1295 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1296
1297 wrmsrl(MSR_TEST_CTRL, test_ctrl_val);
1298}
1299
1300static void split_lock_init(void)
1301{
1302 /*
1303 * #DB for bus lock handles ratelimit and #AC for split lock is
1304 * disabled.
1305 */
1306 if (sld_state == sld_ratelimit) {
1307 split_lock_verify_msr(false);
1308 return;
1309 }
1310
1311 if (cpu_model_supports_sld)
1312 split_lock_verify_msr(sld_state != sld_off);
1313}
1314
1315static void __split_lock_reenable_unlock(struct work_struct *work)
1316{
1317 sld_update_msr(true);
1318 up(&buslock_sem);
1319}
1320
1321static DECLARE_DELAYED_WORK(sl_reenable_unlock, __split_lock_reenable_unlock);
1322
1323static void __split_lock_reenable(struct work_struct *work)
1324{
1325 sld_update_msr(true);
1326}
1327static DECLARE_DELAYED_WORK(sl_reenable, __split_lock_reenable);
1328
1329/*
1330 * If a CPU goes offline with pending delayed work to re-enable split lock
1331 * detection then the delayed work will be executed on some other CPU. That
1332 * handles releasing the buslock_sem, but because it executes on a
1333 * different CPU probably won't re-enable split lock detection. This is a
1334 * problem on HT systems since the sibling CPU on the same core may then be
1335 * left running with split lock detection disabled.
1336 *
1337 * Unconditionally re-enable detection here.
1338 */
1339static int splitlock_cpu_offline(unsigned int cpu)
1340{
1341 sld_update_msr(true);
1342
1343 return 0;
1344}
1345
1346static void split_lock_warn(unsigned long ip)
1347{
1348 struct delayed_work *work;
1349 int cpu;
1350
1351 if (!current->reported_split_lock)
1352 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n",
1353 current->comm, current->pid, ip);
1354 current->reported_split_lock = 1;
1355
1356 if (sysctl_sld_mitigate) {
1357 /*
1358 * misery factor #1:
1359 * sleep 10ms before trying to execute split lock.
1360 */
1361 if (msleep_interruptible(10) > 0)
1362 return;
1363 /*
1364 * Misery factor #2:
1365 * only allow one buslocked disabled core at a time.
1366 */
1367 if (down_interruptible(&buslock_sem) == -EINTR)
1368 return;
1369 work = &sl_reenable_unlock;
1370 } else {
1371 work = &sl_reenable;
1372 }
1373
1374 cpu = get_cpu();
1375 schedule_delayed_work_on(cpu, work, 2);
1376
1377 /* Disable split lock detection on this CPU to make progress */
1378 sld_update_msr(false);
1379 put_cpu();
1380}
1381
1382bool handle_guest_split_lock(unsigned long ip)
1383{
1384 if (sld_state == sld_warn) {
1385 split_lock_warn(ip);
1386 return true;
1387 }
1388
1389 pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n",
1390 current->comm, current->pid,
1391 sld_state == sld_fatal ? "fatal" : "bogus", ip);
1392
1393 current->thread.error_code = 0;
1394 current->thread.trap_nr = X86_TRAP_AC;
1395 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1396 return false;
1397}
1398EXPORT_SYMBOL_GPL(handle_guest_split_lock);
1399
1400static void bus_lock_init(void)
1401{
1402 u64 val;
1403
1404 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1405 return;
1406
1407 rdmsrl(MSR_IA32_DEBUGCTLMSR, val);
1408
1409 if ((boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1410 (sld_state == sld_warn || sld_state == sld_fatal)) ||
1411 sld_state == sld_off) {
1412 /*
1413 * Warn and fatal are handled by #AC for split lock if #AC for
1414 * split lock is supported.
1415 */
1416 val &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1417 } else {
1418 val |= DEBUGCTLMSR_BUS_LOCK_DETECT;
1419 }
1420
1421 wrmsrl(MSR_IA32_DEBUGCTLMSR, val);
1422}
1423
1424bool handle_user_split_lock(struct pt_regs *regs, long error_code)
1425{
1426 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)
1427 return false;
1428 split_lock_warn(regs->ip);
1429 return true;
1430}
1431
1432void handle_bus_lock(struct pt_regs *regs)
1433{
1434 switch (sld_state) {
1435 case sld_off:
1436 break;
1437 case sld_ratelimit:
1438 /* Enforce no more than bld_ratelimit bus locks/sec. */
1439 while (!__ratelimit(&bld_ratelimit))
1440 msleep(20);
1441 /* Warn on the bus lock. */
1442 fallthrough;
1443 case sld_warn:
1444 pr_warn_ratelimited("#DB: %s/%d took a bus_lock trap at address: 0x%lx\n",
1445 current->comm, current->pid, regs->ip);
1446 break;
1447 case sld_fatal:
1448 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1449 break;
1450 }
1451}
1452
1453/*
1454 * Bits in the IA32_CORE_CAPABILITIES are not architectural, so they should
1455 * only be trusted if it is confirmed that a CPU model implements a
1456 * specific feature at a particular bit position.
1457 *
1458 * The possible driver data field values:
1459 *
1460 * - 0: CPU models that are known to have the per-core split-lock detection
1461 * feature even though they do not enumerate IA32_CORE_CAPABILITIES.
1462 *
1463 * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use
1464 * bit 5 to enumerate the per-core split-lock detection feature.
1465 */
1466static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
1467 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0),
1468 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0),
1469 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0),
1470 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, 1),
1471 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, 1),
1472 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, 1),
1473 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, 1),
1474 X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, 1),
1475 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 1),
1476 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 1),
1477 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 1),
1478 X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, 1),
1479 {}
1480};
1481
1482static void __init split_lock_setup(struct cpuinfo_x86 *c)
1483{
1484 const struct x86_cpu_id *m;
1485 u64 ia32_core_caps;
1486
1487 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1488 return;
1489
1490 m = x86_match_cpu(split_lock_cpu_ids);
1491 if (!m)
1492 return;
1493
1494 switch (m->driver_data) {
1495 case 0:
1496 break;
1497 case 1:
1498 if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))
1499 return;
1500 rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
1501 if (!(ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT))
1502 return;
1503 break;
1504 default:
1505 return;
1506 }
1507
1508 cpu_model_supports_sld = true;
1509 __split_lock_setup();
1510}
1511
1512static void sld_state_show(void)
1513{
1514 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) &&
1515 !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
1516 return;
1517
1518 switch (sld_state) {
1519 case sld_off:
1520 pr_info("disabled\n");
1521 break;
1522 case sld_warn:
1523 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1524 pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");
1525 if (cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
1526 "x86/splitlock", NULL, splitlock_cpu_offline) < 0)
1527 pr_warn("No splitlock CPU offline handler\n");
1528 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1529 pr_info("#DB: warning on user-space bus_locks\n");
1530 }
1531 break;
1532 case sld_fatal:
1533 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1534 pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n");
1535 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1536 pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",
1537 boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) ?
1538 " from non-WB" : "");
1539 }
1540 break;
1541 case sld_ratelimit:
1542 if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1543 pr_info("#DB: setting system wide bus lock rate limit to %u/sec\n", bld_ratelimit.burst);
1544 break;
1545 }
1546}
1547
1548void __init sld_setup(struct cpuinfo_x86 *c)
1549{
1550 split_lock_setup(c);
1551 sld_state_setup();
1552 sld_state_show();
1553}
1554
1555#define X86_HYBRID_CPU_TYPE_ID_SHIFT 24
1556
1557/**
1558 * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU
1559 *
1560 * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in
1561 * a hybrid processor. If the processor is not hybrid, returns 0.
1562 */
1563u8 get_this_hybrid_cpu_type(void)
1564{
1565 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
1566 return 0;
1567
1568 return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT;
1569}
1// SPDX-License-Identifier: GPL-2.0
2#include <linux/kernel.h>
3
4#include <linux/string.h>
5#include <linux/bitops.h>
6#include <linux/smp.h>
7#include <linux/sched.h>
8#include <linux/sched/clock.h>
9#include <linux/thread_info.h>
10#include <linux/init.h>
11#include <linux/uaccess.h>
12
13#include <asm/cpufeature.h>
14#include <asm/pgtable.h>
15#include <asm/msr.h>
16#include <asm/bugs.h>
17#include <asm/cpu.h>
18#include <asm/intel-family.h>
19#include <asm/microcode_intel.h>
20#include <asm/hwcap2.h>
21#include <asm/elf.h>
22
23#ifdef CONFIG_X86_64
24#include <linux/topology.h>
25#endif
26
27#include "cpu.h"
28
29#ifdef CONFIG_X86_LOCAL_APIC
30#include <asm/mpspec.h>
31#include <asm/apic.h>
32#endif
33
34/*
35 * Just in case our CPU detection goes bad, or you have a weird system,
36 * allow a way to override the automatic disabling of MPX.
37 */
38static int forcempx;
39
40static int __init forcempx_setup(char *__unused)
41{
42 forcempx = 1;
43
44 return 1;
45}
46__setup("intel-skd-046-workaround=disable", forcempx_setup);
47
48void check_mpx_erratum(struct cpuinfo_x86 *c)
49{
50 if (forcempx)
51 return;
52 /*
53 * Turn off the MPX feature on CPUs where SMEP is not
54 * available or disabled.
55 *
56 * Works around Intel Erratum SKD046: "Branch Instructions
57 * May Initialize MPX Bound Registers Incorrectly".
58 *
59 * This might falsely disable MPX on systems without
60 * SMEP, like Atom processors without SMEP. But there
61 * is no such hardware known at the moment.
62 */
63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
64 setup_clear_cpu_cap(X86_FEATURE_MPX);
65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
66 }
67}
68
69static bool ring3mwait_disabled __read_mostly;
70
71static int __init ring3mwait_disable(char *__unused)
72{
73 ring3mwait_disabled = true;
74 return 0;
75}
76__setup("ring3mwait=disable", ring3mwait_disable);
77
78static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
79{
80 /*
81 * Ring 3 MONITOR/MWAIT feature cannot be detected without
82 * cpu model and family comparison.
83 */
84 if (c->x86 != 6)
85 return;
86 switch (c->x86_model) {
87 case INTEL_FAM6_XEON_PHI_KNL:
88 case INTEL_FAM6_XEON_PHI_KNM:
89 break;
90 default:
91 return;
92 }
93
94 if (ring3mwait_disabled)
95 return;
96
97 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
98 this_cpu_or(msr_misc_features_shadow,
99 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
100
101 if (c == &boot_cpu_data)
102 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
103}
104
105/*
106 * Early microcode releases for the Spectre v2 mitigation were broken.
107 * Information taken from;
108 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
109 * - https://kb.vmware.com/s/article/52345
110 * - Microcode revisions observed in the wild
111 * - Release note from 20180108 microcode release
112 */
113struct sku_microcode {
114 u8 model;
115 u8 stepping;
116 u32 microcode;
117};
118static const struct sku_microcode spectre_bad_microcodes[] = {
119 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0B, 0x80 },
120 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0A, 0x80 },
121 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x09, 0x80 },
122 { INTEL_FAM6_KABYLAKE_MOBILE, 0x0A, 0x80 },
123 { INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 },
124 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
125 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
126 { INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 },
127 { INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x1b },
128 { INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 },
129 { INTEL_FAM6_BROADWELL_XEON_D, 0x03, 0x07000011 },
130 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
131 { INTEL_FAM6_HASWELL_ULT, 0x01, 0x21 },
132 { INTEL_FAM6_HASWELL_GT3E, 0x01, 0x18 },
133 { INTEL_FAM6_HASWELL_CORE, 0x03, 0x23 },
134 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
135 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
136 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
137 /* Observed in the wild */
138 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
139 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
140};
141
142static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
143{
144 int i;
145
146 /*
147 * We know that the hypervisor lie to us on the microcode version so
148 * we may as well hope that it is running the correct version.
149 */
150 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
151 return false;
152
153 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
154 if (c->x86_model == spectre_bad_microcodes[i].model &&
155 c->x86_stepping == spectre_bad_microcodes[i].stepping)
156 return (c->microcode <= spectre_bad_microcodes[i].microcode);
157 }
158 return false;
159}
160
161static void early_init_intel(struct cpuinfo_x86 *c)
162{
163 u64 misc_enable;
164
165 /* Unmask CPUID levels if masked: */
166 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
167 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
168 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
169 c->cpuid_level = cpuid_eax(0);
170 get_cpu_cap(c);
171 }
172 }
173
174 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
175 (c->x86 == 0x6 && c->x86_model >= 0x0e))
176 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
177
178 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
179 c->microcode = intel_get_microcode_revision();
180
181 /* Now if any of them are set, check the blacklist and clear the lot */
182 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
183 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
184 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
185 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
186 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
187 setup_clear_cpu_cap(X86_FEATURE_IBRS);
188 setup_clear_cpu_cap(X86_FEATURE_IBPB);
189 setup_clear_cpu_cap(X86_FEATURE_STIBP);
190 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
191 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
192 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
193 setup_clear_cpu_cap(X86_FEATURE_SSBD);
194 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
195 }
196
197 /*
198 * Atom erratum AAE44/AAF40/AAG38/AAH41:
199 *
200 * A race condition between speculative fetches and invalidating
201 * a large page. This is worked around in microcode, but we
202 * need the microcode to have already been loaded... so if it is
203 * not, recommend a BIOS update and disable large pages.
204 */
205 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
206 c->microcode < 0x20e) {
207 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
208 clear_cpu_cap(c, X86_FEATURE_PSE);
209 }
210
211#ifdef CONFIG_X86_64
212 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
213#else
214 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
215 if (c->x86 == 15 && c->x86_cache_alignment == 64)
216 c->x86_cache_alignment = 128;
217#endif
218
219 /* CPUID workaround for 0F33/0F34 CPU */
220 if (c->x86 == 0xF && c->x86_model == 0x3
221 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
222 c->x86_phys_bits = 36;
223
224 /*
225 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
226 * with P/T states and does not stop in deep C-states.
227 *
228 * It is also reliable across cores and sockets. (but not across
229 * cabinets - we turn it off in that case explicitly.)
230 */
231 if (c->x86_power & (1 << 8)) {
232 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
233 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
234 }
235
236 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
237 if (c->x86 == 6) {
238 switch (c->x86_model) {
239 case 0x27: /* Penwell */
240 case 0x35: /* Cloverview */
241 case 0x4a: /* Merrifield */
242 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
243 break;
244 default:
245 break;
246 }
247 }
248
249 /*
250 * There is a known erratum on Pentium III and Core Solo
251 * and Core Duo CPUs.
252 * " Page with PAT set to WC while associated MTRR is UC
253 * may consolidate to UC "
254 * Because of this erratum, it is better to stick with
255 * setting WC in MTRR rather than using PAT on these CPUs.
256 *
257 * Enable PAT WC only on P4, Core 2 or later CPUs.
258 */
259 if (c->x86 == 6 && c->x86_model < 15)
260 clear_cpu_cap(c, X86_FEATURE_PAT);
261
262 /*
263 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
264 * clear the fast string and enhanced fast string CPU capabilities.
265 */
266 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
267 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
268 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
269 pr_info("Disabled fast string operations\n");
270 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
271 setup_clear_cpu_cap(X86_FEATURE_ERMS);
272 }
273 }
274
275 /*
276 * Intel Quark Core DevMan_001.pdf section 6.4.11
277 * "The operating system also is required to invalidate (i.e., flush)
278 * the TLB when any changes are made to any of the page table entries.
279 * The operating system must reload CR3 to cause the TLB to be flushed"
280 *
281 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
282 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
283 * to be modified.
284 */
285 if (c->x86 == 5 && c->x86_model == 9) {
286 pr_info("Disabling PGE capability bit\n");
287 setup_clear_cpu_cap(X86_FEATURE_PGE);
288 }
289
290 if (c->cpuid_level >= 0x00000001) {
291 u32 eax, ebx, ecx, edx;
292
293 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
294 /*
295 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
296 * apicids which are reserved per package. Store the resulting
297 * shift value for the package management code.
298 */
299 if (edx & (1U << 28))
300 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
301 }
302
303 check_mpx_erratum(c);
304}
305
306#ifdef CONFIG_X86_32
307/*
308 * Early probe support logic for ppro memory erratum #50
309 *
310 * This is called before we do cpu ident work
311 */
312
313int ppro_with_ram_bug(void)
314{
315 /* Uses data from early_cpu_detect now */
316 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
317 boot_cpu_data.x86 == 6 &&
318 boot_cpu_data.x86_model == 1 &&
319 boot_cpu_data.x86_stepping < 8) {
320 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
321 return 1;
322 }
323 return 0;
324}
325
326static void intel_smp_check(struct cpuinfo_x86 *c)
327{
328 /* calling is from identify_secondary_cpu() ? */
329 if (!c->cpu_index)
330 return;
331
332 /*
333 * Mask B, Pentium, but not Pentium MMX
334 */
335 if (c->x86 == 5 &&
336 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
337 c->x86_model <= 3) {
338 /*
339 * Remember we have B step Pentia with bugs
340 */
341 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
342 "with B stepping processors.\n");
343 }
344}
345
346static int forcepae;
347static int __init forcepae_setup(char *__unused)
348{
349 forcepae = 1;
350 return 1;
351}
352__setup("forcepae", forcepae_setup);
353
354static void intel_workarounds(struct cpuinfo_x86 *c)
355{
356#ifdef CONFIG_X86_F00F_BUG
357 /*
358 * All models of Pentium and Pentium with MMX technology CPUs
359 * have the F0 0F bug, which lets nonprivileged users lock up the
360 * system. Announce that the fault handler will be checking for it.
361 * The Quark is also family 5, but does not have the same bug.
362 */
363 clear_cpu_bug(c, X86_BUG_F00F);
364 if (c->x86 == 5 && c->x86_model < 9) {
365 static int f00f_workaround_enabled;
366
367 set_cpu_bug(c, X86_BUG_F00F);
368 if (!f00f_workaround_enabled) {
369 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
370 f00f_workaround_enabled = 1;
371 }
372 }
373#endif
374
375 /*
376 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
377 * model 3 mask 3
378 */
379 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
380 clear_cpu_cap(c, X86_FEATURE_SEP);
381
382 /*
383 * PAE CPUID issue: many Pentium M report no PAE but may have a
384 * functionally usable PAE implementation.
385 * Forcefully enable PAE if kernel parameter "forcepae" is present.
386 */
387 if (forcepae) {
388 pr_warn("PAE forced!\n");
389 set_cpu_cap(c, X86_FEATURE_PAE);
390 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
391 }
392
393 /*
394 * P4 Xeon erratum 037 workaround.
395 * Hardware prefetcher may cause stale data to be loaded into the cache.
396 */
397 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
398 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
399 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
400 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
401 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
402 }
403 }
404
405 /*
406 * See if we have a good local APIC by checking for buggy Pentia,
407 * i.e. all B steppings and the C2 stepping of P54C when using their
408 * integrated APIC (see 11AP erratum in "Pentium Processor
409 * Specification Update").
410 */
411 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
412 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
413 set_cpu_bug(c, X86_BUG_11AP);
414
415
416#ifdef CONFIG_X86_INTEL_USERCOPY
417 /*
418 * Set up the preferred alignment for movsl bulk memory moves
419 */
420 switch (c->x86) {
421 case 4: /* 486: untested */
422 break;
423 case 5: /* Old Pentia: untested */
424 break;
425 case 6: /* PII/PIII only like movsl with 8-byte alignment */
426 movsl_mask.mask = 7;
427 break;
428 case 15: /* P4 is OK down to 8-byte alignment */
429 movsl_mask.mask = 7;
430 break;
431 }
432#endif
433
434 intel_smp_check(c);
435}
436#else
437static void intel_workarounds(struct cpuinfo_x86 *c)
438{
439}
440#endif
441
442static void srat_detect_node(struct cpuinfo_x86 *c)
443{
444#ifdef CONFIG_NUMA
445 unsigned node;
446 int cpu = smp_processor_id();
447
448 /* Don't do the funky fallback heuristics the AMD version employs
449 for now. */
450 node = numa_cpu_node(cpu);
451 if (node == NUMA_NO_NODE || !node_online(node)) {
452 /* reuse the value from init_cpu_to_node() */
453 node = cpu_to_node(cpu);
454 }
455 numa_set_node(cpu, node);
456#endif
457}
458
459/*
460 * find out the number of processor cores on the die
461 */
462static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
463{
464 unsigned int eax, ebx, ecx, edx;
465
466 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
467 return 1;
468
469 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
470 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
471 if (eax & 0x1f)
472 return (eax >> 26) + 1;
473 else
474 return 1;
475}
476
477static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
478{
479 /* Intel VMX MSR indicated features */
480#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
481#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
482#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
483#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
484#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
485#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
486
487 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
488
489 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
490 clear_cpu_cap(c, X86_FEATURE_VNMI);
491 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
492 clear_cpu_cap(c, X86_FEATURE_EPT);
493 clear_cpu_cap(c, X86_FEATURE_VPID);
494
495 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
496 msr_ctl = vmx_msr_high | vmx_msr_low;
497 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
498 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
499 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
500 set_cpu_cap(c, X86_FEATURE_VNMI);
501 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
502 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
503 vmx_msr_low, vmx_msr_high);
504 msr_ctl2 = vmx_msr_high | vmx_msr_low;
505 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
506 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
507 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
508 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
509 set_cpu_cap(c, X86_FEATURE_EPT);
510 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
511 set_cpu_cap(c, X86_FEATURE_VPID);
512 }
513}
514
515#define MSR_IA32_TME_ACTIVATE 0x982
516
517/* Helpers to access TME_ACTIVATE MSR */
518#define TME_ACTIVATE_LOCKED(x) (x & 0x1)
519#define TME_ACTIVATE_ENABLED(x) (x & 0x2)
520
521#define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
522#define TME_ACTIVATE_POLICY_AES_XTS_128 0
523
524#define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
525
526#define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
527#define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
528
529/* Values for mktme_status (SW only construct) */
530#define MKTME_ENABLED 0
531#define MKTME_DISABLED 1
532#define MKTME_UNINITIALIZED 2
533static int mktme_status = MKTME_UNINITIALIZED;
534
535static void detect_tme(struct cpuinfo_x86 *c)
536{
537 u64 tme_activate, tme_policy, tme_crypto_algs;
538 int keyid_bits = 0, nr_keyids = 0;
539 static u64 tme_activate_cpu0 = 0;
540
541 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
542
543 if (mktme_status != MKTME_UNINITIALIZED) {
544 if (tme_activate != tme_activate_cpu0) {
545 /* Broken BIOS? */
546 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
547 pr_err_once("x86/tme: MKTME is not usable\n");
548 mktme_status = MKTME_DISABLED;
549
550 /* Proceed. We may need to exclude bits from x86_phys_bits. */
551 }
552 } else {
553 tme_activate_cpu0 = tme_activate;
554 }
555
556 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
557 pr_info_once("x86/tme: not enabled by BIOS\n");
558 mktme_status = MKTME_DISABLED;
559 return;
560 }
561
562 if (mktme_status != MKTME_UNINITIALIZED)
563 goto detect_keyid_bits;
564
565 pr_info("x86/tme: enabled by BIOS\n");
566
567 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
568 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
569 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
570
571 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
572 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
573 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
574 tme_crypto_algs);
575 mktme_status = MKTME_DISABLED;
576 }
577detect_keyid_bits:
578 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
579 nr_keyids = (1UL << keyid_bits) - 1;
580 if (nr_keyids) {
581 pr_info_once("x86/mktme: enabled by BIOS\n");
582 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
583 } else {
584 pr_info_once("x86/mktme: disabled by BIOS\n");
585 }
586
587 if (mktme_status == MKTME_UNINITIALIZED) {
588 /* MKTME is usable */
589 mktme_status = MKTME_ENABLED;
590 }
591
592 /*
593 * KeyID bits effectively lower the number of physical address
594 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
595 */
596 c->x86_phys_bits -= keyid_bits;
597}
598
599static void init_intel_energy_perf(struct cpuinfo_x86 *c)
600{
601 u64 epb;
602
603 /*
604 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
605 * (x86_energy_perf_policy(8) is available to change it at run-time.)
606 */
607 if (!cpu_has(c, X86_FEATURE_EPB))
608 return;
609
610 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
611 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
612 return;
613
614 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
615 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
616 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
617 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
618}
619
620static void intel_bsp_resume(struct cpuinfo_x86 *c)
621{
622 /*
623 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
624 * so reinitialize it properly like during bootup:
625 */
626 init_intel_energy_perf(c);
627}
628
629static void init_cpuid_fault(struct cpuinfo_x86 *c)
630{
631 u64 msr;
632
633 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
634 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
635 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
636 }
637}
638
639static void init_intel_misc_features(struct cpuinfo_x86 *c)
640{
641 u64 msr;
642
643 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
644 return;
645
646 /* Clear all MISC features */
647 this_cpu_write(msr_misc_features_shadow, 0);
648
649 /* Check features and update capabilities and shadow control bits */
650 init_cpuid_fault(c);
651 probe_xeon_phi_r3mwait(c);
652
653 msr = this_cpu_read(msr_misc_features_shadow);
654 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
655}
656
657static void init_intel(struct cpuinfo_x86 *c)
658{
659 unsigned int l2 = 0;
660
661 early_init_intel(c);
662
663 intel_workarounds(c);
664
665 /*
666 * Detect the extended topology information if available. This
667 * will reinitialise the initial_apicid which will be used
668 * in init_intel_cacheinfo()
669 */
670 detect_extended_topology(c);
671
672 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
673 /*
674 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
675 * detection.
676 */
677 c->x86_max_cores = intel_num_cpu_cores(c);
678#ifdef CONFIG_X86_32
679 detect_ht(c);
680#endif
681 }
682
683 l2 = init_intel_cacheinfo(c);
684
685 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
686 if (l2 == 0) {
687 cpu_detect_cache_sizes(c);
688 l2 = c->x86_cache_size;
689 }
690
691 if (c->cpuid_level > 9) {
692 unsigned eax = cpuid_eax(10);
693 /* Check for version and the number of counters */
694 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
695 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
696 }
697
698 if (cpu_has(c, X86_FEATURE_XMM2))
699 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
700
701 if (boot_cpu_has(X86_FEATURE_DS)) {
702 unsigned int l1;
703 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
704 if (!(l1 & (1<<11)))
705 set_cpu_cap(c, X86_FEATURE_BTS);
706 if (!(l1 & (1<<12)))
707 set_cpu_cap(c, X86_FEATURE_PEBS);
708 }
709
710 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
711 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
712 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
713
714 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
715 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
716 set_cpu_bug(c, X86_BUG_MONITOR);
717
718#ifdef CONFIG_X86_64
719 if (c->x86 == 15)
720 c->x86_cache_alignment = c->x86_clflush_size * 2;
721 if (c->x86 == 6)
722 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
723#else
724 /*
725 * Names for the Pentium II/Celeron processors
726 * detectable only by also checking the cache size.
727 * Dixon is NOT a Celeron.
728 */
729 if (c->x86 == 6) {
730 char *p = NULL;
731
732 switch (c->x86_model) {
733 case 5:
734 if (l2 == 0)
735 p = "Celeron (Covington)";
736 else if (l2 == 256)
737 p = "Mobile Pentium II (Dixon)";
738 break;
739
740 case 6:
741 if (l2 == 128)
742 p = "Celeron (Mendocino)";
743 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
744 p = "Celeron-A";
745 break;
746
747 case 8:
748 if (l2 == 128)
749 p = "Celeron (Coppermine)";
750 break;
751 }
752
753 if (p)
754 strcpy(c->x86_model_id, p);
755 }
756
757 if (c->x86 == 15)
758 set_cpu_cap(c, X86_FEATURE_P4);
759 if (c->x86 == 6)
760 set_cpu_cap(c, X86_FEATURE_P3);
761#endif
762
763 /* Work around errata */
764 srat_detect_node(c);
765
766 if (cpu_has(c, X86_FEATURE_VMX))
767 detect_vmx_virtcap(c);
768
769 if (cpu_has(c, X86_FEATURE_TME))
770 detect_tme(c);
771
772 init_intel_energy_perf(c);
773
774 init_intel_misc_features(c);
775}
776
777#ifdef CONFIG_X86_32
778static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
779{
780 /*
781 * Intel PIII Tualatin. This comes in two flavours.
782 * One has 256kb of cache, the other 512. We have no way
783 * to determine which, so we use a boottime override
784 * for the 512kb model, and assume 256 otherwise.
785 */
786 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
787 size = 256;
788
789 /*
790 * Intel Quark SoC X1000 contains a 4-way set associative
791 * 16K cache with a 16 byte cache line and 256 lines per tag
792 */
793 if ((c->x86 == 5) && (c->x86_model == 9))
794 size = 16;
795 return size;
796}
797#endif
798
799#define TLB_INST_4K 0x01
800#define TLB_INST_4M 0x02
801#define TLB_INST_2M_4M 0x03
802
803#define TLB_INST_ALL 0x05
804#define TLB_INST_1G 0x06
805
806#define TLB_DATA_4K 0x11
807#define TLB_DATA_4M 0x12
808#define TLB_DATA_2M_4M 0x13
809#define TLB_DATA_4K_4M 0x14
810
811#define TLB_DATA_1G 0x16
812
813#define TLB_DATA0_4K 0x21
814#define TLB_DATA0_4M 0x22
815#define TLB_DATA0_2M_4M 0x23
816
817#define STLB_4K 0x41
818#define STLB_4K_2M 0x42
819
820static const struct _tlb_table intel_tlb_table[] = {
821 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
822 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
823 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
824 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
825 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
826 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
827 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
828 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
829 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
830 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
831 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
832 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
833 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
834 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
835 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
836 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
837 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
838 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
839 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
840 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
841 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
842 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
843 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
844 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
845 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
846 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
847 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
848 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
849 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
850 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
851 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
852 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
853 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
854 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
855 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
856 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
857 { 0x00, 0, 0 }
858};
859
860static void intel_tlb_lookup(const unsigned char desc)
861{
862 unsigned char k;
863 if (desc == 0)
864 return;
865
866 /* look up this descriptor in the table */
867 for (k = 0; intel_tlb_table[k].descriptor != desc && \
868 intel_tlb_table[k].descriptor != 0; k++)
869 ;
870
871 if (intel_tlb_table[k].tlb_type == 0)
872 return;
873
874 switch (intel_tlb_table[k].tlb_type) {
875 case STLB_4K:
876 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
877 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
878 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
879 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
880 break;
881 case STLB_4K_2M:
882 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
883 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
884 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
885 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
886 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
887 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
888 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
889 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
890 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
891 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
892 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
893 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
894 break;
895 case TLB_INST_ALL:
896 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
897 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
898 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
899 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
900 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
901 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
902 break;
903 case TLB_INST_4K:
904 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
905 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
906 break;
907 case TLB_INST_4M:
908 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
909 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
910 break;
911 case TLB_INST_2M_4M:
912 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
913 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
914 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
915 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
916 break;
917 case TLB_DATA_4K:
918 case TLB_DATA0_4K:
919 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
920 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
921 break;
922 case TLB_DATA_4M:
923 case TLB_DATA0_4M:
924 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
925 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
926 break;
927 case TLB_DATA_2M_4M:
928 case TLB_DATA0_2M_4M:
929 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
930 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
931 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
932 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
933 break;
934 case TLB_DATA_4K_4M:
935 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
936 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
937 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
938 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
939 break;
940 case TLB_DATA_1G:
941 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
942 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
943 break;
944 }
945}
946
947static void intel_detect_tlb(struct cpuinfo_x86 *c)
948{
949 int i, j, n;
950 unsigned int regs[4];
951 unsigned char *desc = (unsigned char *)regs;
952
953 if (c->cpuid_level < 2)
954 return;
955
956 /* Number of times to iterate */
957 n = cpuid_eax(2) & 0xFF;
958
959 for (i = 0 ; i < n ; i++) {
960 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
961
962 /* If bit 31 is set, this is an unknown format */
963 for (j = 0 ; j < 3 ; j++)
964 if (regs[j] & (1 << 31))
965 regs[j] = 0;
966
967 /* Byte 0 is level count, not a descriptor */
968 for (j = 1 ; j < 16 ; j++)
969 intel_tlb_lookup(desc[j]);
970 }
971}
972
973static const struct cpu_dev intel_cpu_dev = {
974 .c_vendor = "Intel",
975 .c_ident = { "GenuineIntel" },
976#ifdef CONFIG_X86_32
977 .legacy_models = {
978 { .family = 4, .model_names =
979 {
980 [0] = "486 DX-25/33",
981 [1] = "486 DX-50",
982 [2] = "486 SX",
983 [3] = "486 DX/2",
984 [4] = "486 SL",
985 [5] = "486 SX/2",
986 [7] = "486 DX/2-WB",
987 [8] = "486 DX/4",
988 [9] = "486 DX/4-WB"
989 }
990 },
991 { .family = 5, .model_names =
992 {
993 [0] = "Pentium 60/66 A-step",
994 [1] = "Pentium 60/66",
995 [2] = "Pentium 75 - 200",
996 [3] = "OverDrive PODP5V83",
997 [4] = "Pentium MMX",
998 [7] = "Mobile Pentium 75 - 200",
999 [8] = "Mobile Pentium MMX",
1000 [9] = "Quark SoC X1000",
1001 }
1002 },
1003 { .family = 6, .model_names =
1004 {
1005 [0] = "Pentium Pro A-step",
1006 [1] = "Pentium Pro",
1007 [3] = "Pentium II (Klamath)",
1008 [4] = "Pentium II (Deschutes)",
1009 [5] = "Pentium II (Deschutes)",
1010 [6] = "Mobile Pentium II",
1011 [7] = "Pentium III (Katmai)",
1012 [8] = "Pentium III (Coppermine)",
1013 [10] = "Pentium III (Cascades)",
1014 [11] = "Pentium III (Tualatin)",
1015 }
1016 },
1017 { .family = 15, .model_names =
1018 {
1019 [0] = "Pentium 4 (Unknown)",
1020 [1] = "Pentium 4 (Willamette)",
1021 [2] = "Pentium 4 (Northwood)",
1022 [4] = "Pentium 4 (Foster)",
1023 [5] = "Pentium 4 (Foster)",
1024 }
1025 },
1026 },
1027 .legacy_cache_size = intel_size_cache,
1028#endif
1029 .c_detect_tlb = intel_detect_tlb,
1030 .c_early_init = early_init_intel,
1031 .c_init = init_intel,
1032 .c_bsp_resume = intel_bsp_resume,
1033 .c_x86_vendor = X86_VENDOR_INTEL,
1034};
1035
1036cpu_dev_register(intel_cpu_dev);
1037