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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * include/asm/processor.h
4 *
5 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#ifndef __ASM_SPARC64_PROCESSOR_H
9#define __ASM_SPARC64_PROCESSOR_H
10
11#include <asm/asi.h>
12#include <asm/pstate.h>
13#include <asm/ptrace.h>
14#include <asm/page.h>
15
16/*
17 * User lives in his very own context, and cannot reference us. Note
18 * that TASK_SIZE is a misnomer, it really gives maximum user virtual
19 * address that the kernel will allocate out.
20 *
21 * XXX No longer using virtual page tables, kill this upper limit...
22 */
23#define VA_BITS 44
24#ifndef __ASSEMBLY__
25#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
26#else
27#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
28#endif
29
30#define TASK_SIZE_OF(tsk) \
31 (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
32 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
33#define TASK_SIZE \
34 (test_thread_flag(TIF_32BIT) ? \
35 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
36#ifdef __KERNEL__
37
38#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
39#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
40
41#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
42 STACK_TOP32 : STACK_TOP64)
43
44#define STACK_TOP_MAX STACK_TOP64
45
46#endif
47
48#ifndef __ASSEMBLY__
49
50/* The Sparc processor specific thread struct. */
51/* XXX This should die, everything can go into thread_info now. */
52struct thread_struct {
53#ifdef CONFIG_DEBUG_SPINLOCK
54 /* How many spinlocks held by this thread.
55 * Used with spin lock debugging to catch tasks
56 * sleeping illegally with locks held.
57 */
58 int smp_lock_count;
59 unsigned int smp_lock_pc;
60#else
61 int dummy; /* f'in gcc bug... */
62#endif
63};
64
65#endif /* !(__ASSEMBLY__) */
66
67#ifndef CONFIG_DEBUG_SPINLOCK
68#define INIT_THREAD { \
69 0, \
70}
71#else /* CONFIG_DEBUG_SPINLOCK */
72#define INIT_THREAD { \
73/* smp_lock_count, smp_lock_pc, */ \
74 0, 0, \
75}
76#endif /* !(CONFIG_DEBUG_SPINLOCK) */
77
78#ifndef __ASSEMBLY__
79
80#include <linux/types.h>
81#include <asm/fpumacro.h>
82
83struct task_struct;
84
85/* On Uniprocessor, even in RMO processes see TSO semantics */
86#ifdef CONFIG_SMP
87#define TSTATE_INITIAL_MM TSTATE_TSO
88#else
89#define TSTATE_INITIAL_MM TSTATE_RMO
90#endif
91
92/* Do necessary setup to start up a newly executed thread. */
93#define start_thread(regs, pc, sp) \
94do { \
95 unsigned long __asi = ASI_PNF; \
96 regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
97 regs->tpc = ((pc & (~3)) - 4); \
98 regs->tnpc = regs->tpc + 4; \
99 regs->y = 0; \
100 set_thread_wstate(1 << 3); \
101 if (current_thread_info()->utraps) { \
102 if (*(current_thread_info()->utraps) < 2) \
103 kfree(current_thread_info()->utraps); \
104 else \
105 (*(current_thread_info()->utraps))--; \
106 current_thread_info()->utraps = NULL; \
107 } \
108 __asm__ __volatile__( \
109 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
110 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
111 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
112 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
113 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
114 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
115 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
116 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
117 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
118 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
119 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
120 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
121 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
122 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
123 "stx %1, [%0 + %2 + 0x70]\n\t" \
124 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
125 "wrpr %%g0, (1 << 3), %%wstate\n\t" \
126 : \
127 : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
128 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
129 fprs_write(0); \
130 current_thread_info()->xfsr[0] = 0; \
131 current_thread_info()->fpsaved[0] = 0; \
132 regs->tstate &= ~TSTATE_PEF; \
133} while (0)
134
135#define start_thread32(regs, pc, sp) \
136do { \
137 unsigned long __asi = ASI_PNF; \
138 pc &= 0x00000000ffffffffUL; \
139 sp &= 0x00000000ffffffffUL; \
140 regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
141 regs->tpc = ((pc & (~3)) - 4); \
142 regs->tnpc = regs->tpc + 4; \
143 regs->y = 0; \
144 set_thread_wstate(2 << 3); \
145 if (current_thread_info()->utraps) { \
146 if (*(current_thread_info()->utraps) < 2) \
147 kfree(current_thread_info()->utraps); \
148 else \
149 (*(current_thread_info()->utraps))--; \
150 current_thread_info()->utraps = NULL; \
151 } \
152 __asm__ __volatile__( \
153 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
154 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
155 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
156 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
157 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
158 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
159 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
160 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
161 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
162 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
163 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
164 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
165 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
166 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
167 "stx %1, [%0 + %2 + 0x70]\n\t" \
168 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
169 "wrpr %%g0, (2 << 3), %%wstate\n\t" \
170 : \
171 : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
172 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
173 fprs_write(0); \
174 current_thread_info()->xfsr[0] = 0; \
175 current_thread_info()->fpsaved[0] = 0; \
176 regs->tstate &= ~TSTATE_PEF; \
177} while (0)
178
179unsigned long __get_wchan(struct task_struct *task);
180
181#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
182#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
183#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
184
185/* Please see the commentary in asm/backoff.h for a description of
186 * what these instructions are doing and how they have been chosen.
187 * To make a long story short, we are trying to yield the current cpu
188 * strand during busy loops.
189 */
190#ifdef BUILD_VDSO
191#define cpu_relax() asm volatile("\n99:\n\t" \
192 "rd %%ccr, %%g0\n\t" \
193 "rd %%ccr, %%g0\n\t" \
194 "rd %%ccr, %%g0\n\t" \
195 ::: "memory")
196#else /* ! BUILD_VDSO */
197#define cpu_relax() asm volatile("\n99:\n\t" \
198 "rd %%ccr, %%g0\n\t" \
199 "rd %%ccr, %%g0\n\t" \
200 "rd %%ccr, %%g0\n\t" \
201 ".section .pause_3insn_patch,\"ax\"\n\t"\
202 ".word 99b\n\t" \
203 "wr %%g0, 128, %%asr27\n\t" \
204 "nop\n\t" \
205 "nop\n\t" \
206 ".previous" \
207 ::: "memory")
208#endif
209
210/* Prefetch support. This is tuned for UltraSPARC-III and later.
211 * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
212 * a shallower prefetch queue than later chips.
213 */
214#define ARCH_HAS_PREFETCH
215#define ARCH_HAS_PREFETCHW
216#define ARCH_HAS_SPINLOCK_PREFETCH
217
218static inline void prefetch(const void *x)
219{
220 /* We do not use the read prefetch mnemonic because that
221 * prefetches into the prefetch-cache which only is accessible
222 * by floating point operations in UltraSPARC-III and later.
223 * By contrast, "#one_write" prefetches into the L2 cache
224 * in shared state.
225 */
226 __asm__ __volatile__("prefetch [%0], #one_write"
227 : /* no outputs */
228 : "r" (x));
229}
230
231static inline void prefetchw(const void *x)
232{
233 /* The most optimal prefetch to use for writes is
234 * "#n_writes". This brings the cacheline into the
235 * L2 cache in "owned" state.
236 */
237 __asm__ __volatile__("prefetch [%0], #n_writes"
238 : /* no outputs */
239 : "r" (x));
240}
241
242#define spin_lock_prefetch(x) prefetchw(x)
243
244#define HAVE_ARCH_PICK_MMAP_LAYOUT
245
246int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap);
247
248#endif /* !(__ASSEMBLY__) */
249
250#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * include/asm/processor.h
4 *
5 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#ifndef __ASM_SPARC64_PROCESSOR_H
9#define __ASM_SPARC64_PROCESSOR_H
10
11/*
12 * Sparc64 implementation of macro that returns current
13 * instruction pointer ("program counter").
14 */
15#define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
16
17#include <asm/asi.h>
18#include <asm/pstate.h>
19#include <asm/ptrace.h>
20#include <asm/page.h>
21
22/*
23 * User lives in his very own context, and cannot reference us. Note
24 * that TASK_SIZE is a misnomer, it really gives maximum user virtual
25 * address that the kernel will allocate out.
26 *
27 * XXX No longer using virtual page tables, kill this upper limit...
28 */
29#define VA_BITS 44
30#ifndef __ASSEMBLY__
31#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
32#else
33#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
34#endif
35
36#define TASK_SIZE_OF(tsk) \
37 (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
38 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
39#define TASK_SIZE \
40 (test_thread_flag(TIF_32BIT) ? \
41 (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
42#ifdef __KERNEL__
43
44#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
45#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
46
47#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
48 STACK_TOP32 : STACK_TOP64)
49
50#define STACK_TOP_MAX STACK_TOP64
51
52#endif
53
54#ifndef __ASSEMBLY__
55
56typedef struct {
57 unsigned char seg;
58} mm_segment_t;
59
60/* The Sparc processor specific thread struct. */
61/* XXX This should die, everything can go into thread_info now. */
62struct thread_struct {
63#ifdef CONFIG_DEBUG_SPINLOCK
64 /* How many spinlocks held by this thread.
65 * Used with spin lock debugging to catch tasks
66 * sleeping illegally with locks held.
67 */
68 int smp_lock_count;
69 unsigned int smp_lock_pc;
70#else
71 int dummy; /* f'in gcc bug... */
72#endif
73};
74
75#endif /* !(__ASSEMBLY__) */
76
77#ifndef CONFIG_DEBUG_SPINLOCK
78#define INIT_THREAD { \
79 0, \
80}
81#else /* CONFIG_DEBUG_SPINLOCK */
82#define INIT_THREAD { \
83/* smp_lock_count, smp_lock_pc, */ \
84 0, 0, \
85}
86#endif /* !(CONFIG_DEBUG_SPINLOCK) */
87
88#ifndef __ASSEMBLY__
89
90#include <linux/types.h>
91#include <asm/fpumacro.h>
92
93struct task_struct;
94
95/* On Uniprocessor, even in RMO processes see TSO semantics */
96#ifdef CONFIG_SMP
97#define TSTATE_INITIAL_MM TSTATE_TSO
98#else
99#define TSTATE_INITIAL_MM TSTATE_RMO
100#endif
101
102/* Do necessary setup to start up a newly executed thread. */
103#define start_thread(regs, pc, sp) \
104do { \
105 unsigned long __asi = ASI_PNF; \
106 regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
107 regs->tpc = ((pc & (~3)) - 4); \
108 regs->tnpc = regs->tpc + 4; \
109 regs->y = 0; \
110 set_thread_wstate(1 << 3); \
111 if (current_thread_info()->utraps) { \
112 if (*(current_thread_info()->utraps) < 2) \
113 kfree(current_thread_info()->utraps); \
114 else \
115 (*(current_thread_info()->utraps))--; \
116 current_thread_info()->utraps = NULL; \
117 } \
118 __asm__ __volatile__( \
119 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
120 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
121 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
122 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
123 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
124 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
125 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
126 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
127 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
128 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
129 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
130 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
131 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
132 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
133 "stx %1, [%0 + %2 + 0x70]\n\t" \
134 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
135 "wrpr %%g0, (1 << 3), %%wstate\n\t" \
136 : \
137 : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
138 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
139 fprs_write(0); \
140 current_thread_info()->xfsr[0] = 0; \
141 current_thread_info()->fpsaved[0] = 0; \
142 regs->tstate &= ~TSTATE_PEF; \
143} while (0)
144
145#define start_thread32(regs, pc, sp) \
146do { \
147 unsigned long __asi = ASI_PNF; \
148 pc &= 0x00000000ffffffffUL; \
149 sp &= 0x00000000ffffffffUL; \
150 regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
151 regs->tpc = ((pc & (~3)) - 4); \
152 regs->tnpc = regs->tpc + 4; \
153 regs->y = 0; \
154 set_thread_wstate(2 << 3); \
155 if (current_thread_info()->utraps) { \
156 if (*(current_thread_info()->utraps) < 2) \
157 kfree(current_thread_info()->utraps); \
158 else \
159 (*(current_thread_info()->utraps))--; \
160 current_thread_info()->utraps = NULL; \
161 } \
162 __asm__ __volatile__( \
163 "stx %%g0, [%0 + %2 + 0x00]\n\t" \
164 "stx %%g0, [%0 + %2 + 0x08]\n\t" \
165 "stx %%g0, [%0 + %2 + 0x10]\n\t" \
166 "stx %%g0, [%0 + %2 + 0x18]\n\t" \
167 "stx %%g0, [%0 + %2 + 0x20]\n\t" \
168 "stx %%g0, [%0 + %2 + 0x28]\n\t" \
169 "stx %%g0, [%0 + %2 + 0x30]\n\t" \
170 "stx %%g0, [%0 + %2 + 0x38]\n\t" \
171 "stx %%g0, [%0 + %2 + 0x40]\n\t" \
172 "stx %%g0, [%0 + %2 + 0x48]\n\t" \
173 "stx %%g0, [%0 + %2 + 0x50]\n\t" \
174 "stx %%g0, [%0 + %2 + 0x58]\n\t" \
175 "stx %%g0, [%0 + %2 + 0x60]\n\t" \
176 "stx %%g0, [%0 + %2 + 0x68]\n\t" \
177 "stx %1, [%0 + %2 + 0x70]\n\t" \
178 "stx %%g0, [%0 + %2 + 0x78]\n\t" \
179 "wrpr %%g0, (2 << 3), %%wstate\n\t" \
180 : \
181 : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
182 "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
183 fprs_write(0); \
184 current_thread_info()->xfsr[0] = 0; \
185 current_thread_info()->fpsaved[0] = 0; \
186 regs->tstate &= ~TSTATE_PEF; \
187} while (0)
188
189/* Free all resources held by a thread. */
190#define release_thread(tsk) do { } while (0)
191
192unsigned long get_wchan(struct task_struct *task);
193
194#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
195#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
196#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
197
198/* Please see the commentary in asm/backoff.h for a description of
199 * what these instructions are doing and how they have been chosen.
200 * To make a long story short, we are trying to yield the current cpu
201 * strand during busy loops.
202 */
203#ifdef BUILD_VDSO
204#define cpu_relax() asm volatile("\n99:\n\t" \
205 "rd %%ccr, %%g0\n\t" \
206 "rd %%ccr, %%g0\n\t" \
207 "rd %%ccr, %%g0\n\t" \
208 ::: "memory")
209#else /* ! BUILD_VDSO */
210#define cpu_relax() asm volatile("\n99:\n\t" \
211 "rd %%ccr, %%g0\n\t" \
212 "rd %%ccr, %%g0\n\t" \
213 "rd %%ccr, %%g0\n\t" \
214 ".section .pause_3insn_patch,\"ax\"\n\t"\
215 ".word 99b\n\t" \
216 "wr %%g0, 128, %%asr27\n\t" \
217 "nop\n\t" \
218 "nop\n\t" \
219 ".previous" \
220 ::: "memory")
221#endif
222
223/* Prefetch support. This is tuned for UltraSPARC-III and later.
224 * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
225 * a shallower prefetch queue than later chips.
226 */
227#define ARCH_HAS_PREFETCH
228#define ARCH_HAS_PREFETCHW
229#define ARCH_HAS_SPINLOCK_PREFETCH
230
231static inline void prefetch(const void *x)
232{
233 /* We do not use the read prefetch mnemonic because that
234 * prefetches into the prefetch-cache which only is accessible
235 * by floating point operations in UltraSPARC-III and later.
236 * By contrast, "#one_write" prefetches into the L2 cache
237 * in shared state.
238 */
239 __asm__ __volatile__("prefetch [%0], #one_write"
240 : /* no outputs */
241 : "r" (x));
242}
243
244static inline void prefetchw(const void *x)
245{
246 /* The most optimal prefetch to use for writes is
247 * "#n_writes". This brings the cacheline into the
248 * L2 cache in "owned" state.
249 */
250 __asm__ __volatile__("prefetch [%0], #n_writes"
251 : /* no outputs */
252 : "r" (x));
253}
254
255#define spin_lock_prefetch(x) prefetchw(x)
256
257#define HAVE_ARCH_PICK_MMAP_LAYOUT
258
259int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap);
260
261#endif /* !(__ASSEMBLY__) */
262
263#endif /* !(__ASM_SPARC64_PROCESSOR_H) */