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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __SPARC64_IO_H
3#define __SPARC64_IO_H
4
5#include <linux/kernel.h>
6#include <linux/compiler.h>
7#include <linux/types.h>
8
9#include <asm/page.h> /* IO address mapping routines need this */
10#include <asm/asi.h>
11#include <asm-generic/pci_iomap.h>
12#define pci_iomap pci_iomap
13
14/* BIO layer definitions. */
15extern unsigned long kern_base, kern_size;
16
17/* __raw_{read,write}{b,w,l,q} uses direct access.
18 * Access the memory as big endian bypassing the cache
19 * by using ASI_PHYS_BYPASS_EC_E
20 */
21#define __raw_readb __raw_readb
22static inline u8 __raw_readb(const volatile void __iomem *addr)
23{
24 u8 ret;
25
26 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
27 : "=r" (ret)
28 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
29
30 return ret;
31}
32
33#define __raw_readw __raw_readw
34static inline u16 __raw_readw(const volatile void __iomem *addr)
35{
36 u16 ret;
37
38 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
39 : "=r" (ret)
40 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
41
42 return ret;
43}
44
45#define __raw_readl __raw_readl
46static inline u32 __raw_readl(const volatile void __iomem *addr)
47{
48 u32 ret;
49
50 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
51 : "=r" (ret)
52 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
53
54 return ret;
55}
56
57#define __raw_readq __raw_readq
58static inline u64 __raw_readq(const volatile void __iomem *addr)
59{
60 u64 ret;
61
62 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
63 : "=r" (ret)
64 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
65
66 return ret;
67}
68
69#define __raw_writeb __raw_writeb
70static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
71{
72 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
73 : /* no outputs */
74 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
75}
76
77#define __raw_writew __raw_writew
78static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
79{
80 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
81 : /* no outputs */
82 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
83}
84
85#define __raw_writel __raw_writel
86static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
87{
88 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
89 : /* no outputs */
90 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
91}
92
93#define __raw_writeq __raw_writeq
94static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
95{
96 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
97 : /* no outputs */
98 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
99}
100
101/* Memory functions, same as I/O accesses on Ultra.
102 * Access memory as little endian bypassing
103 * the cache by using ASI_PHYS_BYPASS_EC_E_L
104 */
105#define readb readb
106#define readb_relaxed readb
107static inline u8 readb(const volatile void __iomem *addr)
108{ u8 ret;
109
110 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
111 : "=r" (ret)
112 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
113 : "memory");
114 return ret;
115}
116
117#define readw readw
118#define readw_relaxed readw
119static inline u16 readw(const volatile void __iomem *addr)
120{ u16 ret;
121
122 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
123 : "=r" (ret)
124 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
125 : "memory");
126
127 return ret;
128}
129
130#define readl readl
131#define readl_relaxed readl
132static inline u32 readl(const volatile void __iomem *addr)
133{ u32 ret;
134
135 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
136 : "=r" (ret)
137 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
138 : "memory");
139
140 return ret;
141}
142
143#define readq readq
144#define readq_relaxed readq
145static inline u64 readq(const volatile void __iomem *addr)
146{ u64 ret;
147
148 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
149 : "=r" (ret)
150 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
151 : "memory");
152
153 return ret;
154}
155
156#define writeb writeb
157#define writeb_relaxed writeb
158static inline void writeb(u8 b, volatile void __iomem *addr)
159{
160 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
161 : /* no outputs */
162 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
163 : "memory");
164}
165
166#define writew writew
167#define writew_relaxed writew
168static inline void writew(u16 w, volatile void __iomem *addr)
169{
170 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
171 : /* no outputs */
172 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
173 : "memory");
174}
175
176#define writel writel
177#define writel_relaxed writel
178static inline void writel(u32 l, volatile void __iomem *addr)
179{
180 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
181 : /* no outputs */
182 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
183 : "memory");
184}
185
186#define writeq writeq
187#define writeq_relaxed writeq
188static inline void writeq(u64 q, volatile void __iomem *addr)
189{
190 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
191 : /* no outputs */
192 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
193 : "memory");
194}
195
196#define inb inb
197static inline u8 inb(unsigned long addr)
198{
199 return readb((volatile void __iomem *)addr);
200}
201
202#define inw inw
203static inline u16 inw(unsigned long addr)
204{
205 return readw((volatile void __iomem *)addr);
206}
207
208#define inl inl
209static inline u32 inl(unsigned long addr)
210{
211 return readl((volatile void __iomem *)addr);
212}
213
214#define outb outb
215static inline void outb(u8 b, unsigned long addr)
216{
217 writeb(b, (volatile void __iomem *)addr);
218}
219
220#define outw outw
221static inline void outw(u16 w, unsigned long addr)
222{
223 writew(w, (volatile void __iomem *)addr);
224}
225
226#define outl outl
227static inline void outl(u32 l, unsigned long addr)
228{
229 writel(l, (volatile void __iomem *)addr);
230}
231
232
233#define inb_p(__addr) inb(__addr)
234#define outb_p(__b, __addr) outb(__b, __addr)
235#define inw_p(__addr) inw(__addr)
236#define outw_p(__w, __addr) outw(__w, __addr)
237#define inl_p(__addr) inl(__addr)
238#define outl_p(__l, __addr) outl(__l, __addr)
239
240void outsb(unsigned long, const void *, unsigned long);
241void outsw(unsigned long, const void *, unsigned long);
242void outsl(unsigned long, const void *, unsigned long);
243#define outsb outsb
244#define outsw outsw
245#define outsl outsl
246void insb(unsigned long, void *, unsigned long);
247void insw(unsigned long, void *, unsigned long);
248void insl(unsigned long, void *, unsigned long);
249#define insb insb
250#define insw insw
251#define insl insl
252
253static inline void readsb(void __iomem *port, void *buf, unsigned long count)
254{
255 insb((unsigned long __force)port, buf, count);
256}
257#define readsb readsb
258
259static inline void readsw(void __iomem *port, void *buf, unsigned long count)
260{
261 insw((unsigned long __force)port, buf, count);
262}
263#define readsw readsw
264
265static inline void readsl(void __iomem *port, void *buf, unsigned long count)
266{
267 insl((unsigned long __force)port, buf, count);
268}
269#define readsl readsl
270
271static inline void writesb(void __iomem *port, const void *buf, unsigned long count)
272{
273 outsb((unsigned long __force)port, buf, count);
274}
275#define writesb writesb
276
277static inline void writesw(void __iomem *port, const void *buf, unsigned long count)
278{
279 outsw((unsigned long __force)port, buf, count);
280}
281#define writesw writesw
282
283static inline void writesl(void __iomem *port, const void *buf, unsigned long count)
284{
285 outsl((unsigned long __force)port, buf, count);
286}
287#define writesl writesl
288
289#define ioread8_rep(p,d,l) readsb(p,d,l)
290#define ioread16_rep(p,d,l) readsw(p,d,l)
291#define ioread32_rep(p,d,l) readsl(p,d,l)
292#define iowrite8_rep(p,d,l) writesb(p,d,l)
293#define iowrite16_rep(p,d,l) writesw(p,d,l)
294#define iowrite32_rep(p,d,l) writesl(p,d,l)
295
296/* Valid I/O Space regions are anywhere, because each PCI bus supported
297 * can live in an arbitrary area of the physical address range.
298 */
299#define IO_SPACE_LIMIT 0xffffffffffffffffUL
300
301/* Now, SBUS variants, only difference from PCI is that we do
302 * not use little-endian ASIs.
303 */
304static inline u8 sbus_readb(const volatile void __iomem *addr)
305{
306 return __raw_readb(addr);
307}
308
309static inline u16 sbus_readw(const volatile void __iomem *addr)
310{
311 return __raw_readw(addr);
312}
313
314static inline u32 sbus_readl(const volatile void __iomem *addr)
315{
316 return __raw_readl(addr);
317}
318
319static inline u64 sbus_readq(const volatile void __iomem *addr)
320{
321 return __raw_readq(addr);
322}
323
324static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
325{
326 __raw_writeb(b, addr);
327}
328
329static inline void sbus_writew(u16 w, volatile void __iomem *addr)
330{
331 __raw_writew(w, addr);
332}
333
334static inline void sbus_writel(u32 l, volatile void __iomem *addr)
335{
336 __raw_writel(l, addr);
337}
338
339static inline void sbus_writeq(u64 q, volatile void __iomem *addr)
340{
341 __raw_writeq(q, addr);
342}
343
344static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
345{
346 while(n--) {
347 sbus_writeb(c, dst);
348 dst++;
349 }
350}
351
352static inline void memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
353{
354 volatile void __iomem *d = dst;
355
356 while (n--) {
357 writeb(c, d);
358 d++;
359 }
360}
361#define memset_io memset_io
362
363static inline void sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
364 __kernel_size_t n)
365{
366 char *d = dst;
367
368 while (n--) {
369 char tmp = sbus_readb(src);
370 *d++ = tmp;
371 src++;
372 }
373}
374
375
376static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
377 __kernel_size_t n)
378{
379 char *d = dst;
380
381 while (n--) {
382 char tmp = readb(src);
383 *d++ = tmp;
384 src++;
385 }
386}
387#define memcpy_fromio memcpy_fromio
388
389static inline void sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
390 __kernel_size_t n)
391{
392 const char *s = src;
393 volatile void __iomem *d = dst;
394
395 while (n--) {
396 char tmp = *s++;
397 sbus_writeb(tmp, d);
398 d++;
399 }
400}
401
402static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
403 __kernel_size_t n)
404{
405 const char *s = src;
406 volatile void __iomem *d = dst;
407
408 while (n--) {
409 char tmp = *s++;
410 writeb(tmp, d);
411 d++;
412 }
413}
414#define memcpy_toio memcpy_toio
415
416#ifdef __KERNEL__
417
418/* On sparc64 we have the whole physical IO address space accessible
419 * using physically addressed loads and stores, so this does nothing.
420 */
421static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
422{
423 return (void __iomem *)offset;
424}
425
426#define ioremap_uc(X,Y) ioremap((X),(Y))
427#define ioremap_wc(X,Y) ioremap((X),(Y))
428#define ioremap_wt(X,Y) ioremap((X),(Y))
429static inline void __iomem *ioremap_np(unsigned long offset, unsigned long size)
430{
431 return NULL;
432
433}
434#define ioremap_np ioremap_np
435
436static inline void iounmap(volatile void __iomem *addr)
437{
438}
439
440#define ioread8 readb
441#define ioread16 readw
442#define ioread16be __raw_readw
443#define ioread32 readl
444#define ioread32be __raw_readl
445#define iowrite8 writeb
446#define iowrite16 writew
447#define iowrite16be __raw_writew
448#define iowrite32 writel
449#define iowrite32be __raw_writel
450
451/* Create a virtual mapping cookie for an IO port range */
452void __iomem *ioport_map(unsigned long port, unsigned int nr);
453void ioport_unmap(void __iomem *);
454#define ioport_map ioport_map
455#define ioport_unmap ioport_unmap
456
457/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
458struct pci_dev;
459void pci_iounmap(struct pci_dev *dev, void __iomem *);
460#define pci_iounmap pci_iounmap
461
462static inline int sbus_can_dma_64bit(void)
463{
464 return 1;
465}
466static inline int sbus_can_burst64(void)
467{
468 return 1;
469}
470struct device;
471void sbus_set_sbus64(struct device *, int);
472
473/*
474 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
475 * access
476 */
477#define xlate_dev_mem_ptr(p) __va(p)
478
479#endif
480
481#endif /* !(__SPARC64_IO_H) */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __SPARC64_IO_H
3#define __SPARC64_IO_H
4
5#include <linux/kernel.h>
6#include <linux/compiler.h>
7#include <linux/types.h>
8
9#include <asm/page.h> /* IO address mapping routines need this */
10#include <asm/asi.h>
11#include <asm-generic/pci_iomap.h>
12
13/* BIO layer definitions. */
14extern unsigned long kern_base, kern_size;
15
16/* __raw_{read,write}{b,w,l,q} uses direct access.
17 * Access the memory as big endian bypassing the cache
18 * by using ASI_PHYS_BYPASS_EC_E
19 */
20#define __raw_readb __raw_readb
21static inline u8 __raw_readb(const volatile void __iomem *addr)
22{
23 u8 ret;
24
25 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */"
26 : "=r" (ret)
27 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
28
29 return ret;
30}
31
32#define __raw_readw __raw_readw
33static inline u16 __raw_readw(const volatile void __iomem *addr)
34{
35 u16 ret;
36
37 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */"
38 : "=r" (ret)
39 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
40
41 return ret;
42}
43
44#define __raw_readl __raw_readl
45static inline u32 __raw_readl(const volatile void __iomem *addr)
46{
47 u32 ret;
48
49 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */"
50 : "=r" (ret)
51 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
52
53 return ret;
54}
55
56#define __raw_readq __raw_readq
57static inline u64 __raw_readq(const volatile void __iomem *addr)
58{
59 u64 ret;
60
61 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */"
62 : "=r" (ret)
63 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
64
65 return ret;
66}
67
68#define __raw_writeb __raw_writeb
69static inline void __raw_writeb(u8 b, const volatile void __iomem *addr)
70{
71 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */"
72 : /* no outputs */
73 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
74}
75
76#define __raw_writew __raw_writew
77static inline void __raw_writew(u16 w, const volatile void __iomem *addr)
78{
79 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */"
80 : /* no outputs */
81 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
82}
83
84#define __raw_writel __raw_writel
85static inline void __raw_writel(u32 l, const volatile void __iomem *addr)
86{
87 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */"
88 : /* no outputs */
89 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
90}
91
92#define __raw_writeq __raw_writeq
93static inline void __raw_writeq(u64 q, const volatile void __iomem *addr)
94{
95 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */"
96 : /* no outputs */
97 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
98}
99
100/* Memory functions, same as I/O accesses on Ultra.
101 * Access memory as little endian bypassing
102 * the cache by using ASI_PHYS_BYPASS_EC_E_L
103 */
104#define readb readb
105#define readb_relaxed readb
106static inline u8 readb(const volatile void __iomem *addr)
107{ u8 ret;
108
109 __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
110 : "=r" (ret)
111 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
112 : "memory");
113 return ret;
114}
115
116#define readw readw
117#define readw_relaxed readw
118static inline u16 readw(const volatile void __iomem *addr)
119{ u16 ret;
120
121 __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
122 : "=r" (ret)
123 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
124 : "memory");
125
126 return ret;
127}
128
129#define readl readl
130#define readl_relaxed readl
131static inline u32 readl(const volatile void __iomem *addr)
132{ u32 ret;
133
134 __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
135 : "=r" (ret)
136 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
137 : "memory");
138
139 return ret;
140}
141
142#define readq readq
143#define readq_relaxed readq
144static inline u64 readq(const volatile void __iomem *addr)
145{ u64 ret;
146
147 __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
148 : "=r" (ret)
149 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
150 : "memory");
151
152 return ret;
153}
154
155#define writeb writeb
156#define writeb_relaxed writeb
157static inline void writeb(u8 b, volatile void __iomem *addr)
158{
159 __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
160 : /* no outputs */
161 : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
162 : "memory");
163}
164
165#define writew writew
166#define writew_relaxed writew
167static inline void writew(u16 w, volatile void __iomem *addr)
168{
169 __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
170 : /* no outputs */
171 : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
172 : "memory");
173}
174
175#define writel writel
176#define writel_relaxed writel
177static inline void writel(u32 l, volatile void __iomem *addr)
178{
179 __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
180 : /* no outputs */
181 : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
182 : "memory");
183}
184
185#define writeq writeq
186#define writeq_relaxed writeq
187static inline void writeq(u64 q, volatile void __iomem *addr)
188{
189 __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
190 : /* no outputs */
191 : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
192 : "memory");
193}
194
195#define inb inb
196static inline u8 inb(unsigned long addr)
197{
198 return readb((volatile void __iomem *)addr);
199}
200
201#define inw inw
202static inline u16 inw(unsigned long addr)
203{
204 return readw((volatile void __iomem *)addr);
205}
206
207#define inl inl
208static inline u32 inl(unsigned long addr)
209{
210 return readl((volatile void __iomem *)addr);
211}
212
213#define outb outb
214static inline void outb(u8 b, unsigned long addr)
215{
216 writeb(b, (volatile void __iomem *)addr);
217}
218
219#define outw outw
220static inline void outw(u16 w, unsigned long addr)
221{
222 writew(w, (volatile void __iomem *)addr);
223}
224
225#define outl outl
226static inline void outl(u32 l, unsigned long addr)
227{
228 writel(l, (volatile void __iomem *)addr);
229}
230
231
232#define inb_p(__addr) inb(__addr)
233#define outb_p(__b, __addr) outb(__b, __addr)
234#define inw_p(__addr) inw(__addr)
235#define outw_p(__w, __addr) outw(__w, __addr)
236#define inl_p(__addr) inl(__addr)
237#define outl_p(__l, __addr) outl(__l, __addr)
238
239void outsb(unsigned long, const void *, unsigned long);
240void outsw(unsigned long, const void *, unsigned long);
241void outsl(unsigned long, const void *, unsigned long);
242void insb(unsigned long, void *, unsigned long);
243void insw(unsigned long, void *, unsigned long);
244void insl(unsigned long, void *, unsigned long);
245
246static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count)
247{
248 insb((unsigned long __force)port, buf, count);
249}
250static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count)
251{
252 insw((unsigned long __force)port, buf, count);
253}
254
255static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count)
256{
257 insl((unsigned long __force)port, buf, count);
258}
259
260static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count)
261{
262 outsb((unsigned long __force)port, buf, count);
263}
264
265static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count)
266{
267 outsw((unsigned long __force)port, buf, count);
268}
269
270static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count)
271{
272 outsl((unsigned long __force)port, buf, count);
273}
274
275/* Valid I/O Space regions are anywhere, because each PCI bus supported
276 * can live in an arbitrary area of the physical address range.
277 */
278#define IO_SPACE_LIMIT 0xffffffffffffffffUL
279
280/* Now, SBUS variants, only difference from PCI is that we do
281 * not use little-endian ASIs.
282 */
283static inline u8 sbus_readb(const volatile void __iomem *addr)
284{
285 return __raw_readb(addr);
286}
287
288static inline u16 sbus_readw(const volatile void __iomem *addr)
289{
290 return __raw_readw(addr);
291}
292
293static inline u32 sbus_readl(const volatile void __iomem *addr)
294{
295 return __raw_readl(addr);
296}
297
298static inline u64 sbus_readq(const volatile void __iomem *addr)
299{
300 return __raw_readq(addr);
301}
302
303static inline void sbus_writeb(u8 b, volatile void __iomem *addr)
304{
305 __raw_writeb(b, addr);
306}
307
308static inline void sbus_writew(u16 w, volatile void __iomem *addr)
309{
310 __raw_writew(w, addr);
311}
312
313static inline void sbus_writel(u32 l, volatile void __iomem *addr)
314{
315 __raw_writel(l, addr);
316}
317
318static inline void sbus_writeq(u64 q, volatile void __iomem *addr)
319{
320 __raw_writeq(q, addr);
321}
322
323static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
324{
325 while(n--) {
326 sbus_writeb(c, dst);
327 dst++;
328 }
329}
330
331static inline void memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
332{
333 volatile void __iomem *d = dst;
334
335 while (n--) {
336 writeb(c, d);
337 d++;
338 }
339}
340
341static inline void sbus_memcpy_fromio(void *dst, const volatile void __iomem *src,
342 __kernel_size_t n)
343{
344 char *d = dst;
345
346 while (n--) {
347 char tmp = sbus_readb(src);
348 *d++ = tmp;
349 src++;
350 }
351}
352
353
354static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
355 __kernel_size_t n)
356{
357 char *d = dst;
358
359 while (n--) {
360 char tmp = readb(src);
361 *d++ = tmp;
362 src++;
363 }
364}
365
366static inline void sbus_memcpy_toio(volatile void __iomem *dst, const void *src,
367 __kernel_size_t n)
368{
369 const char *s = src;
370 volatile void __iomem *d = dst;
371
372 while (n--) {
373 char tmp = *s++;
374 sbus_writeb(tmp, d);
375 d++;
376 }
377}
378
379static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
380 __kernel_size_t n)
381{
382 const char *s = src;
383 volatile void __iomem *d = dst;
384
385 while (n--) {
386 char tmp = *s++;
387 writeb(tmp, d);
388 d++;
389 }
390}
391
392#define mmiowb()
393
394#ifdef __KERNEL__
395
396/* On sparc64 we have the whole physical IO address space accessible
397 * using physically addressed loads and stores, so this does nothing.
398 */
399static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
400{
401 return (void __iomem *)offset;
402}
403
404#define ioremap_nocache(X,Y) ioremap((X),(Y))
405#define ioremap_wc(X,Y) ioremap((X),(Y))
406#define ioremap_wt(X,Y) ioremap((X),(Y))
407
408static inline void iounmap(volatile void __iomem *addr)
409{
410}
411
412#define ioread8 readb
413#define ioread16 readw
414#define ioread16be __raw_readw
415#define ioread32 readl
416#define ioread32be __raw_readl
417#define iowrite8 writeb
418#define iowrite16 writew
419#define iowrite16be __raw_writew
420#define iowrite32 writel
421#define iowrite32be __raw_writel
422
423/* Create a virtual mapping cookie for an IO port range */
424void __iomem *ioport_map(unsigned long port, unsigned int nr);
425void ioport_unmap(void __iomem *);
426
427/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
428struct pci_dev;
429void pci_iounmap(struct pci_dev *dev, void __iomem *);
430
431static inline int sbus_can_dma_64bit(void)
432{
433 return 1;
434}
435static inline int sbus_can_burst64(void)
436{
437 return 1;
438}
439struct device;
440void sbus_set_sbus64(struct device *, int);
441
442/*
443 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
444 * access
445 */
446#define xlate_dev_mem_ptr(p) __va(p)
447
448/*
449 * Convert a virtual cached pointer to an uncached pointer
450 */
451#define xlate_dev_kmem_ptr(p) p
452
453#endif
454
455#endif /* !(__SPARC64_IO_H) */