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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC8641 HPCN Device Tree Source
4 *
5 * Copyright 2008-2009 Freescale Semiconductor Inc.
6 */
7
8/include/ "mpc8641si-pre.dtsi"
9
10/ {
11 model = "MPC8641HPCN";
12 compatible = "fsl,mpc8641hpcn";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 memory {
17 device_type = "memory";
18 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
19 };
20
21 lbc: localbus@fffe05000 {
22 reg = <0x0f 0xffe05000 0x0 0x1000>;
23
24 ranges = <0 0 0xf 0xef800000 0x00800000
25 2 0 0xf 0xffdf8000 0x00008000
26 3 0 0xf 0xffdf0000 0x00008000>;
27
28 flash@0,0 {
29 compatible = "cfi-flash";
30 reg = <0 0 0x00800000>;
31 bank-width = <2>;
32 device-width = <2>;
33 #address-cells = <1>;
34 #size-cells = <1>;
35 partition@0 {
36 label = "kernel";
37 reg = <0x00000000 0x00300000>;
38 };
39 partition@300000 {
40 label = "firmware b";
41 reg = <0x00300000 0x00100000>;
42 read-only;
43 };
44 partition@400000 {
45 label = "fs";
46 reg = <0x00400000 0x00300000>;
47 };
48 partition@700000 {
49 label = "firmware a";
50 reg = <0x00700000 0x00100000>;
51 read-only;
52 };
53 };
54 };
55
56 soc: soc8641@fffe00000 {
57 ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
58
59 enet0: ethernet@24000 {
60 tbi-handle = <&tbi0>;
61 phy-handle = <&phy0>;
62 phy-connection-type = "rgmii-id";
63 };
64
65 mdio@24520 {
66 phy0: ethernet-phy@0 {
67 interrupts = <10 1 0 0>;
68 reg = <0>;
69 };
70 phy1: ethernet-phy@1 {
71 interrupts = <10 1 0 0>;
72 reg = <1>;
73 };
74 phy2: ethernet-phy@2 {
75 interrupts = <10 1 0 0>;
76 reg = <2>;
77 };
78 phy3: ethernet-phy@3 {
79 interrupts = <10 1 0 0>;
80 reg = <3>;
81 };
82 tbi0: tbi-phy@11 {
83 reg = <0x11>;
84 device_type = "tbi-phy";
85 };
86 };
87
88 enet1: ethernet@25000 {
89 tbi-handle = <&tbi1>;
90 phy-handle = <&phy1>;
91 phy-connection-type = "rgmii-id";
92 };
93
94 mdio@25520 {
95 tbi1: tbi-phy@11 {
96 reg = <0x11>;
97 device_type = "tbi-phy";
98 };
99 };
100
101 enet2: ethernet@26000 {
102 tbi-handle = <&tbi2>;
103 phy-handle = <&phy2>;
104 phy-connection-type = "rgmii-id";
105 };
106
107 mdio@26520 {
108 tbi2: tbi-phy@11 {
109 reg = <0x11>;
110 device_type = "tbi-phy";
111 };
112 };
113
114 enet3: ethernet@27000 {
115 tbi-handle = <&tbi3>;
116 phy-handle = <&phy3>;
117 phy-connection-type = "rgmii-id";
118 };
119
120 mdio@27520 {
121 tbi3: tbi-phy@11 {
122 reg = <0x11>;
123 device_type = "tbi-phy";
124 };
125 };
126 };
127
128 pci0: pcie@fffe08000 {
129 reg = <0x0f 0xffe08000 0x0 0x1000>;
130 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
131 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
132 interrupt-map-mask = <0xff00 0 0 7>;
133 interrupt-map = <
134 /* IDSEL 0x11 func 0 - PCI slot 1 */
135 0x8800 0 0 1 &mpic 2 1 0 0
136 0x8800 0 0 2 &mpic 3 1 0 0
137 0x8800 0 0 3 &mpic 4 1 0 0
138 0x8800 0 0 4 &mpic 1 1 0 0
139
140 /* IDSEL 0x11 func 1 - PCI slot 1 */
141 0x8900 0 0 1 &mpic 2 1 0 0
142 0x8900 0 0 2 &mpic 3 1 0 0
143 0x8900 0 0 3 &mpic 4 1 0 0
144 0x8900 0 0 4 &mpic 1 1 0 0
145
146 /* IDSEL 0x11 func 2 - PCI slot 1 */
147 0x8a00 0 0 1 &mpic 2 1 0 0
148 0x8a00 0 0 2 &mpic 3 1 0 0
149 0x8a00 0 0 3 &mpic 4 1 0 0
150 0x8a00 0 0 4 &mpic 1 1 0 0
151
152 /* IDSEL 0x11 func 3 - PCI slot 1 */
153 0x8b00 0 0 1 &mpic 2 1 0 0
154 0x8b00 0 0 2 &mpic 3 1 0 0
155 0x8b00 0 0 3 &mpic 4 1 0 0
156 0x8b00 0 0 4 &mpic 1 1 0 0
157
158 /* IDSEL 0x11 func 4 - PCI slot 1 */
159 0x8c00 0 0 1 &mpic 2 1 0 0
160 0x8c00 0 0 2 &mpic 3 1 0 0
161 0x8c00 0 0 3 &mpic 4 1 0 0
162 0x8c00 0 0 4 &mpic 1 1 0 0
163
164 /* IDSEL 0x11 func 5 - PCI slot 1 */
165 0x8d00 0 0 1 &mpic 2 1 0 0
166 0x8d00 0 0 2 &mpic 3 1 0 0
167 0x8d00 0 0 3 &mpic 4 1 0 0
168 0x8d00 0 0 4 &mpic 1 1 0 0
169
170 /* IDSEL 0x11 func 6 - PCI slot 1 */
171 0x8e00 0 0 1 &mpic 2 1 0 0
172 0x8e00 0 0 2 &mpic 3 1 0 0
173 0x8e00 0 0 3 &mpic 4 1 0 0
174 0x8e00 0 0 4 &mpic 1 1 0 0
175
176 /* IDSEL 0x11 func 7 - PCI slot 1 */
177 0x8f00 0 0 1 &mpic 2 1 0 0
178 0x8f00 0 0 2 &mpic 3 1 0 0
179 0x8f00 0 0 3 &mpic 4 1 0 0
180 0x8f00 0 0 4 &mpic 1 1 0 0
181
182 /* IDSEL 0x12 func 0 - PCI slot 2 */
183 0x9000 0 0 1 &mpic 3 1 0 0
184 0x9000 0 0 2 &mpic 4 1 0 0
185 0x9000 0 0 3 &mpic 1 1 0 0
186 0x9000 0 0 4 &mpic 2 1 0 0
187
188 /* IDSEL 0x12 func 1 - PCI slot 2 */
189 0x9100 0 0 1 &mpic 3 1 0 0
190 0x9100 0 0 2 &mpic 4 1 0 0
191 0x9100 0 0 3 &mpic 1 1 0 0
192 0x9100 0 0 4 &mpic 2 1 0 0
193
194 /* IDSEL 0x12 func 2 - PCI slot 2 */
195 0x9200 0 0 1 &mpic 3 1 0 0
196 0x9200 0 0 2 &mpic 4 1 0 0
197 0x9200 0 0 3 &mpic 1 1 0 0
198 0x9200 0 0 4 &mpic 2 1 0 0
199
200 /* IDSEL 0x12 func 3 - PCI slot 2 */
201 0x9300 0 0 1 &mpic 3 1 0 0
202 0x9300 0 0 2 &mpic 4 1 0 0
203 0x9300 0 0 3 &mpic 1 1 0 0
204 0x9300 0 0 4 &mpic 2 1 0 0
205
206 /* IDSEL 0x12 func 4 - PCI slot 2 */
207 0x9400 0 0 1 &mpic 3 1 0 0
208 0x9400 0 0 2 &mpic 4 1 0 0
209 0x9400 0 0 3 &mpic 1 1 0 0
210 0x9400 0 0 4 &mpic 2 1 0 0
211
212 /* IDSEL 0x12 func 5 - PCI slot 2 */
213 0x9500 0 0 1 &mpic 3 1 0 0
214 0x9500 0 0 2 &mpic 4 1 0 0
215 0x9500 0 0 3 &mpic 1 1 0 0
216 0x9500 0 0 4 &mpic 2 1 0 0
217
218 /* IDSEL 0x12 func 6 - PCI slot 2 */
219 0x9600 0 0 1 &mpic 3 1 0 0
220 0x9600 0 0 2 &mpic 4 1 0 0
221 0x9600 0 0 3 &mpic 1 1 0 0
222 0x9600 0 0 4 &mpic 2 1 0 0
223
224 /* IDSEL 0x12 func 7 - PCI slot 2 */
225 0x9700 0 0 1 &mpic 3 1 0 0
226 0x9700 0 0 2 &mpic 4 1 0 0
227 0x9700 0 0 3 &mpic 1 1 0 0
228 0x9700 0 0 4 &mpic 2 1 0 0
229
230 // IDSEL 0x1c USB
231 0xe000 0 0 1 &i8259 12 2
232 0xe100 0 0 2 &i8259 9 2
233 0xe200 0 0 3 &i8259 10 2
234 0xe300 0 0 4 &i8259 11 2
235
236 // IDSEL 0x1d Audio
237 0xe800 0 0 1 &i8259 6 2
238
239 // IDSEL 0x1e Legacy
240 0xf000 0 0 1 &i8259 7 2
241 0xf100 0 0 1 &i8259 7 2
242
243 // IDSEL 0x1f IDE/SATA
244 0xf800 0 0 1 &i8259 14 2
245 0xf900 0 0 1 &i8259 5 2
246 >;
247
248 pcie@0 {
249 ranges = <0x02000000 0x0 0xe0000000
250 0x02000000 0x0 0xe0000000
251 0x0 0x20000000
252
253 0x01000000 0x0 0x00000000
254 0x01000000 0x0 0x00000000
255 0x0 0x00010000>;
256 uli1575@0 {
257 reg = <0 0 0 0 0>;
258 #size-cells = <2>;
259 #address-cells = <3>;
260 ranges = <0x02000000 0x0 0xe0000000
261 0x02000000 0x0 0xe0000000
262 0x0 0x20000000
263 0x01000000 0x0 0x00000000
264 0x01000000 0x0 0x00000000
265 0x0 0x00010000>;
266 isa@1e {
267 device_type = "isa";
268 #size-cells = <1>;
269 #address-cells = <2>;
270 reg = <0xf000 0 0 0 0>;
271 ranges = <1 0 0x01000000 0 0
272 0x00001000>;
273 interrupt-parent = <&i8259>;
274
275 i8259: interrupt-controller@20 {
276 reg = <1 0x20 2
277 1 0xa0 2
278 1 0x4d0 2>;
279 interrupt-controller;
280 device_type = "interrupt-controller";
281 #address-cells = <0>;
282 #interrupt-cells = <2>;
283 compatible = "chrp,iic";
284 interrupts = <9 2 0 0>;
285 };
286
287 i8042@60 {
288 #size-cells = <0>;
289 #address-cells = <1>;
290 reg = <1 0x60 1 1 0x64 1>;
291 interrupts = <1 3 12 3>;
292 interrupt-parent = <&i8259>;
293
294 keyboard@0 {
295 reg = <0>;
296 compatible = "pnpPNP,303";
297 };
298
299 mouse@1 {
300 reg = <1>;
301 compatible = "pnpPNP,f03";
302 };
303 };
304
305 rtc@70 {
306 compatible =
307 "pnpPNP,b00";
308 reg = <1 0x70 2>;
309 };
310
311 gpio@400 {
312 reg = <1 0x400 0x80>;
313 };
314 };
315 };
316 };
317
318 };
319
320 pci1: pcie@fffe09000 {
321 reg = <0x0f 0xffe09000 0x0 0x1000>;
322 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
323 0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
324
325 pcie@0 {
326 ranges = <0x02000000 0x0 0xe0000000
327 0x02000000 0x0 0xe0000000
328 0x0 0x20000000
329
330 0x01000000 0x0 0x00000000
331 0x01000000 0x0 0x00000000
332 0x0 0x00010000>;
333 };
334 };
335};
336
337/include/ "mpc8641si-post.dtsi"
1/*
2 * MPC8641 HPCN Device Tree Source
3 *
4 * Copyright 2008-2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "mpc8641si-pre.dtsi"
13
14/ {
15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 memory {
21 device_type = "memory";
22 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
23 };
24
25 lbc: localbus@fffe05000 {
26 reg = <0x0f 0xffe05000 0x0 0x1000>;
27
28 ranges = <0 0 0xf 0xef800000 0x00800000
29 2 0 0xf 0xffdf8000 0x00008000
30 3 0 0xf 0xffdf0000 0x00008000>;
31
32 flash@0,0 {
33 compatible = "cfi-flash";
34 reg = <0 0 0x00800000>;
35 bank-width = <2>;
36 device-width = <2>;
37 #address-cells = <1>;
38 #size-cells = <1>;
39 partition@0 {
40 label = "kernel";
41 reg = <0x00000000 0x00300000>;
42 };
43 partition@300000 {
44 label = "firmware b";
45 reg = <0x00300000 0x00100000>;
46 read-only;
47 };
48 partition@400000 {
49 label = "fs";
50 reg = <0x00400000 0x00300000>;
51 };
52 partition@700000 {
53 label = "firmware a";
54 reg = <0x00700000 0x00100000>;
55 read-only;
56 };
57 };
58 };
59
60 soc: soc8641@fffe00000 {
61 ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
62
63 enet0: ethernet@24000 {
64 tbi-handle = <&tbi0>;
65 phy-handle = <&phy0>;
66 phy-connection-type = "rgmii-id";
67 };
68
69 mdio@24520 {
70 phy0: ethernet-phy@0 {
71 interrupts = <10 1 0 0>;
72 reg = <0>;
73 };
74 phy1: ethernet-phy@1 {
75 interrupts = <10 1 0 0>;
76 reg = <1>;
77 };
78 phy2: ethernet-phy@2 {
79 interrupts = <10 1 0 0>;
80 reg = <2>;
81 };
82 phy3: ethernet-phy@3 {
83 interrupts = <10 1 0 0>;
84 reg = <3>;
85 };
86 tbi0: tbi-phy@11 {
87 reg = <0x11>;
88 device_type = "tbi-phy";
89 };
90 };
91
92 enet1: ethernet@25000 {
93 tbi-handle = <&tbi1>;
94 phy-handle = <&phy1>;
95 phy-connection-type = "rgmii-id";
96 };
97
98 mdio@25520 {
99 tbi1: tbi-phy@11 {
100 reg = <0x11>;
101 device_type = "tbi-phy";
102 };
103 };
104
105 enet2: ethernet@26000 {
106 tbi-handle = <&tbi2>;
107 phy-handle = <&phy2>;
108 phy-connection-type = "rgmii-id";
109 };
110
111 mdio@26520 {
112 tbi2: tbi-phy@11 {
113 reg = <0x11>;
114 device_type = "tbi-phy";
115 };
116 };
117
118 enet3: ethernet@27000 {
119 tbi-handle = <&tbi3>;
120 phy-handle = <&phy3>;
121 phy-connection-type = "rgmii-id";
122 };
123
124 mdio@27520 {
125 tbi3: tbi-phy@11 {
126 reg = <0x11>;
127 device_type = "tbi-phy";
128 };
129 };
130 };
131
132 pci0: pcie@fffe08000 {
133 reg = <0x0f 0xffe08000 0x0 0x1000>;
134 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
135 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
136 interrupt-map-mask = <0xff00 0 0 7>;
137 interrupt-map = <
138 /* IDSEL 0x11 func 0 - PCI slot 1 */
139 0x8800 0 0 1 &mpic 2 1
140 0x8800 0 0 2 &mpic 3 1
141 0x8800 0 0 3 &mpic 4 1
142 0x8800 0 0 4 &mpic 1 1
143
144 /* IDSEL 0x11 func 1 - PCI slot 1 */
145 0x8900 0 0 1 &mpic 2 1
146 0x8900 0 0 2 &mpic 3 1
147 0x8900 0 0 3 &mpic 4 1
148 0x8900 0 0 4 &mpic 1 1
149
150 /* IDSEL 0x11 func 2 - PCI slot 1 */
151 0x8a00 0 0 1 &mpic 2 1
152 0x8a00 0 0 2 &mpic 3 1
153 0x8a00 0 0 3 &mpic 4 1
154 0x8a00 0 0 4 &mpic 1 1
155
156 /* IDSEL 0x11 func 3 - PCI slot 1 */
157 0x8b00 0 0 1 &mpic 2 1
158 0x8b00 0 0 2 &mpic 3 1
159 0x8b00 0 0 3 &mpic 4 1
160 0x8b00 0 0 4 &mpic 1 1
161
162 /* IDSEL 0x11 func 4 - PCI slot 1 */
163 0x8c00 0 0 1 &mpic 2 1
164 0x8c00 0 0 2 &mpic 3 1
165 0x8c00 0 0 3 &mpic 4 1
166 0x8c00 0 0 4 &mpic 1 1
167
168 /* IDSEL 0x11 func 5 - PCI slot 1 */
169 0x8d00 0 0 1 &mpic 2 1
170 0x8d00 0 0 2 &mpic 3 1
171 0x8d00 0 0 3 &mpic 4 1
172 0x8d00 0 0 4 &mpic 1 1
173
174 /* IDSEL 0x11 func 6 - PCI slot 1 */
175 0x8e00 0 0 1 &mpic 2 1
176 0x8e00 0 0 2 &mpic 3 1
177 0x8e00 0 0 3 &mpic 4 1
178 0x8e00 0 0 4 &mpic 1 1
179
180 /* IDSEL 0x11 func 7 - PCI slot 1 */
181 0x8f00 0 0 1 &mpic 2 1
182 0x8f00 0 0 2 &mpic 3 1
183 0x8f00 0 0 3 &mpic 4 1
184 0x8f00 0 0 4 &mpic 1 1
185
186 /* IDSEL 0x12 func 0 - PCI slot 2 */
187 0x9000 0 0 1 &mpic 3 1
188 0x9000 0 0 2 &mpic 4 1
189 0x9000 0 0 3 &mpic 1 1
190 0x9000 0 0 4 &mpic 2 1
191
192 /* IDSEL 0x12 func 1 - PCI slot 2 */
193 0x9100 0 0 1 &mpic 3 1
194 0x9100 0 0 2 &mpic 4 1
195 0x9100 0 0 3 &mpic 1 1
196 0x9100 0 0 4 &mpic 2 1
197
198 /* IDSEL 0x12 func 2 - PCI slot 2 */
199 0x9200 0 0 1 &mpic 3 1
200 0x9200 0 0 2 &mpic 4 1
201 0x9200 0 0 3 &mpic 1 1
202 0x9200 0 0 4 &mpic 2 1
203
204 /* IDSEL 0x12 func 3 - PCI slot 2 */
205 0x9300 0 0 1 &mpic 3 1
206 0x9300 0 0 2 &mpic 4 1
207 0x9300 0 0 3 &mpic 1 1
208 0x9300 0 0 4 &mpic 2 1
209
210 /* IDSEL 0x12 func 4 - PCI slot 2 */
211 0x9400 0 0 1 &mpic 3 1
212 0x9400 0 0 2 &mpic 4 1
213 0x9400 0 0 3 &mpic 1 1
214 0x9400 0 0 4 &mpic 2 1
215
216 /* IDSEL 0x12 func 5 - PCI slot 2 */
217 0x9500 0 0 1 &mpic 3 1
218 0x9500 0 0 2 &mpic 4 1
219 0x9500 0 0 3 &mpic 1 1
220 0x9500 0 0 4 &mpic 2 1
221
222 /* IDSEL 0x12 func 6 - PCI slot 2 */
223 0x9600 0 0 1 &mpic 3 1
224 0x9600 0 0 2 &mpic 4 1
225 0x9600 0 0 3 &mpic 1 1
226 0x9600 0 0 4 &mpic 2 1
227
228 /* IDSEL 0x12 func 7 - PCI slot 2 */
229 0x9700 0 0 1 &mpic 3 1
230 0x9700 0 0 2 &mpic 4 1
231 0x9700 0 0 3 &mpic 1 1
232 0x9700 0 0 4 &mpic 2 1
233
234 // IDSEL 0x1c USB
235 0xe000 0 0 1 &i8259 12 2
236 0xe100 0 0 2 &i8259 9 2
237 0xe200 0 0 3 &i8259 10 2
238 0xe300 0 0 4 &i8259 11 2
239
240 // IDSEL 0x1d Audio
241 0xe800 0 0 1 &i8259 6 2
242
243 // IDSEL 0x1e Legacy
244 0xf000 0 0 1 &i8259 7 2
245 0xf100 0 0 1 &i8259 7 2
246
247 // IDSEL 0x1f IDE/SATA
248 0xf800 0 0 1 &i8259 14 2
249 0xf900 0 0 1 &i8259 5 2
250 >;
251
252 pcie@0 {
253 ranges = <0x02000000 0x0 0xe0000000
254 0x02000000 0x0 0xe0000000
255 0x0 0x20000000
256
257 0x01000000 0x0 0x00000000
258 0x01000000 0x0 0x00000000
259 0x0 0x00010000>;
260 uli1575@0 {
261 reg = <0 0 0 0 0>;
262 #size-cells = <2>;
263 #address-cells = <3>;
264 ranges = <0x02000000 0x0 0xe0000000
265 0x02000000 0x0 0xe0000000
266 0x0 0x20000000
267 0x01000000 0x0 0x00000000
268 0x01000000 0x0 0x00000000
269 0x0 0x00010000>;
270 isa@1e {
271 device_type = "isa";
272 #size-cells = <1>;
273 #address-cells = <2>;
274 reg = <0xf000 0 0 0 0>;
275 ranges = <1 0 0x01000000 0 0
276 0x00001000>;
277 interrupt-parent = <&i8259>;
278
279 i8259: interrupt-controller@20 {
280 reg = <1 0x20 2
281 1 0xa0 2
282 1 0x4d0 2>;
283 interrupt-controller;
284 device_type = "interrupt-controller";
285 #address-cells = <0>;
286 #interrupt-cells = <2>;
287 compatible = "chrp,iic";
288 interrupts = <9 2 0 0>;
289 };
290
291 i8042@60 {
292 #size-cells = <0>;
293 #address-cells = <1>;
294 reg = <1 0x60 1 1 0x64 1>;
295 interrupts = <1 3 12 3>;
296 interrupt-parent = <&i8259>;
297
298 keyboard@0 {
299 reg = <0>;
300 compatible = "pnpPNP,303";
301 };
302
303 mouse@1 {
304 reg = <1>;
305 compatible = "pnpPNP,f03";
306 };
307 };
308
309 rtc@70 {
310 compatible =
311 "pnpPNP,b00";
312 reg = <1 0x70 2>;
313 };
314
315 gpio@400 {
316 reg = <1 0x400 0x80>;
317 };
318 };
319 };
320 };
321
322 };
323
324 pci1: pcie@fffe09000 {
325 reg = <0x0f 0xffe09000 0x0 0x1000>;
326 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
327 0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
328
329 pcie@0 {
330 ranges = <0x02000000 0x0 0xe0000000
331 0x02000000 0x0 0xe0000000
332 0x0 0x20000000
333
334 0x01000000 0x0 0x00000000
335 0x01000000 0x0 0x00000000
336 0x0 0x00010000>;
337 };
338 };
339};
340
341/include/ "mpc8641si-post.dtsi"