1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 * Copyright (C) 2014 Imagination Technologies
 4 * Author: Paul Burton <paul.burton@mips.com>
 
 
 
 
 
 5 */
 6
 7#ifndef __MIPS_ASM_PM_CPS_H__
 8#define __MIPS_ASM_PM_CPS_H__
 9
10/*
11 * The CM & CPC can only handle coherence & power control on a per-core basis,
12 * thus in an MT system the VP(E)s within each core are coupled and can only
13 * enter or exit states requiring CM or CPC assistance in unison.
14 */
15#if defined(CONFIG_CPU_MIPSR6)
16# define coupled_coherence cpu_has_vp
17#elif defined(CONFIG_MIPS_MT)
18# define coupled_coherence cpu_has_mipsmt
19#else
20# define coupled_coherence 0
21#endif
22
23/* Enumeration of possible PM states */
24enum cps_pm_state {
25	CPS_PM_NC_WAIT,		/* MIPS wait instruction, non-coherent */
26	CPS_PM_CLOCK_GATED,	/* Core clock gated */
27	CPS_PM_POWER_GATED,	/* Core power gated */
28	CPS_PM_STATE_COUNT,
29};
30
31/**
32 * cps_pm_support_state - determine whether the system supports a PM state
33 * @state: the state to test for support
34 *
35 * Returns true if the system supports the given state, otherwise false.
36 */
37extern bool cps_pm_support_state(enum cps_pm_state state);
38
39/**
40 * cps_pm_enter_state - enter a PM state
41 * @state: the state to enter
42 *
43 * Enter the given PM state. If coupled_coherence is non-zero then it is
44 * expected that this function be called at approximately the same time on
45 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
46 */
47extern int cps_pm_enter_state(enum cps_pm_state state);
48
49#endif /* __MIPS_ASM_PM_CPS_H__ */

 
 1/*
 2 * Copyright (C) 2014 Imagination Technologies
 3 * Author: Paul Burton <paul.burton@mips.com>
 4 *
 5 * This program is free software; you can redistribute it and/or modify it
 6 * under the terms of the GNU General Public License as published by the
 7 * Free Software Foundation;  either version 2 of the  License, or (at your
 8 * option) any later version.
 9 */
10
11#ifndef __MIPS_ASM_PM_CPS_H__
12#define __MIPS_ASM_PM_CPS_H__
13
14/*
15 * The CM & CPC can only handle coherence & power control on a per-core basis,
16 * thus in an MT system the VP(E)s within each core are coupled and can only
17 * enter or exit states requiring CM or CPC assistance in unison.
18 */
19#if defined(CONFIG_CPU_MIPSR6)
20# define coupled_coherence cpu_has_vp
21#elif defined(CONFIG_MIPS_MT)
22# define coupled_coherence cpu_has_mipsmt
23#else
24# define coupled_coherence 0
25#endif
26
27/* Enumeration of possible PM states */
28enum cps_pm_state {
29	CPS_PM_NC_WAIT,		/* MIPS wait instruction, non-coherent */
30	CPS_PM_CLOCK_GATED,	/* Core clock gated */
31	CPS_PM_POWER_GATED,	/* Core power gated */
32	CPS_PM_STATE_COUNT,
33};
34
35/**
36 * cps_pm_support_state - determine whether the system supports a PM state
37 * @state: the state to test for support
38 *
39 * Returns true if the system supports the given state, otherwise false.
40 */
41extern bool cps_pm_support_state(enum cps_pm_state state);
42
43/**
44 * cps_pm_enter_state - enter a PM state
45 * @state: the state to enter
46 *
47 * Enter the given PM state. If coupled_coherence is non-zero then it is
48 * expected that this function be called at approximately the same time on
49 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
50 */
51extern int cps_pm_enter_state(enum cps_pm_state state);
52
53#endif /* __MIPS_ASM_PM_CPS_H__ */