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1/*
2 * linux/arch/arm/mach-omap2/timer.c
3 *
4 * OMAP2 GP timer support.
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 *
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
11 *
12 * Original driver:
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
17 *
18 * Some parts based off of TI's 24xx code:
19 *
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
21 *
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24 *
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
27 * for more details.
28 */
29#include <linux/clk.h>
30#include <linux/clocksource.h>
31
32#include "soc.h"
33#include "common.h"
34#include "control.h"
35#include "omap-secure.h"
36
37#define REALTIME_COUNTER_BASE 0x48243200
38#define INCREMENTER_NUMERATOR_OFFSET 0x10
39#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
40#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
41
42static unsigned long arch_timer_freq;
43
44void set_cntfreq(void)
45{
46 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
47}
48
49/*
50 * The realtime counter also called master counter, is a free-running
51 * counter, which is related to real time. It produces the count used
52 * by the CPU local timer peripherals in the MPU cluster. The timer counts
53 * at a rate of 6.144 MHz. Because the device operates on different clocks
54 * in different power modes, the master counter shifts operation between
55 * clocks, adjusting the increment per clock in hardware accordingly to
56 * maintain a constant count rate.
57 */
58static void __init realtime_counter_init(void)
59{
60 void __iomem *base;
61 static struct clk *sys_clk;
62 unsigned long rate;
63 unsigned int reg;
64 unsigned long long num, den;
65
66 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
67 if (!base) {
68 pr_err("%s: ioremap failed\n", __func__);
69 return;
70 }
71 sys_clk = clk_get(NULL, "sys_clkin");
72 if (IS_ERR(sys_clk)) {
73 pr_err("%s: failed to get system clock handle\n", __func__);
74 iounmap(base);
75 return;
76 }
77
78 rate = clk_get_rate(sys_clk);
79
80 if (soc_is_dra7xx()) {
81 /*
82 * Errata i856 says the 32.768KHz crystal does not start at
83 * power on, so the CPU falls back to an emulated 32KHz clock
84 * based on sysclk / 610 instead. This causes the master counter
85 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
86 * (OR sysclk * 75 / 244)
87 *
88 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
89 * Of course any board built without a populated 32.768KHz
90 * crystal would also need this fix even if the CPU is fixed
91 * later.
92 *
93 * Either case can be detected by using the two speedselect bits
94 * If they are not 0, then the 32.768KHz clock driving the
95 * coarse counter that corrects the fine counter every time it
96 * ticks is actually rate/610 rather than 32.768KHz and we
97 * should compensate to avoid the 570ppm (at 20MHz, much worse
98 * at other rates) too fast system time.
99 */
100 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
101 if (reg & DRA7_SPEEDSELECT_MASK) {
102 num = 75;
103 den = 244;
104 goto sysclk1_based;
105 }
106 }
107
108 /* Numerator/denumerator values refer TRM Realtime Counter section */
109 switch (rate) {
110 case 12000000:
111 num = 64;
112 den = 125;
113 break;
114 case 13000000:
115 num = 768;
116 den = 1625;
117 break;
118 case 19200000:
119 num = 8;
120 den = 25;
121 break;
122 case 20000000:
123 num = 192;
124 den = 625;
125 break;
126 case 26000000:
127 num = 384;
128 den = 1625;
129 break;
130 case 27000000:
131 num = 256;
132 den = 1125;
133 break;
134 case 38400000:
135 default:
136 /* Program it for 38.4 MHz */
137 num = 4;
138 den = 25;
139 break;
140 }
141
142sysclk1_based:
143 /* Program numerator and denumerator registers */
144 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
145 NUMERATOR_DENUMERATOR_MASK;
146 reg |= num;
147 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
148
149 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
150 NUMERATOR_DENUMERATOR_MASK;
151 reg |= den;
152 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
153
154 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
155 set_cntfreq();
156
157 iounmap(base);
158}
159
160void __init omap5_realtime_timer_init(void)
161{
162 omap_clk_init();
163 realtime_counter_init();
164
165 timer_probe();
166}
1/*
2 * linux/arch/arm/mach-omap2/timer.c
3 *
4 * OMAP2 GP timer support.
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 *
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
11 *
12 * Original driver:
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
17 *
18 * Some parts based off of TI's 24xx code:
19 *
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
21 *
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
24 *
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
27 * for more details.
28 */
29#include <linux/init.h>
30#include <linux/time.h>
31#include <linux/interrupt.h>
32#include <linux/err.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
35#include <linux/irq.h>
36#include <linux/clocksource.h>
37#include <linux/clockchips.h>
38#include <linux/slab.h>
39#include <linux/of.h>
40#include <linux/of_address.h>
41#include <linux/of_irq.h>
42#include <linux/platform_device.h>
43#include <linux/platform_data/dmtimer-omap.h>
44#include <linux/sched_clock.h>
45
46#include <asm/mach/time.h>
47#include <asm/smp_twd.h>
48
49#include "omap_hwmod.h"
50#include "omap_device.h"
51#include <plat/counter-32k.h>
52#include <clocksource/timer-ti-dm.h>
53#include "omap-pm.h"
54
55#include "soc.h"
56#include "common.h"
57#include "control.h"
58#include "powerdomain.h"
59#include "omap-secure.h"
60
61#define REALTIME_COUNTER_BASE 0x48243200
62#define INCREMENTER_NUMERATOR_OFFSET 0x10
63#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
64#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
65
66/* Clockevent code */
67
68static struct omap_dm_timer clkev;
69static struct clock_event_device clockevent_gpt;
70
71/* Clockevent hwmod for am335x and am437x suspend */
72static struct omap_hwmod *clockevent_gpt_hwmod;
73
74#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
75static unsigned long arch_timer_freq;
76
77void set_cntfreq(void)
78{
79 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
80}
81#endif
82
83static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
84{
85 struct clock_event_device *evt = &clockevent_gpt;
86
87 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
88
89 evt->event_handler(evt);
90 return IRQ_HANDLED;
91}
92
93static struct irqaction omap2_gp_timer_irq = {
94 .name = "gp_timer",
95 .flags = IRQF_TIMER | IRQF_IRQPOLL,
96 .handler = omap2_gp_timer_interrupt,
97};
98
99static int omap2_gp_timer_set_next_event(unsigned long cycles,
100 struct clock_event_device *evt)
101{
102 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
103 0xffffffff - cycles, OMAP_TIMER_POSTED);
104
105 return 0;
106}
107
108static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
109{
110 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
111 return 0;
112}
113
114static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
115{
116 u32 period;
117
118 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
119
120 period = clkev.rate / HZ;
121 period -= 1;
122 /* Looks like we need to first set the load value separately */
123 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
124 OMAP_TIMER_POSTED);
125 __omap_dm_timer_load_start(&clkev,
126 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
127 0xffffffff - period, OMAP_TIMER_POSTED);
128 return 0;
129}
130
131static void omap_clkevt_idle(struct clock_event_device *unused)
132{
133 if (!clockevent_gpt_hwmod)
134 return;
135
136 omap_hwmod_idle(clockevent_gpt_hwmod);
137}
138
139static void omap_clkevt_unidle(struct clock_event_device *unused)
140{
141 if (!clockevent_gpt_hwmod)
142 return;
143
144 omap_hwmod_enable(clockevent_gpt_hwmod);
145 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
146}
147
148static struct clock_event_device clockevent_gpt = {
149 .features = CLOCK_EVT_FEAT_PERIODIC |
150 CLOCK_EVT_FEAT_ONESHOT,
151 .rating = 300,
152 .set_next_event = omap2_gp_timer_set_next_event,
153 .set_state_shutdown = omap2_gp_timer_shutdown,
154 .set_state_periodic = omap2_gp_timer_set_periodic,
155 .set_state_oneshot = omap2_gp_timer_shutdown,
156 .tick_resume = omap2_gp_timer_shutdown,
157};
158
159static const struct of_device_id omap_timer_match[] __initconst = {
160 { .compatible = "ti,omap2420-timer", },
161 { .compatible = "ti,omap3430-timer", },
162 { .compatible = "ti,omap4430-timer", },
163 { .compatible = "ti,omap5430-timer", },
164 { .compatible = "ti,dm814-timer", },
165 { .compatible = "ti,dm816-timer", },
166 { .compatible = "ti,am335x-timer", },
167 { .compatible = "ti,am335x-timer-1ms", },
168 { }
169};
170
171/**
172 * omap_get_timer_dt - get a timer using device-tree
173 * @match - device-tree match structure for matching a device type
174 * @property - optional timer property to match
175 *
176 * Helper function to get a timer during early boot using device-tree for use
177 * as kernel system timer. Optionally, the property argument can be used to
178 * select a timer with a specific property. Once a timer is found then mark
179 * the timer node in device-tree as disabled, to prevent the kernel from
180 * registering this timer as a platform device and so no one else can use it.
181 */
182static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
183 const char *property)
184{
185 struct device_node *np;
186
187 for_each_matching_node(np, match) {
188 if (!of_device_is_available(np))
189 continue;
190
191 if (property && !of_get_property(np, property, NULL))
192 continue;
193
194 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
195 of_get_property(np, "ti,timer-dsp", NULL) ||
196 of_get_property(np, "ti,timer-pwm", NULL) ||
197 of_get_property(np, "ti,timer-secure", NULL)))
198 continue;
199
200 if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
201 struct property *prop;
202
203 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
204 if (!prop)
205 return NULL;
206 prop->name = "status";
207 prop->value = "disabled";
208 prop->length = strlen(prop->value);
209 of_add_property(np, prop);
210 }
211 return np;
212 }
213
214 return NULL;
215}
216
217/**
218 * omap_dmtimer_init - initialisation function when device tree is used
219 *
220 * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
221 * cannot be used by the kernel as they are reserved. Therefore, to prevent the
222 * kernel registering these devices remove them dynamically from the device
223 * tree on boot.
224 */
225static void __init omap_dmtimer_init(void)
226{
227 struct device_node *np;
228
229 if (!cpu_is_omap34xx() && !soc_is_dra7xx())
230 return;
231
232 /* If we are a secure device, remove any secure timer nodes */
233 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
234 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
235 of_node_put(np);
236 }
237}
238
239/**
240 * omap_dm_timer_get_errata - get errata flags for a timer
241 *
242 * Get the timer errata flags that are specific to the OMAP device being used.
243 */
244static u32 __init omap_dm_timer_get_errata(void)
245{
246 if (cpu_is_omap24xx())
247 return 0;
248
249 return OMAP_TIMER_ERRATA_I103_I767;
250}
251
252static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
253 const char *fck_source,
254 const char *property,
255 const char **timer_name,
256 int posted)
257{
258 const char *oh_name = NULL;
259 struct device_node *np;
260 struct omap_hwmod *oh;
261 struct clk *src;
262 int r = 0;
263
264 np = omap_get_timer_dt(omap_timer_match, property);
265 if (!np)
266 return -ENODEV;
267
268 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
269 if (!oh_name)
270 return -ENODEV;
271
272 timer->irq = irq_of_parse_and_map(np, 0);
273 if (!timer->irq)
274 return -ENXIO;
275
276 timer->io_base = of_iomap(np, 0);
277
278 timer->fclk = of_clk_get_by_name(np, "fck");
279
280 of_node_put(np);
281
282 oh = omap_hwmod_lookup(oh_name);
283 if (!oh)
284 return -ENODEV;
285
286 *timer_name = oh->name;
287
288 if (!timer->io_base)
289 return -ENXIO;
290
291 omap_hwmod_setup_one(oh_name);
292
293 /* After the dmtimer is using hwmod these clocks won't be needed */
294 if (IS_ERR_OR_NULL(timer->fclk))
295 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
296 if (IS_ERR(timer->fclk))
297 return PTR_ERR(timer->fclk);
298
299 src = clk_get(NULL, fck_source);
300 if (IS_ERR(src))
301 return PTR_ERR(src);
302
303 WARN(clk_set_parent(timer->fclk, src) < 0,
304 "Cannot set timer parent clock, no PLL clock driver?");
305
306 clk_put(src);
307
308 omap_hwmod_enable(oh);
309 __omap_dm_timer_init_regs(timer);
310
311 if (posted)
312 __omap_dm_timer_enable_posted(timer);
313
314 /* Check that the intended posted configuration matches the actual */
315 if (posted != timer->posted)
316 return -EINVAL;
317
318 timer->rate = clk_get_rate(timer->fclk);
319 timer->reserved = 1;
320
321 return r;
322}
323
324#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
325void tick_broadcast(const struct cpumask *mask)
326{
327}
328#endif
329
330static void __init omap2_gp_clockevent_init(int gptimer_id,
331 const char *fck_source,
332 const char *property)
333{
334 int res;
335
336 clkev.id = gptimer_id;
337 clkev.errata = omap_dm_timer_get_errata();
338
339 /*
340 * For clock-event timers we never read the timer counter and
341 * so we are not impacted by errata i103 and i767. Therefore,
342 * we can safely ignore this errata for clock-event timers.
343 */
344 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
345
346 res = omap_dm_timer_init_one(&clkev, fck_source, property,
347 &clockevent_gpt.name, OMAP_TIMER_POSTED);
348 BUG_ON(res);
349
350 omap2_gp_timer_irq.dev_id = &clkev;
351 setup_irq(clkev.irq, &omap2_gp_timer_irq);
352
353 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
354
355 clockevent_gpt.cpumask = cpu_possible_mask;
356 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
357 clockevents_config_and_register(&clockevent_gpt, clkev.rate,
358 3, /* Timer internal resynch latency */
359 0xffffffff);
360
361 if (soc_is_am33xx() || soc_is_am43xx()) {
362 clockevent_gpt.suspend = omap_clkevt_idle;
363 clockevent_gpt.resume = omap_clkevt_unidle;
364
365 clockevent_gpt_hwmod =
366 omap_hwmod_lookup(clockevent_gpt.name);
367 }
368
369 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
370 clkev.rate);
371}
372
373/* Clocksource code */
374static struct omap_dm_timer clksrc;
375static bool use_gptimer_clksrc __initdata;
376
377/*
378 * clocksource
379 */
380static u64 clocksource_read_cycles(struct clocksource *cs)
381{
382 return (u64)__omap_dm_timer_read_counter(&clksrc,
383 OMAP_TIMER_NONPOSTED);
384}
385
386static struct clocksource clocksource_gpt = {
387 .rating = 300,
388 .read = clocksource_read_cycles,
389 .mask = CLOCKSOURCE_MASK(32),
390 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
391};
392
393static u64 notrace dmtimer_read_sched_clock(void)
394{
395 if (clksrc.reserved)
396 return __omap_dm_timer_read_counter(&clksrc,
397 OMAP_TIMER_NONPOSTED);
398
399 return 0;
400}
401
402static const struct of_device_id omap_counter_match[] __initconst = {
403 { .compatible = "ti,omap-counter32k", },
404 { }
405};
406
407/* Setup free-running counter for clocksource */
408static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
409{
410 int ret;
411 struct device_node *np = NULL;
412 struct omap_hwmod *oh;
413 const char *oh_name = "counter_32k";
414
415 /*
416 * See if the 32kHz counter is supported.
417 */
418 np = omap_get_timer_dt(omap_counter_match, NULL);
419 if (!np)
420 return -ENODEV;
421
422 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
423 if (!oh_name)
424 return -ENODEV;
425
426 /*
427 * First check hwmod data is available for sync32k counter
428 */
429 oh = omap_hwmod_lookup(oh_name);
430 if (!oh || oh->slaves_cnt == 0)
431 return -ENODEV;
432
433 omap_hwmod_setup_one(oh_name);
434
435 ret = omap_hwmod_enable(oh);
436 if (ret) {
437 pr_warn("%s: failed to enable counter_32k module (%d)\n",
438 __func__, ret);
439 return ret;
440 }
441
442 return ret;
443}
444
445static void __init omap2_gptimer_clocksource_init(int gptimer_id,
446 const char *fck_source,
447 const char *property)
448{
449 int res;
450
451 clksrc.id = gptimer_id;
452 clksrc.errata = omap_dm_timer_get_errata();
453
454 res = omap_dm_timer_init_one(&clksrc, fck_source, property,
455 &clocksource_gpt.name,
456 OMAP_TIMER_NONPOSTED);
457 BUG_ON(res);
458
459 __omap_dm_timer_load_start(&clksrc,
460 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
461 OMAP_TIMER_NONPOSTED);
462 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
463
464 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
465 pr_err("Could not register clocksource %s\n",
466 clocksource_gpt.name);
467 else
468 pr_info("OMAP clocksource: %s at %lu Hz\n",
469 clocksource_gpt.name, clksrc.rate);
470}
471
472static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
473 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
474 const char *clksrc_prop, bool gptimer)
475{
476 omap_clk_init();
477 omap_dmtimer_init();
478 omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
479
480 /* Enable the use of clocksource="gp_timer" kernel parameter */
481 if (use_gptimer_clksrc || gptimer)
482 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
483 clksrc_prop);
484 else
485 omap2_sync32k_clocksource_init();
486}
487
488void __init omap_init_time(void)
489{
490 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
491 2, "timer_sys_ck", NULL, false);
492
493 timer_probe();
494}
495
496#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
497void __init omap3_secure_sync32k_timer_init(void)
498{
499 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
500 2, "timer_sys_ck", NULL, false);
501
502 timer_probe();
503}
504#endif /* CONFIG_ARCH_OMAP3 */
505
506#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
507 defined(CONFIG_SOC_AM43XX)
508void __init omap3_gptimer_timer_init(void)
509{
510 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
511 1, "timer_sys_ck", "ti,timer-alwon", true);
512 if (of_have_populated_dt())
513 timer_probe();
514}
515#endif
516
517#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
518 defined(CONFIG_SOC_DRA7XX)
519static void __init omap4_sync32k_timer_init(void)
520{
521 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
522 2, "sys_clkin_ck", NULL, false);
523}
524
525void __init omap4_local_timer_init(void)
526{
527 omap4_sync32k_timer_init();
528 timer_probe();
529}
530#endif
531
532#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
533
534/*
535 * The realtime counter also called master counter, is a free-running
536 * counter, which is related to real time. It produces the count used
537 * by the CPU local timer peripherals in the MPU cluster. The timer counts
538 * at a rate of 6.144 MHz. Because the device operates on different clocks
539 * in different power modes, the master counter shifts operation between
540 * clocks, adjusting the increment per clock in hardware accordingly to
541 * maintain a constant count rate.
542 */
543static void __init realtime_counter_init(void)
544{
545#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
546 void __iomem *base;
547 static struct clk *sys_clk;
548 unsigned long rate;
549 unsigned int reg;
550 unsigned long long num, den;
551
552 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
553 if (!base) {
554 pr_err("%s: ioremap failed\n", __func__);
555 return;
556 }
557 sys_clk = clk_get(NULL, "sys_clkin");
558 if (IS_ERR(sys_clk)) {
559 pr_err("%s: failed to get system clock handle\n", __func__);
560 iounmap(base);
561 return;
562 }
563
564 rate = clk_get_rate(sys_clk);
565
566 if (soc_is_dra7xx()) {
567 /*
568 * Errata i856 says the 32.768KHz crystal does not start at
569 * power on, so the CPU falls back to an emulated 32KHz clock
570 * based on sysclk / 610 instead. This causes the master counter
571 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
572 * (OR sysclk * 75 / 244)
573 *
574 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
575 * Of course any board built without a populated 32.768KHz
576 * crystal would also need this fix even if the CPU is fixed
577 * later.
578 *
579 * Either case can be detected by using the two speedselect bits
580 * If they are not 0, then the 32.768KHz clock driving the
581 * coarse counter that corrects the fine counter every time it
582 * ticks is actually rate/610 rather than 32.768KHz and we
583 * should compensate to avoid the 570ppm (at 20MHz, much worse
584 * at other rates) too fast system time.
585 */
586 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
587 if (reg & DRA7_SPEEDSELECT_MASK) {
588 num = 75;
589 den = 244;
590 goto sysclk1_based;
591 }
592 }
593
594 /* Numerator/denumerator values refer TRM Realtime Counter section */
595 switch (rate) {
596 case 12000000:
597 num = 64;
598 den = 125;
599 break;
600 case 13000000:
601 num = 768;
602 den = 1625;
603 break;
604 case 19200000:
605 num = 8;
606 den = 25;
607 break;
608 case 20000000:
609 num = 192;
610 den = 625;
611 break;
612 case 26000000:
613 num = 384;
614 den = 1625;
615 break;
616 case 27000000:
617 num = 256;
618 den = 1125;
619 break;
620 case 38400000:
621 default:
622 /* Program it for 38.4 MHz */
623 num = 4;
624 den = 25;
625 break;
626 }
627
628sysclk1_based:
629 /* Program numerator and denumerator registers */
630 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
631 NUMERATOR_DENUMERATOR_MASK;
632 reg |= num;
633 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
634
635 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
636 NUMERATOR_DENUMERATOR_MASK;
637 reg |= den;
638 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
639
640 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
641 set_cntfreq();
642
643 iounmap(base);
644#endif
645}
646
647void __init omap5_realtime_timer_init(void)
648{
649 omap4_sync32k_timer_init();
650 realtime_counter_init();
651
652 timer_probe();
653}
654#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
655
656/**
657 * omap2_override_clocksource - clocksource override with user configuration
658 *
659 * Allows user to override default clocksource, using kernel parameter
660 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
661 *
662 * Note that, here we are using same standard kernel parameter "clocksource=",
663 * and not introducing any OMAP specific interface.
664 */
665static int __init omap2_override_clocksource(char *str)
666{
667 if (!str)
668 return 0;
669 /*
670 * For OMAP architecture, we only have two options
671 * - sync_32k (default)
672 * - gp_timer (sys_clk based)
673 */
674 if (!strcmp(str, "gp_timer"))
675 use_gptimer_clksrc = true;
676
677 return 0;
678}
679early_param("clocksource", omap2_override_clocksource);