1// SPDX-License-Identifier: GPL-2.0+
 2/*
 3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
 
 
 
 
 
 
 
 
 
 
 
 
 
 4 */
 5
 6/dts-v1/;
 7/* First 4KB has trampoline code for secondary cores. */
 8/memreserve/ 0x00000000 0x0001000;
 9#include "socfpga.dtsi"
10
11/ {
12	soc {
13		clkmgr@ffd04000 {
14			clocks {
15				osc1 {
16					clock-frequency = <25000000>;
17				};
18			};
19		};
20
21		mmc0: mmc@ff704000 {
22			broken-cd;
23			bus-width = <4>;
24			cap-mmc-highspeed;
25			cap-sd-highspeed;
26			clk-phase-sd-hs = <0>, <135>;
27		};
28
29		sysmgr@ffd08000 {
30			cpu1-start-addr = <0xffd080c4>;
31		};
32	};
33};
34
35&watchdog0 {
36	status = "okay";
37};

 
 1/*
 2 *  Copyright (C) 2012 Altera Corporation <www.altera.com>
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License as published by
 6 * the Free Software Foundation; either version 2 of the License, or
 7 * (at your option) any later version.
 8 *
 9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/dts-v1/;
19/* First 4KB has trampoline code for secondary cores. */
20/memreserve/ 0x00000000 0x0001000;
21#include "socfpga.dtsi"
22
23/ {
24	soc {
25		clkmgr@ffd04000 {
26			clocks {
27				osc1 {
28					clock-frequency = <25000000>;
29				};
30			};
31		};
32
33		mmc0: dwmmc0@ff704000 {
34			broken-cd;
35			bus-width = <4>;
36			cap-mmc-highspeed;
37			cap-sd-highspeed;
 
38		};
39
40		sysmgr@ffd08000 {
41			cpu1-start-addr = <0xffd080c4>;
42		};
43	};
44};
45
46&watchdog0 {
47	status = "okay";
48};