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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car V2H (R8A77920) SoC
4 *
5 * Copyright (C) 2016 Cogent Embedded Inc.
6 */
7
8#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/power/r8a7792-sysc.h>
12
13/ {
14 compatible = "renesas,r8a7792";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 i2c3 = &i2c3;
23 i2c4 = &i2c4;
24 i2c5 = &i2c5;
25 i2c6 = &iic3;
26 spi0 = &qspi;
27 spi1 = &msiof0;
28 spi2 = &msiof1;
29 vin0 = &vin0;
30 vin1 = &vin1;
31 vin2 = &vin2;
32 vin3 = &vin3;
33 vin4 = &vin4;
34 vin5 = &vin5;
35 };
36
37 /* External CAN clock */
38 can_clk: can {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 /* This value must be overridden by the board. */
42 clock-frequency = <0>;
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 cpu0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a15";
52 reg = <0>;
53 clock-frequency = <1000000000>;
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
55 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
56 enable-method = "renesas,apmu";
57 next-level-cache = <&L2_CA15>;
58 };
59
60 cpu1: cpu@1 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a15";
63 reg = <1>;
64 clock-frequency = <1000000000>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
66 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
67 enable-method = "renesas,apmu";
68 next-level-cache = <&L2_CA15>;
69 };
70
71 L2_CA15: cache-controller-0 {
72 compatible = "cache";
73 cache-unified;
74 cache-level = <2>;
75 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
76 };
77 };
78
79 /* External root clock */
80 extal_clk: extal {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 /* This value must be overridden by the board. */
84 clock-frequency = <0>;
85 };
86
87 pmu {
88 compatible = "arm,cortex-a15-pmu";
89 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
90 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
91 interrupt-affinity = <&cpu0>, <&cpu1>;
92 };
93
94 /* External SCIF clock */
95 scif_clk: scif {
96 compatible = "fixed-clock";
97 #clock-cells = <0>;
98 /* This value must be overridden by the board. */
99 clock-frequency = <0>;
100 };
101
102 soc {
103 compatible = "simple-bus";
104 interrupt-parent = <&gic>;
105
106 #address-cells = <2>;
107 #size-cells = <2>;
108 ranges;
109
110 rwdt: watchdog@e6020000 {
111 compatible = "renesas,r8a7792-wdt",
112 "renesas,rcar-gen2-wdt";
113 reg = <0 0xe6020000 0 0x0c>;
114 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&cpg CPG_MOD 402>;
116 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
117 resets = <&cpg 402>;
118 status = "disabled";
119 };
120
121 gpio0: gpio@e6050000 {
122 compatible = "renesas,gpio-r8a7792",
123 "renesas,rcar-gen2-gpio";
124 reg = <0 0xe6050000 0 0x50>;
125 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
126 #gpio-cells = <2>;
127 gpio-controller;
128 gpio-ranges = <&pfc 0 0 29>;
129 #interrupt-cells = <2>;
130 interrupt-controller;
131 clocks = <&cpg CPG_MOD 912>;
132 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
133 resets = <&cpg 912>;
134 };
135
136 gpio1: gpio@e6051000 {
137 compatible = "renesas,gpio-r8a7792",
138 "renesas,rcar-gen2-gpio";
139 reg = <0 0xe6051000 0 0x50>;
140 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
141 #gpio-cells = <2>;
142 gpio-controller;
143 gpio-ranges = <&pfc 0 32 23>;
144 #interrupt-cells = <2>;
145 interrupt-controller;
146 clocks = <&cpg CPG_MOD 911>;
147 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
148 resets = <&cpg 911>;
149 };
150
151 gpio2: gpio@e6052000 {
152 compatible = "renesas,gpio-r8a7792",
153 "renesas,rcar-gen2-gpio";
154 reg = <0 0xe6052000 0 0x50>;
155 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
156 #gpio-cells = <2>;
157 gpio-controller;
158 gpio-ranges = <&pfc 0 64 32>;
159 #interrupt-cells = <2>;
160 interrupt-controller;
161 clocks = <&cpg CPG_MOD 910>;
162 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
163 resets = <&cpg 910>;
164 };
165
166 gpio3: gpio@e6053000 {
167 compatible = "renesas,gpio-r8a7792",
168 "renesas,rcar-gen2-gpio";
169 reg = <0 0xe6053000 0 0x50>;
170 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
171 #gpio-cells = <2>;
172 gpio-controller;
173 gpio-ranges = <&pfc 0 96 28>;
174 #interrupt-cells = <2>;
175 interrupt-controller;
176 clocks = <&cpg CPG_MOD 909>;
177 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
178 resets = <&cpg 909>;
179 };
180
181 gpio4: gpio@e6054000 {
182 compatible = "renesas,gpio-r8a7792",
183 "renesas,rcar-gen2-gpio";
184 reg = <0 0xe6054000 0 0x50>;
185 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
186 #gpio-cells = <2>;
187 gpio-controller;
188 gpio-ranges = <&pfc 0 128 17>;
189 #interrupt-cells = <2>;
190 interrupt-controller;
191 clocks = <&cpg CPG_MOD 908>;
192 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
193 resets = <&cpg 908>;
194 };
195
196 gpio5: gpio@e6055000 {
197 compatible = "renesas,gpio-r8a7792",
198 "renesas,rcar-gen2-gpio";
199 reg = <0 0xe6055000 0 0x50>;
200 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
201 #gpio-cells = <2>;
202 gpio-controller;
203 gpio-ranges = <&pfc 0 160 17>;
204 #interrupt-cells = <2>;
205 interrupt-controller;
206 clocks = <&cpg CPG_MOD 907>;
207 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
208 resets = <&cpg 907>;
209 };
210
211 gpio6: gpio@e6055100 {
212 compatible = "renesas,gpio-r8a7792",
213 "renesas,rcar-gen2-gpio";
214 reg = <0 0xe6055100 0 0x50>;
215 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
216 #gpio-cells = <2>;
217 gpio-controller;
218 gpio-ranges = <&pfc 0 192 17>;
219 #interrupt-cells = <2>;
220 interrupt-controller;
221 clocks = <&cpg CPG_MOD 905>;
222 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
223 resets = <&cpg 905>;
224 };
225
226 gpio7: gpio@e6055200 {
227 compatible = "renesas,gpio-r8a7792",
228 "renesas,rcar-gen2-gpio";
229 reg = <0 0xe6055200 0 0x50>;
230 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
231 #gpio-cells = <2>;
232 gpio-controller;
233 gpio-ranges = <&pfc 0 224 17>;
234 #interrupt-cells = <2>;
235 interrupt-controller;
236 clocks = <&cpg CPG_MOD 904>;
237 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
238 resets = <&cpg 904>;
239 };
240
241 gpio8: gpio@e6055300 {
242 compatible = "renesas,gpio-r8a7792",
243 "renesas,rcar-gen2-gpio";
244 reg = <0 0xe6055300 0 0x50>;
245 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
246 #gpio-cells = <2>;
247 gpio-controller;
248 gpio-ranges = <&pfc 0 256 17>;
249 #interrupt-cells = <2>;
250 interrupt-controller;
251 clocks = <&cpg CPG_MOD 921>;
252 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
253 resets = <&cpg 921>;
254 };
255
256 gpio9: gpio@e6055400 {
257 compatible = "renesas,gpio-r8a7792",
258 "renesas,rcar-gen2-gpio";
259 reg = <0 0xe6055400 0 0x50>;
260 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
261 #gpio-cells = <2>;
262 gpio-controller;
263 gpio-ranges = <&pfc 0 288 17>;
264 #interrupt-cells = <2>;
265 interrupt-controller;
266 clocks = <&cpg CPG_MOD 919>;
267 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
268 resets = <&cpg 919>;
269 };
270
271 gpio10: gpio@e6055500 {
272 compatible = "renesas,gpio-r8a7792",
273 "renesas,rcar-gen2-gpio";
274 reg = <0 0xe6055500 0 0x50>;
275 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
276 #gpio-cells = <2>;
277 gpio-controller;
278 gpio-ranges = <&pfc 0 320 32>;
279 #interrupt-cells = <2>;
280 interrupt-controller;
281 clocks = <&cpg CPG_MOD 914>;
282 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
283 resets = <&cpg 914>;
284 };
285
286 gpio11: gpio@e6055600 {
287 compatible = "renesas,gpio-r8a7792",
288 "renesas,rcar-gen2-gpio";
289 reg = <0 0xe6055600 0 0x50>;
290 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
291 #gpio-cells = <2>;
292 gpio-controller;
293 gpio-ranges = <&pfc 0 352 30>;
294 #interrupt-cells = <2>;
295 interrupt-controller;
296 clocks = <&cpg CPG_MOD 913>;
297 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
298 resets = <&cpg 913>;
299 };
300
301 pfc: pinctrl@e6060000 {
302 compatible = "renesas,pfc-r8a7792";
303 reg = <0 0xe6060000 0 0x144>;
304 };
305
306 cpg: clock-controller@e6150000 {
307 compatible = "renesas,r8a7792-cpg-mssr";
308 reg = <0 0xe6150000 0 0x1000>;
309 clocks = <&extal_clk>;
310 clock-names = "extal";
311 #clock-cells = <2>;
312 #power-domain-cells = <0>;
313 #reset-cells = <1>;
314 };
315
316 apmu@e6152000 {
317 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
318 reg = <0 0xe6152000 0 0x188>;
319 cpus = <&cpu0>, <&cpu1>;
320 };
321
322 rst: reset-controller@e6160000 {
323 compatible = "renesas,r8a7792-rst";
324 reg = <0 0xe6160000 0 0x0100>;
325 };
326
327 sysc: system-controller@e6180000 {
328 compatible = "renesas,r8a7792-sysc";
329 reg = <0 0xe6180000 0 0x0200>;
330 #power-domain-cells = <1>;
331 };
332
333 irqc: interrupt-controller@e61c0000 {
334 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
335 #interrupt-cells = <2>;
336 interrupt-controller;
337 reg = <0 0xe61c0000 0 0x200>;
338 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&cpg CPG_MOD 407>;
343 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
344 resets = <&cpg 407>;
345 };
346
347 icram0: sram@e63a0000 {
348 compatible = "mmio-sram";
349 reg = <0 0xe63a0000 0 0x12000>;
350 #address-cells = <1>;
351 #size-cells = <1>;
352 ranges = <0 0 0xe63a0000 0x12000>;
353 };
354
355 icram1: sram@e63c0000 {
356 compatible = "mmio-sram";
357 reg = <0 0xe63c0000 0 0x1000>;
358 #address-cells = <1>;
359 #size-cells = <1>;
360 ranges = <0 0 0xe63c0000 0x1000>;
361
362 smp-sram@0 {
363 compatible = "renesas,smp-sram";
364 reg = <0 0x100>;
365 };
366 };
367
368 /* I2C doesn't need pinmux */
369 i2c0: i2c@e6508000 {
370 compatible = "renesas,i2c-r8a7792",
371 "renesas,rcar-gen2-i2c";
372 reg = <0 0xe6508000 0 0x40>;
373 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&cpg CPG_MOD 931>;
375 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
376 resets = <&cpg 931>;
377 i2c-scl-internal-delay-ns = <6>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 status = "disabled";
381 };
382
383 i2c1: i2c@e6518000 {
384 compatible = "renesas,i2c-r8a7792",
385 "renesas,rcar-gen2-i2c";
386 reg = <0 0xe6518000 0 0x40>;
387 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&cpg CPG_MOD 930>;
389 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
390 resets = <&cpg 930>;
391 i2c-scl-internal-delay-ns = <6>;
392 #address-cells = <1>;
393 #size-cells = <0>;
394 status = "disabled";
395 };
396
397 i2c2: i2c@e6530000 {
398 compatible = "renesas,i2c-r8a7792",
399 "renesas,rcar-gen2-i2c";
400 reg = <0 0xe6530000 0 0x40>;
401 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&cpg CPG_MOD 929>;
403 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
404 resets = <&cpg 929>;
405 i2c-scl-internal-delay-ns = <6>;
406 #address-cells = <1>;
407 #size-cells = <0>;
408 status = "disabled";
409 };
410
411 i2c3: i2c@e6540000 {
412 compatible = "renesas,i2c-r8a7792",
413 "renesas,rcar-gen2-i2c";
414 reg = <0 0xe6540000 0 0x40>;
415 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&cpg CPG_MOD 928>;
417 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
418 resets = <&cpg 928>;
419 i2c-scl-internal-delay-ns = <6>;
420 #address-cells = <1>;
421 #size-cells = <0>;
422 status = "disabled";
423 };
424
425 i2c4: i2c@e6520000 {
426 compatible = "renesas,i2c-r8a7792",
427 "renesas,rcar-gen2-i2c";
428 reg = <0 0xe6520000 0 0x40>;
429 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&cpg CPG_MOD 927>;
431 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
432 resets = <&cpg 927>;
433 i2c-scl-internal-delay-ns = <6>;
434 #address-cells = <1>;
435 #size-cells = <0>;
436 status = "disabled";
437 };
438
439 i2c5: i2c@e6528000 {
440 compatible = "renesas,i2c-r8a7792",
441 "renesas,rcar-gen2-i2c";
442 reg = <0 0xe6528000 0 0x40>;
443 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&cpg CPG_MOD 925>;
445 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
446 resets = <&cpg 925>;
447 i2c-scl-internal-delay-ns = <110>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450 status = "disabled";
451 };
452
453 iic3: i2c@e60b0000 {
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "renesas,iic-r8a7792",
457 "renesas,rcar-gen2-iic",
458 "renesas,rmobile-iic";
459 reg = <0 0xe60b0000 0 0x425>;
460 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&cpg CPG_MOD 926>;
462 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
463 <&dmac1 0x77>, <&dmac1 0x78>;
464 dma-names = "tx", "rx", "tx", "rx";
465 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
466 resets = <&cpg 926>;
467 status = "disabled";
468 };
469
470 dmac0: dma-controller@e6700000 {
471 compatible = "renesas,dmac-r8a7792",
472 "renesas,rcar-dmac";
473 reg = <0 0xe6700000 0 0x20000>;
474 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
490 interrupt-names = "error",
491 "ch0", "ch1", "ch2", "ch3",
492 "ch4", "ch5", "ch6", "ch7",
493 "ch8", "ch9", "ch10", "ch11",
494 "ch12", "ch13", "ch14";
495 clocks = <&cpg CPG_MOD 219>;
496 clock-names = "fck";
497 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
498 resets = <&cpg 219>;
499 #dma-cells = <1>;
500 dma-channels = <15>;
501 };
502
503 dmac1: dma-controller@e6720000 {
504 compatible = "renesas,dmac-r8a7792",
505 "renesas,rcar-dmac";
506 reg = <0 0xe6720000 0 0x20000>;
507 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
523 interrupt-names = "error",
524 "ch0", "ch1", "ch2", "ch3",
525 "ch4", "ch5", "ch6", "ch7",
526 "ch8", "ch9", "ch10", "ch11",
527 "ch12", "ch13", "ch14";
528 clocks = <&cpg CPG_MOD 218>;
529 clock-names = "fck";
530 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
531 resets = <&cpg 218>;
532 #dma-cells = <1>;
533 dma-channels = <15>;
534 };
535
536 avb: ethernet@e6800000 {
537 compatible = "renesas,etheravb-r8a7792",
538 "renesas,etheravb-rcar-gen2";
539 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
540 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&cpg CPG_MOD 812>;
542 clock-names = "fck";
543 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
544 resets = <&cpg 812>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 status = "disabled";
548 };
549
550 qspi: spi@e6b10000 {
551 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
552 reg = <0 0xe6b10000 0 0x2c>;
553 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&cpg CPG_MOD 917>;
555 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
556 <&dmac1 0x17>, <&dmac1 0x18>;
557 dma-names = "tx", "rx", "tx", "rx";
558 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
559 resets = <&cpg 917>;
560 num-cs = <1>;
561 #address-cells = <1>;
562 #size-cells = <0>;
563 status = "disabled";
564 };
565
566 scif0: serial@e6e60000 {
567 compatible = "renesas,scif-r8a7792",
568 "renesas,rcar-gen2-scif", "renesas,scif";
569 reg = <0 0xe6e60000 0 64>;
570 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cpg CPG_MOD 721>,
572 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
573 clock-names = "fck", "brg_int", "scif_clk";
574 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
575 <&dmac1 0x29>, <&dmac1 0x2a>;
576 dma-names = "tx", "rx", "tx", "rx";
577 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
578 resets = <&cpg 721>;
579 status = "disabled";
580 };
581
582 scif1: serial@e6e68000 {
583 compatible = "renesas,scif-r8a7792",
584 "renesas,rcar-gen2-scif", "renesas,scif";
585 reg = <0 0xe6e68000 0 64>;
586 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&cpg CPG_MOD 720>,
588 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
589 clock-names = "fck", "brg_int", "scif_clk";
590 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
591 <&dmac1 0x2d>, <&dmac1 0x2e>;
592 dma-names = "tx", "rx", "tx", "rx";
593 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
594 resets = <&cpg 720>;
595 status = "disabled";
596 };
597
598 scif2: serial@e6e58000 {
599 compatible = "renesas,scif-r8a7792",
600 "renesas,rcar-gen2-scif", "renesas,scif";
601 reg = <0 0xe6e58000 0 64>;
602 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cpg CPG_MOD 719>,
604 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
605 clock-names = "fck", "brg_int", "scif_clk";
606 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
607 <&dmac1 0x2b>, <&dmac1 0x2c>;
608 dma-names = "tx", "rx", "tx", "rx";
609 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
610 resets = <&cpg 719>;
611 status = "disabled";
612 };
613
614 scif3: serial@e6ea8000 {
615 compatible = "renesas,scif-r8a7792",
616 "renesas,rcar-gen2-scif", "renesas,scif";
617 reg = <0 0xe6ea8000 0 64>;
618 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cpg CPG_MOD 718>,
620 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
621 clock-names = "fck", "brg_int", "scif_clk";
622 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
623 <&dmac1 0x2f>, <&dmac1 0x30>;
624 dma-names = "tx", "rx", "tx", "rx";
625 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
626 resets = <&cpg 718>;
627 status = "disabled";
628 };
629
630 hscif0: serial@e62c0000 {
631 compatible = "renesas,hscif-r8a7792",
632 "renesas,rcar-gen2-hscif", "renesas,hscif";
633 reg = <0 0xe62c0000 0 96>;
634 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&cpg CPG_MOD 717>,
636 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
637 clock-names = "fck", "brg_int", "scif_clk";
638 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
639 <&dmac1 0x39>, <&dmac1 0x3a>;
640 dma-names = "tx", "rx", "tx", "rx";
641 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
642 resets = <&cpg 717>;
643 status = "disabled";
644 };
645
646 hscif1: serial@e62c8000 {
647 compatible = "renesas,hscif-r8a7792",
648 "renesas,rcar-gen2-hscif", "renesas,hscif";
649 reg = <0 0xe62c8000 0 96>;
650 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&cpg CPG_MOD 716>,
652 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
653 clock-names = "fck", "brg_int", "scif_clk";
654 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
655 <&dmac1 0x4d>, <&dmac1 0x4e>;
656 dma-names = "tx", "rx", "tx", "rx";
657 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
658 resets = <&cpg 716>;
659 status = "disabled";
660 };
661
662 msiof0: spi@e6e20000 {
663 compatible = "renesas,msiof-r8a7792",
664 "renesas,rcar-gen2-msiof";
665 reg = <0 0xe6e20000 0 0x0064>;
666 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&cpg CPG_MOD 000>;
668 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
669 <&dmac1 0x51>, <&dmac1 0x52>;
670 dma-names = "tx", "rx", "tx", "rx";
671 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
672 resets = <&cpg 000>;
673 #address-cells = <1>;
674 #size-cells = <0>;
675 status = "disabled";
676 };
677
678 msiof1: spi@e6e10000 {
679 compatible = "renesas,msiof-r8a7792",
680 "renesas,rcar-gen2-msiof";
681 reg = <0 0xe6e10000 0 0x0064>;
682 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&cpg CPG_MOD 208>;
684 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
685 <&dmac1 0x55>, <&dmac1 0x56>;
686 dma-names = "tx", "rx", "tx", "rx";
687 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
688 resets = <&cpg 208>;
689 #address-cells = <1>;
690 #size-cells = <0>;
691 status = "disabled";
692 };
693
694 can0: can@e6e80000 {
695 compatible = "renesas,can-r8a7792",
696 "renesas,rcar-gen2-can";
697 reg = <0 0xe6e80000 0 0x1000>;
698 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&cpg CPG_MOD 916>,
700 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
701 clock-names = "clkp1", "clkp2", "can_clk";
702 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
703 resets = <&cpg 916>;
704 status = "disabled";
705 };
706
707 can1: can@e6e88000 {
708 compatible = "renesas,can-r8a7792",
709 "renesas,rcar-gen2-can";
710 reg = <0 0xe6e88000 0 0x1000>;
711 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&cpg CPG_MOD 915>,
713 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
714 clock-names = "clkp1", "clkp2", "can_clk";
715 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
716 resets = <&cpg 915>;
717 status = "disabled";
718 };
719
720 vin0: video@e6ef0000 {
721 compatible = "renesas,vin-r8a7792",
722 "renesas,rcar-gen2-vin";
723 reg = <0 0xe6ef0000 0 0x1000>;
724 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&cpg CPG_MOD 811>;
726 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
727 resets = <&cpg 811>;
728 status = "disabled";
729 };
730
731 vin1: video@e6ef1000 {
732 compatible = "renesas,vin-r8a7792",
733 "renesas,rcar-gen2-vin";
734 reg = <0 0xe6ef1000 0 0x1000>;
735 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&cpg CPG_MOD 810>;
737 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
738 resets = <&cpg 810>;
739 status = "disabled";
740 };
741
742 vin2: video@e6ef2000 {
743 compatible = "renesas,vin-r8a7792",
744 "renesas,rcar-gen2-vin";
745 reg = <0 0xe6ef2000 0 0x1000>;
746 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&cpg CPG_MOD 809>;
748 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
749 resets = <&cpg 809>;
750 status = "disabled";
751 };
752
753 vin3: video@e6ef3000 {
754 compatible = "renesas,vin-r8a7792",
755 "renesas,rcar-gen2-vin";
756 reg = <0 0xe6ef3000 0 0x1000>;
757 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cpg CPG_MOD 808>;
759 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
760 resets = <&cpg 808>;
761 status = "disabled";
762 };
763
764 vin4: video@e6ef4000 {
765 compatible = "renesas,vin-r8a7792",
766 "renesas,rcar-gen2-vin";
767 reg = <0 0xe6ef4000 0 0x1000>;
768 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&cpg CPG_MOD 805>;
770 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
771 resets = <&cpg 805>;
772 status = "disabled";
773 };
774
775 vin5: video@e6ef5000 {
776 compatible = "renesas,vin-r8a7792",
777 "renesas,rcar-gen2-vin";
778 reg = <0 0xe6ef5000 0 0x1000>;
779 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&cpg CPG_MOD 804>;
781 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
782 resets = <&cpg 804>;
783 status = "disabled";
784 };
785
786 sdhi0: mmc@ee100000 {
787 compatible = "renesas,sdhi-r8a7792",
788 "renesas,rcar-gen2-sdhi";
789 reg = <0 0xee100000 0 0x328>;
790 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
791 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
792 <&dmac1 0xcd>, <&dmac1 0xce>;
793 dma-names = "tx", "rx", "tx", "rx";
794 clocks = <&cpg CPG_MOD 314>;
795 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
796 resets = <&cpg 314>;
797 status = "disabled";
798 };
799
800 gic: interrupt-controller@f1001000 {
801 compatible = "arm,gic-400";
802 #interrupt-cells = <3>;
803 interrupt-controller;
804 reg = <0 0xf1001000 0 0x1000>,
805 <0 0xf1002000 0 0x2000>,
806 <0 0xf1004000 0 0x2000>,
807 <0 0xf1006000 0 0x2000>;
808 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
809 IRQ_TYPE_LEVEL_HIGH)>;
810 clocks = <&cpg CPG_MOD 408>;
811 clock-names = "clk";
812 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
813 resets = <&cpg 408>;
814 };
815
816 vsp@fe928000 {
817 compatible = "renesas,vsp1";
818 reg = <0 0xfe928000 0 0x8000>;
819 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&cpg CPG_MOD 131>;
821 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
822 resets = <&cpg 131>;
823 };
824
825 vsp@fe930000 {
826 compatible = "renesas,vsp1";
827 reg = <0 0xfe930000 0 0x8000>;
828 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&cpg CPG_MOD 128>;
830 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
831 resets = <&cpg 128>;
832 };
833
834 vsp@fe938000 {
835 compatible = "renesas,vsp1";
836 reg = <0 0xfe938000 0 0x8000>;
837 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&cpg CPG_MOD 127>;
839 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
840 resets = <&cpg 127>;
841 };
842
843 jpu: jpeg-codec@fe980000 {
844 compatible = "renesas,jpu-r8a7792",
845 "renesas,rcar-gen2-jpu";
846 reg = <0 0xfe980000 0 0x10300>;
847 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&cpg CPG_MOD 106>;
849 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
850 resets = <&cpg 106>;
851 };
852
853 du: display@feb00000 {
854 compatible = "renesas,du-r8a7792";
855 reg = <0 0xfeb00000 0 0x40000>;
856 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
859 clock-names = "du.0", "du.1";
860 resets = <&cpg 724>;
861 reset-names = "du.0";
862 status = "disabled";
863
864 ports {
865 #address-cells = <1>;
866 #size-cells = <0>;
867
868 port@0 {
869 reg = <0>;
870 du_out_rgb0: endpoint {
871 };
872 };
873 port@1 {
874 reg = <1>;
875 du_out_rgb1: endpoint {
876 };
877 };
878 };
879 };
880
881 prr: chipid@ff000044 {
882 compatible = "renesas,prr";
883 reg = <0 0xff000044 0 4>;
884 };
885
886 cmt0: timer@ffca0000 {
887 compatible = "renesas,r8a7792-cmt0",
888 "renesas,rcar-gen2-cmt0";
889 reg = <0 0xffca0000 0 0x1004>;
890 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&cpg CPG_MOD 124>;
893 clock-names = "fck";
894 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
895 resets = <&cpg 124>;
896
897 status = "disabled";
898 };
899
900 cmt1: timer@e6130000 {
901 compatible = "renesas,r8a7792-cmt1",
902 "renesas,rcar-gen2-cmt1";
903 reg = <0 0xe6130000 0 0x1004>;
904 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
905 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
906 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
907 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
911 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&cpg CPG_MOD 329>;
913 clock-names = "fck";
914 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
915 resets = <&cpg 329>;
916
917 status = "disabled";
918 };
919 };
920
921 timer {
922 compatible = "arm,armv7-timer";
923 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
924 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
925 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
926 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
927 };
928};
1/*
2 * Device Tree Source for the r8a7792 SoC
3 *
4 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/power/r8a7792-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7792";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
28 spi0 = &qspi;
29 spi1 = &msiof0;
30 spi2 = &msiof1;
31 vin0 = &vin0;
32 vin1 = &vin1;
33 vin2 = &vin2;
34 vin3 = &vin3;
35 vin4 = &vin4;
36 vin5 = &vin5;
37 };
38
39 /* External CAN clock */
40 can_clk: can {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 /* This value must be overridden by the board. */
44 clock-frequency = <0>;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 enable-method = "renesas,apmu";
51
52 cpu0: cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a15";
55 reg = <0>;
56 clock-frequency = <1000000000>;
57 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
58 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
59 next-level-cache = <&L2_CA15>;
60 };
61
62 cpu1: cpu@1 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a15";
65 reg = <1>;
66 clock-frequency = <1000000000>;
67 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
68 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
69 next-level-cache = <&L2_CA15>;
70 };
71
72 L2_CA15: cache-controller-0 {
73 compatible = "cache";
74 cache-unified;
75 cache-level = <2>;
76 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
77 };
78 };
79
80 /* External root clock */
81 extal_clk: extal {
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
84 /* This value must be overridden by the board. */
85 clock-frequency = <0>;
86 };
87
88 /* External SCIF clock */
89 scif_clk: scif {
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 /* This value must be overridden by the board. */
93 clock-frequency = <0>;
94 };
95
96 soc {
97 compatible = "simple-bus";
98 interrupt-parent = <&gic>;
99
100 #address-cells = <2>;
101 #size-cells = <2>;
102 ranges;
103
104 gpio0: gpio@e6050000 {
105 compatible = "renesas,gpio-r8a7792",
106 "renesas,rcar-gen2-gpio";
107 reg = <0 0xe6050000 0 0x50>;
108 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
109 #gpio-cells = <2>;
110 gpio-controller;
111 gpio-ranges = <&pfc 0 0 29>;
112 #interrupt-cells = <2>;
113 interrupt-controller;
114 clocks = <&cpg CPG_MOD 912>;
115 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
116 resets = <&cpg 912>;
117 };
118
119 gpio1: gpio@e6051000 {
120 compatible = "renesas,gpio-r8a7792",
121 "renesas,rcar-gen2-gpio";
122 reg = <0 0xe6051000 0 0x50>;
123 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
124 #gpio-cells = <2>;
125 gpio-controller;
126 gpio-ranges = <&pfc 0 32 23>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
129 clocks = <&cpg CPG_MOD 911>;
130 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
131 resets = <&cpg 911>;
132 };
133
134 gpio2: gpio@e6052000 {
135 compatible = "renesas,gpio-r8a7792",
136 "renesas,rcar-gen2-gpio";
137 reg = <0 0xe6052000 0 0x50>;
138 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
139 #gpio-cells = <2>;
140 gpio-controller;
141 gpio-ranges = <&pfc 0 64 32>;
142 #interrupt-cells = <2>;
143 interrupt-controller;
144 clocks = <&cpg CPG_MOD 910>;
145 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
146 resets = <&cpg 910>;
147 };
148
149 gpio3: gpio@e6053000 {
150 compatible = "renesas,gpio-r8a7792",
151 "renesas,rcar-gen2-gpio";
152 reg = <0 0xe6053000 0 0x50>;
153 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
154 #gpio-cells = <2>;
155 gpio-controller;
156 gpio-ranges = <&pfc 0 96 28>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
159 clocks = <&cpg CPG_MOD 909>;
160 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
161 resets = <&cpg 909>;
162 };
163
164 gpio4: gpio@e6054000 {
165 compatible = "renesas,gpio-r8a7792",
166 "renesas,rcar-gen2-gpio";
167 reg = <0 0xe6054000 0 0x50>;
168 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
169 #gpio-cells = <2>;
170 gpio-controller;
171 gpio-ranges = <&pfc 0 128 17>;
172 #interrupt-cells = <2>;
173 interrupt-controller;
174 clocks = <&cpg CPG_MOD 908>;
175 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
176 resets = <&cpg 908>;
177 };
178
179 gpio5: gpio@e6055000 {
180 compatible = "renesas,gpio-r8a7792",
181 "renesas,rcar-gen2-gpio";
182 reg = <0 0xe6055000 0 0x50>;
183 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
184 #gpio-cells = <2>;
185 gpio-controller;
186 gpio-ranges = <&pfc 0 160 17>;
187 #interrupt-cells = <2>;
188 interrupt-controller;
189 clocks = <&cpg CPG_MOD 907>;
190 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
191 resets = <&cpg 907>;
192 };
193
194 gpio6: gpio@e6055100 {
195 compatible = "renesas,gpio-r8a7792",
196 "renesas,rcar-gen2-gpio";
197 reg = <0 0xe6055100 0 0x50>;
198 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
199 #gpio-cells = <2>;
200 gpio-controller;
201 gpio-ranges = <&pfc 0 192 17>;
202 #interrupt-cells = <2>;
203 interrupt-controller;
204 clocks = <&cpg CPG_MOD 905>;
205 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
206 resets = <&cpg 905>;
207 };
208
209 gpio7: gpio@e6055200 {
210 compatible = "renesas,gpio-r8a7792",
211 "renesas,rcar-gen2-gpio";
212 reg = <0 0xe6055200 0 0x50>;
213 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
214 #gpio-cells = <2>;
215 gpio-controller;
216 gpio-ranges = <&pfc 0 224 17>;
217 #interrupt-cells = <2>;
218 interrupt-controller;
219 clocks = <&cpg CPG_MOD 904>;
220 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
221 resets = <&cpg 904>;
222 };
223
224 gpio8: gpio@e6055300 {
225 compatible = "renesas,gpio-r8a7792",
226 "renesas,rcar-gen2-gpio";
227 reg = <0 0xe6055300 0 0x50>;
228 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
229 #gpio-cells = <2>;
230 gpio-controller;
231 gpio-ranges = <&pfc 0 256 17>;
232 #interrupt-cells = <2>;
233 interrupt-controller;
234 clocks = <&cpg CPG_MOD 921>;
235 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
236 resets = <&cpg 921>;
237 };
238
239 gpio9: gpio@e6055400 {
240 compatible = "renesas,gpio-r8a7792",
241 "renesas,rcar-gen2-gpio";
242 reg = <0 0xe6055400 0 0x50>;
243 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
244 #gpio-cells = <2>;
245 gpio-controller;
246 gpio-ranges = <&pfc 0 288 17>;
247 #interrupt-cells = <2>;
248 interrupt-controller;
249 clocks = <&cpg CPG_MOD 919>;
250 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
251 resets = <&cpg 919>;
252 };
253
254 gpio10: gpio@e6055500 {
255 compatible = "renesas,gpio-r8a7792",
256 "renesas,rcar-gen2-gpio";
257 reg = <0 0xe6055500 0 0x50>;
258 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
259 #gpio-cells = <2>;
260 gpio-controller;
261 gpio-ranges = <&pfc 0 320 32>;
262 #interrupt-cells = <2>;
263 interrupt-controller;
264 clocks = <&cpg CPG_MOD 914>;
265 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
266 resets = <&cpg 914>;
267 };
268
269 gpio11: gpio@e6055600 {
270 compatible = "renesas,gpio-r8a7792",
271 "renesas,rcar-gen2-gpio";
272 reg = <0 0xe6055600 0 0x50>;
273 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
274 #gpio-cells = <2>;
275 gpio-controller;
276 gpio-ranges = <&pfc 0 352 30>;
277 #interrupt-cells = <2>;
278 interrupt-controller;
279 clocks = <&cpg CPG_MOD 913>;
280 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
281 resets = <&cpg 913>;
282 };
283
284 pfc: pin-controller@e6060000 {
285 compatible = "renesas,pfc-r8a7792";
286 reg = <0 0xe6060000 0 0x144>;
287 };
288
289 cpg: clock-controller@e6150000 {
290 compatible = "renesas,r8a7792-cpg-mssr";
291 reg = <0 0xe6150000 0 0x1000>;
292 clocks = <&extal_clk>;
293 clock-names = "extal";
294 #clock-cells = <2>;
295 #power-domain-cells = <0>;
296 #reset-cells = <1>;
297 };
298
299 apmu@e6152000 {
300 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
301 reg = <0 0xe6152000 0 0x188>;
302 cpus = <&cpu0 &cpu1>;
303 };
304
305 rst: reset-controller@e6160000 {
306 compatible = "renesas,r8a7792-rst";
307 reg = <0 0xe6160000 0 0x0100>;
308 };
309
310 sysc: system-controller@e6180000 {
311 compatible = "renesas,r8a7792-sysc";
312 reg = <0 0xe6180000 0 0x0200>;
313 #power-domain-cells = <1>;
314 };
315
316 irqc: interrupt-controller@e61c0000 {
317 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
318 #interrupt-cells = <2>;
319 interrupt-controller;
320 reg = <0 0xe61c0000 0 0x200>;
321 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 407>;
326 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
327 resets = <&cpg 407>;
328 };
329
330 icram0: sram@e63a0000 {
331 compatible = "mmio-sram";
332 reg = <0 0xe63a0000 0 0x12000>;
333 };
334
335 icram1: sram@e63c0000 {
336 compatible = "mmio-sram";
337 reg = <0 0xe63c0000 0 0x1000>;
338 #address-cells = <1>;
339 #size-cells = <1>;
340 ranges = <0 0 0xe63c0000 0x1000>;
341
342 smp-sram@0 {
343 compatible = "renesas,smp-sram";
344 reg = <0 0x10>;
345 };
346 };
347
348 /* I2C doesn't need pinmux */
349 i2c0: i2c@e6508000 {
350 compatible = "renesas,i2c-r8a7792",
351 "renesas,rcar-gen2-i2c";
352 reg = <0 0xe6508000 0 0x40>;
353 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&cpg CPG_MOD 931>;
355 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
356 resets = <&cpg 931>;
357 i2c-scl-internal-delay-ns = <6>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 status = "disabled";
361 };
362
363 i2c1: i2c@e6518000 {
364 compatible = "renesas,i2c-r8a7792",
365 "renesas,rcar-gen2-i2c";
366 reg = <0 0xe6518000 0 0x40>;
367 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&cpg CPG_MOD 930>;
369 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
370 resets = <&cpg 930>;
371 i2c-scl-internal-delay-ns = <6>;
372 #address-cells = <1>;
373 #size-cells = <0>;
374 status = "disabled";
375 };
376
377 i2c2: i2c@e6530000 {
378 compatible = "renesas,i2c-r8a7792",
379 "renesas,rcar-gen2-i2c";
380 reg = <0 0xe6530000 0 0x40>;
381 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&cpg CPG_MOD 929>;
383 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
384 resets = <&cpg 929>;
385 i2c-scl-internal-delay-ns = <6>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388 status = "disabled";
389 };
390
391 i2c3: i2c@e6540000 {
392 compatible = "renesas,i2c-r8a7792",
393 "renesas,rcar-gen2-i2c";
394 reg = <0 0xe6540000 0 0x40>;
395 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cpg CPG_MOD 928>;
397 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
398 resets = <&cpg 928>;
399 i2c-scl-internal-delay-ns = <6>;
400 #address-cells = <1>;
401 #size-cells = <0>;
402 status = "disabled";
403 };
404
405 i2c4: i2c@e6520000 {
406 compatible = "renesas,i2c-r8a7792",
407 "renesas,rcar-gen2-i2c";
408 reg = <0 0xe6520000 0 0x40>;
409 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&cpg CPG_MOD 927>;
411 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
412 resets = <&cpg 927>;
413 i2c-scl-internal-delay-ns = <6>;
414 #address-cells = <1>;
415 #size-cells = <0>;
416 status = "disabled";
417 };
418
419 i2c5: i2c@e6528000 {
420 compatible = "renesas,i2c-r8a7792",
421 "renesas,rcar-gen2-i2c";
422 reg = <0 0xe6528000 0 0x40>;
423 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&cpg CPG_MOD 925>;
425 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
426 resets = <&cpg 925>;
427 i2c-scl-internal-delay-ns = <110>;
428 #address-cells = <1>;
429 #size-cells = <0>;
430 status = "disabled";
431 };
432
433 dmac0: dma-controller@e6700000 {
434 compatible = "renesas,dmac-r8a7792",
435 "renesas,rcar-dmac";
436 reg = <0 0xe6700000 0 0x20000>;
437 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
438 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
439 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
440 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
441 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
442 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
443 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
444 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
445 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
446 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
447 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
448 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
449 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
450 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
451 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
452 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
453 interrupt-names = "error",
454 "ch0", "ch1", "ch2", "ch3",
455 "ch4", "ch5", "ch6", "ch7",
456 "ch8", "ch9", "ch10", "ch11",
457 "ch12", "ch13", "ch14";
458 clocks = <&cpg CPG_MOD 219>;
459 clock-names = "fck";
460 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
461 resets = <&cpg 219>;
462 #dma-cells = <1>;
463 dma-channels = <15>;
464 };
465
466 dmac1: dma-controller@e6720000 {
467 compatible = "renesas,dmac-r8a7792",
468 "renesas,rcar-dmac";
469 reg = <0 0xe6720000 0 0x20000>;
470 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
471 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
472 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
473 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
474 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
475 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
476 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
477 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
478 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
479 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
480 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
481 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
482 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
483 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
484 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
485 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
486 interrupt-names = "error",
487 "ch0", "ch1", "ch2", "ch3",
488 "ch4", "ch5", "ch6", "ch7",
489 "ch8", "ch9", "ch10", "ch11",
490 "ch12", "ch13", "ch14";
491 clocks = <&cpg CPG_MOD 218>;
492 clock-names = "fck";
493 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
494 resets = <&cpg 218>;
495 #dma-cells = <1>;
496 dma-channels = <15>;
497 };
498
499 avb: ethernet@e6800000 {
500 compatible = "renesas,etheravb-r8a7792",
501 "renesas,etheravb-rcar-gen2";
502 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
503 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&cpg CPG_MOD 812>;
505 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
506 resets = <&cpg 812>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 status = "disabled";
510 };
511
512 qspi: spi@e6b10000 {
513 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
514 reg = <0 0xe6b10000 0 0x2c>;
515 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&cpg CPG_MOD 917>;
517 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
518 <&dmac1 0x17>, <&dmac1 0x18>;
519 dma-names = "tx", "rx", "tx", "rx";
520 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
521 resets = <&cpg 917>;
522 num-cs = <1>;
523 #address-cells = <1>;
524 #size-cells = <0>;
525 status = "disabled";
526 };
527
528 scif0: serial@e6e60000 {
529 compatible = "renesas,scif-r8a7792",
530 "renesas,rcar-gen2-scif", "renesas,scif";
531 reg = <0 0xe6e60000 0 64>;
532 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cpg CPG_MOD 721>,
534 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
535 clock-names = "fck", "brg_int", "scif_clk";
536 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
537 <&dmac1 0x29>, <&dmac1 0x2a>;
538 dma-names = "tx", "rx", "tx", "rx";
539 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
540 resets = <&cpg 721>;
541 status = "disabled";
542 };
543
544 scif1: serial@e6e68000 {
545 compatible = "renesas,scif-r8a7792",
546 "renesas,rcar-gen2-scif", "renesas,scif";
547 reg = <0 0xe6e68000 0 64>;
548 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&cpg CPG_MOD 720>,
550 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
551 clock-names = "fck", "brg_int", "scif_clk";
552 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
553 <&dmac1 0x2d>, <&dmac1 0x2e>;
554 dma-names = "tx", "rx", "tx", "rx";
555 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
556 resets = <&cpg 720>;
557 status = "disabled";
558 };
559
560 scif2: serial@e6e58000 {
561 compatible = "renesas,scif-r8a7792",
562 "renesas,rcar-gen2-scif", "renesas,scif";
563 reg = <0 0xe6e58000 0 64>;
564 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&cpg CPG_MOD 719>,
566 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
567 clock-names = "fck", "brg_int", "scif_clk";
568 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
569 <&dmac1 0x2b>, <&dmac1 0x2c>;
570 dma-names = "tx", "rx", "tx", "rx";
571 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
572 resets = <&cpg 719>;
573 status = "disabled";
574 };
575
576 scif3: serial@e6ea8000 {
577 compatible = "renesas,scif-r8a7792",
578 "renesas,rcar-gen2-scif", "renesas,scif";
579 reg = <0 0xe6ea8000 0 64>;
580 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&cpg CPG_MOD 718>,
582 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
583 clock-names = "fck", "brg_int", "scif_clk";
584 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
585 <&dmac1 0x2f>, <&dmac1 0x30>;
586 dma-names = "tx", "rx", "tx", "rx";
587 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
588 resets = <&cpg 718>;
589 status = "disabled";
590 };
591
592 hscif0: serial@e62c0000 {
593 compatible = "renesas,hscif-r8a7792",
594 "renesas,rcar-gen2-hscif", "renesas,hscif";
595 reg = <0 0xe62c0000 0 96>;
596 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&cpg CPG_MOD 717>,
598 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
599 clock-names = "fck", "brg_int", "scif_clk";
600 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
601 <&dmac1 0x39>, <&dmac1 0x3a>;
602 dma-names = "tx", "rx", "tx", "rx";
603 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
604 resets = <&cpg 717>;
605 status = "disabled";
606 };
607
608 hscif1: serial@e62c8000 {
609 compatible = "renesas,hscif-r8a7792",
610 "renesas,rcar-gen2-hscif", "renesas,hscif";
611 reg = <0 0xe62c8000 0 96>;
612 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&cpg CPG_MOD 716>,
614 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
615 clock-names = "fck", "brg_int", "scif_clk";
616 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
617 <&dmac1 0x4d>, <&dmac1 0x4e>;
618 dma-names = "tx", "rx", "tx", "rx";
619 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
620 resets = <&cpg 716>;
621 status = "disabled";
622 };
623
624 msiof0: spi@e6e20000 {
625 compatible = "renesas,msiof-r8a7792",
626 "renesas,rcar-gen2-msiof";
627 reg = <0 0xe6e20000 0 0x0064>;
628 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&cpg CPG_MOD 000>;
630 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
631 <&dmac1 0x51>, <&dmac1 0x52>;
632 dma-names = "tx", "rx", "tx", "rx";
633 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
634 resets = <&cpg 000>;
635 #address-cells = <1>;
636 #size-cells = <0>;
637 status = "disabled";
638 };
639
640 msiof1: spi@e6e10000 {
641 compatible = "renesas,msiof-r8a7792",
642 "renesas,rcar-gen2-msiof";
643 reg = <0 0xe6e10000 0 0x0064>;
644 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&cpg CPG_MOD 208>;
646 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
647 <&dmac1 0x55>, <&dmac1 0x56>;
648 dma-names = "tx", "rx", "tx", "rx";
649 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
650 resets = <&cpg 208>;
651 #address-cells = <1>;
652 #size-cells = <0>;
653 status = "disabled";
654 };
655
656 can0: can@e6e80000 {
657 compatible = "renesas,can-r8a7792",
658 "renesas,rcar-gen2-can";
659 reg = <0 0xe6e80000 0 0x1000>;
660 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&cpg CPG_MOD 916>,
662 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
663 clock-names = "clkp1", "clkp2", "can_clk";
664 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
665 resets = <&cpg 916>;
666 status = "disabled";
667 };
668
669 can1: can@e6e88000 {
670 compatible = "renesas,can-r8a7792",
671 "renesas,rcar-gen2-can";
672 reg = <0 0xe6e88000 0 0x1000>;
673 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&cpg CPG_MOD 915>,
675 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
676 clock-names = "clkp1", "clkp2", "can_clk";
677 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
678 resets = <&cpg 915>;
679 status = "disabled";
680 };
681
682 vin0: video@e6ef0000 {
683 compatible = "renesas,vin-r8a7792",
684 "renesas,rcar-gen2-vin";
685 reg = <0 0xe6ef0000 0 0x1000>;
686 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&cpg CPG_MOD 811>;
688 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
689 resets = <&cpg 811>;
690 status = "disabled";
691 };
692
693 vin1: video@e6ef1000 {
694 compatible = "renesas,vin-r8a7792",
695 "renesas,rcar-gen2-vin";
696 reg = <0 0xe6ef1000 0 0x1000>;
697 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&cpg CPG_MOD 810>;
699 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
700 resets = <&cpg 810>;
701 status = "disabled";
702 };
703
704 vin2: video@e6ef2000 {
705 compatible = "renesas,vin-r8a7792",
706 "renesas,rcar-gen2-vin";
707 reg = <0 0xe6ef2000 0 0x1000>;
708 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&cpg CPG_MOD 809>;
710 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
711 resets = <&cpg 809>;
712 status = "disabled";
713 };
714
715 vin3: video@e6ef3000 {
716 compatible = "renesas,vin-r8a7792",
717 "renesas,rcar-gen2-vin";
718 reg = <0 0xe6ef3000 0 0x1000>;
719 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&cpg CPG_MOD 808>;
721 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
722 resets = <&cpg 808>;
723 status = "disabled";
724 };
725
726 vin4: video@e6ef4000 {
727 compatible = "renesas,vin-r8a7792",
728 "renesas,rcar-gen2-vin";
729 reg = <0 0xe6ef4000 0 0x1000>;
730 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&cpg CPG_MOD 805>;
732 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
733 resets = <&cpg 805>;
734 status = "disabled";
735 };
736
737 vin5: video@e6ef5000 {
738 compatible = "renesas,vin-r8a7792",
739 "renesas,rcar-gen2-vin";
740 reg = <0 0xe6ef5000 0 0x1000>;
741 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&cpg CPG_MOD 804>;
743 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
744 resets = <&cpg 804>;
745 status = "disabled";
746 };
747
748 sdhi0: sd@ee100000 {
749 compatible = "renesas,sdhi-r8a7792",
750 "renesas,rcar-gen2-sdhi";
751 reg = <0 0xee100000 0 0x328>;
752 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
753 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
754 <&dmac1 0xcd>, <&dmac1 0xce>;
755 dma-names = "tx", "rx", "tx", "rx";
756 clocks = <&cpg CPG_MOD 314>;
757 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
758 resets = <&cpg 314>;
759 status = "disabled";
760 };
761
762 gic: interrupt-controller@f1001000 {
763 compatible = "arm,gic-400";
764 #interrupt-cells = <3>;
765 interrupt-controller;
766 reg = <0 0xf1001000 0 0x1000>,
767 <0 0xf1002000 0 0x2000>,
768 <0 0xf1004000 0 0x2000>,
769 <0 0xf1006000 0 0x2000>;
770 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
771 IRQ_TYPE_LEVEL_HIGH)>;
772 clocks = <&cpg CPG_MOD 408>;
773 clock-names = "clk";
774 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
775 resets = <&cpg 408>;
776 };
777
778 vsp@fe928000 {
779 compatible = "renesas,vsp1";
780 reg = <0 0xfe928000 0 0x8000>;
781 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&cpg CPG_MOD 131>;
783 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
784 resets = <&cpg 131>;
785 };
786
787 vsp@fe930000 {
788 compatible = "renesas,vsp1";
789 reg = <0 0xfe930000 0 0x8000>;
790 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&cpg CPG_MOD 128>;
792 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
793 resets = <&cpg 128>;
794 };
795
796 vsp@fe938000 {
797 compatible = "renesas,vsp1";
798 reg = <0 0xfe938000 0 0x8000>;
799 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&cpg CPG_MOD 127>;
801 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
802 resets = <&cpg 127>;
803 };
804
805 jpu: jpeg-codec@fe980000 {
806 compatible = "renesas,jpu-r8a7792",
807 "renesas,rcar-gen2-jpu";
808 reg = <0 0xfe980000 0 0x10300>;
809 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&cpg CPG_MOD 106>;
811 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
812 resets = <&cpg 106>;
813 };
814
815 du: display@feb00000 {
816 compatible = "renesas,du-r8a7792";
817 reg = <0 0xfeb00000 0 0x40000>;
818 reg-names = "du";
819 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&cpg CPG_MOD 724>,
822 <&cpg CPG_MOD 723>;
823 clock-names = "du.0", "du.1";
824 status = "disabled";
825
826 ports {
827 #address-cells = <1>;
828 #size-cells = <0>;
829
830 port@0 {
831 reg = <0>;
832 du_out_rgb0: endpoint {
833 };
834 };
835 port@1 {
836 reg = <1>;
837 du_out_rgb1: endpoint {
838 };
839 };
840 };
841 };
842
843 prr: chipid@ff000044 {
844 compatible = "renesas,prr";
845 reg = <0 0xff000044 0 4>;
846 };
847 };
848
849 timer {
850 compatible = "arm,armv7-timer";
851 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
852 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
853 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
854 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
855 };
856};