1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 * Device Tree Source for the SK-RZG1E board
 4 *
 5 * Copyright (C) 2016-2017 Cogent Embedded, Inc.
 
 
 
 
 6 */
 7
 8/dts-v1/;
 9#include "r8a7745.dtsi"
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13	model = "SK-RZG1E";
14	compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
15
16	aliases {
17		serial0 = &scif2;
18	};
19
20	chosen {
21		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
22		stdout-path = "serial0:115200n8";
23	};
24
25	memory@40000000 {
26		device_type = "memory";
27		reg = <0 0x40000000 0 0x40000000>;
28	};
29};
30
31&extal_clk {
32	clock-frequency = <20000000>;
33};
34
35&pfc {
36	scif2_pins: scif2 {
37		groups = "scif2_data";
38		function = "scif2";
39	};
40
41	ether_pins: ether {
42		groups = "eth_link", "eth_mdio", "eth_rmii";
43		function = "eth";
44	};
45
46	phy1_pins: phy1 {
47		groups = "intc_irq8";
48		function = "intc";
49	};
50};
51
52&scif2 {
53	pinctrl-0 = <&scif2_pins>;
54	pinctrl-names = "default";
55
56	status = "okay";
57};
58
59&ether {
60	pinctrl-0 = <&ether_pins>, <&phy1_pins>;
61	pinctrl-names = "default";
62
63	phy-handle = <&phy1>;
64	renesas,ether-link-active-low;
65	status = "okay";
66
67	phy1: ethernet-phy@1 {
68		compatible = "ethernet-phy-id0022.1537",
69			     "ethernet-phy-ieee802.3-c22";
70		reg = <1>;
71		interrupt-parent = <&irqc>;
72		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
73		micrel,led-mode = <1>;
74		reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
75	};
76};

 
 1/*
 2 * Device Tree Source for the SK-RZG1E board
 3 *
 4 * Copyright (C) 2016-2017 Cogent Embedded, Inc.
 5 *
 6 * This file is licensed under the terms of the GNU General Public License
 7 * version 2. This program is licensed "as is" without any warranty of any
 8 * kind, whether express or implied.
 9 */
10
11/dts-v1/;
12#include "r8a7745.dtsi"
 
13
14/ {
15	model = "SK-RZG1E";
16	compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
17
18	aliases {
19		serial0 = &scif2;
20	};
21
22	chosen {
23		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
24		stdout-path = "serial0:115200n8";
25	};
26
27	memory@40000000 {
28		device_type = "memory";
29		reg = <0 0x40000000 0 0x40000000>;
30	};
31};
32
33&extal_clk {
34	clock-frequency = <20000000>;
35};
36
37&pfc {
38	scif2_pins: scif2 {
39		groups = "scif2_data";
40		function = "scif2";
41	};
42
43	ether_pins: ether {
44		groups = "eth_link", "eth_mdio", "eth_rmii";
45		function = "eth";
46	};
47
48	phy1_pins: phy1 {
49		groups = "intc_irq8";
50		function = "intc";
51	};
52};
53
54&scif2 {
55	pinctrl-0 = <&scif2_pins>;
56	pinctrl-names = "default";
57
58	status = "okay";
59};
60
61&ether {
62	pinctrl-0 = <&ether_pins &phy1_pins>;
63	pinctrl-names = "default";
64
65	phy-handle = <&phy1>;
66	renesas,ether-link-active-low;
67	status = "okay";
68
69	phy1: ethernet-phy@1 {
 
 
70		reg = <1>;
71		interrupt-parent = <&irqc>;
72		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
73		micrel,led-mode = <1>;
 
74	};
75};