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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2005-2006 by Texas Instruments
4 *
5 * This file is part of the Inventra Controller Driver for Linux.
6 */
7
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/list.h>
12#include <linux/delay.h>
13#include <linux/clk.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19#include <linux/usb/usb_phy_generic.h>
20
21#include <mach/cputype.h>
22#include <mach/hardware.h>
23
24#include <asm/mach-types.h>
25
26#include "musb_core.h"
27
28#ifdef CONFIG_MACH_DAVINCI_EVM
29#define GPIO_nVBUS_DRV 160
30#endif
31
32#include "davinci.h"
33#include "cppi_dma.h"
34
35
36#define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR)
37#define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR)
38
39struct davinci_glue {
40 struct device *dev;
41 struct platform_device *musb;
42 struct clk *clk;
43};
44
45/* REVISIT (PM) we should be able to keep the PHY in low power mode most
46 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
47 * and, when in host mode, autosuspending idle root ports... PHYPLLON
48 * (overriding SUSPENDM?) then likely needs to stay off.
49 */
50
51static inline void phy_on(void)
52{
53 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
54
55 /* power everything up; start the on-chip PHY and its PLL */
56 phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
57 phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
58 __raw_writel(phy_ctrl, USB_PHY_CTRL);
59
60 /* wait for PLL to lock before proceeding */
61 while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
62 cpu_relax();
63}
64
65static inline void phy_off(void)
66{
67 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
68
69 /* powerdown the on-chip PHY, its PLL, and the OTG block */
70 phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON);
71 phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN;
72 __raw_writel(phy_ctrl, USB_PHY_CTRL);
73}
74
75static int dma_off = 1;
76
77static void davinci_musb_enable(struct musb *musb)
78{
79 u32 tmp, old, val;
80
81 /* workaround: setup irqs through both register sets */
82 tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
83 << DAVINCI_USB_TXINT_SHIFT;
84 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
85 old = tmp;
86 tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
87 << DAVINCI_USB_RXINT_SHIFT;
88 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
89 tmp |= old;
90
91 val = ~MUSB_INTR_SOF;
92 tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
93 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
94
95 if (is_dma_capable() && !dma_off)
96 printk(KERN_WARNING "%s %s: dma not reactivated\n",
97 __FILE__, __func__);
98 else
99 dma_off = 0;
100
101 /* force a DRVVBUS irq so we can start polling for ID change */
102 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
103 DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
104}
105
106/*
107 * Disable the HDRC and flush interrupts
108 */
109static void davinci_musb_disable(struct musb *musb)
110{
111 /* because we don't set CTRLR.UINT, "important" to:
112 * - not read/write INTRUSB/INTRUSBE
113 * - (except during initial setup, as workaround)
114 * - use INTSETR/INTCLRR instead
115 */
116 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
117 DAVINCI_USB_USBINT_MASK
118 | DAVINCI_USB_TXINT_MASK
119 | DAVINCI_USB_RXINT_MASK);
120 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
121
122 if (is_dma_capable() && !dma_off)
123 WARNING("dma still active\n");
124}
125
126
127#define portstate(stmt) stmt
128
129/*
130 * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM,
131 * which doesn't wire DRVVBUS to the FET that switches it. Unclear
132 * if that's a problem with the DM6446 chip or just with that board.
133 *
134 * In either case, the DM355 EVM automates DRVVBUS the normal way,
135 * when J10 is out, and TI documents it as handling OTG.
136 */
137
138#ifdef CONFIG_MACH_DAVINCI_EVM
139
140static int vbus_state = -1;
141
142/* I2C operations are always synchronous, and require a task context.
143 * With unloaded systems, using the shared workqueue seems to suffice
144 * to satisfy the 100msec A_WAIT_VRISE timeout...
145 */
146static void evm_deferred_drvvbus(struct work_struct *ignored)
147{
148 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
149 vbus_state = !vbus_state;
150}
151
152#endif /* EVM */
153
154static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate)
155{
156#ifdef CONFIG_MACH_DAVINCI_EVM
157 if (is_on)
158 is_on = 1;
159
160 if (vbus_state == is_on)
161 return;
162 vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
163
164 if (machine_is_davinci_evm()) {
165 static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
166
167 if (immediate)
168 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
169 else
170 schedule_work(&evm_vbus_work);
171 }
172 if (immediate)
173 vbus_state = is_on;
174#endif
175}
176
177static void davinci_musb_set_vbus(struct musb *musb, int is_on)
178{
179 WARN_ON(is_on && is_peripheral_active(musb));
180 davinci_musb_source_power(musb, is_on, 0);
181}
182
183
184#define POLL_SECONDS 2
185
186static void otg_timer(struct timer_list *t)
187{
188 struct musb *musb = from_timer(musb, t, dev_timer);
189 void __iomem *mregs = musb->mregs;
190 u8 devctl;
191 unsigned long flags;
192
193 /* We poll because DaVinci's won't expose several OTG-critical
194 * status change events (from the transceiver) otherwise.
195 */
196 devctl = musb_readb(mregs, MUSB_DEVCTL);
197 dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
198 usb_otg_state_string(musb->xceiv->otg->state));
199
200 spin_lock_irqsave(&musb->lock, flags);
201 switch (musb->xceiv->otg->state) {
202 case OTG_STATE_A_WAIT_VFALL:
203 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
204 * seems to mis-handle session "start" otherwise (or in our
205 * case "recover"), in routine "VBUS was valid by the time
206 * VBUSERR got reported during enumeration" cases.
207 */
208 if (devctl & MUSB_DEVCTL_VBUS) {
209 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
210 break;
211 }
212 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
213 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
214 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
215 break;
216 case OTG_STATE_B_IDLE:
217 /*
218 * There's no ID-changed IRQ, so we have no good way to tell
219 * when to switch to the A-Default state machine (by setting
220 * the DEVCTL.SESSION flag).
221 *
222 * Workaround: whenever we're in B_IDLE, try setting the
223 * session flag every few seconds. If it works, ID was
224 * grounded and we're now in the A-Default state machine.
225 *
226 * NOTE setting the session flag is _supposed_ to trigger
227 * SRP, but clearly it doesn't.
228 */
229 musb_writeb(mregs, MUSB_DEVCTL,
230 devctl | MUSB_DEVCTL_SESSION);
231 devctl = musb_readb(mregs, MUSB_DEVCTL);
232 if (devctl & MUSB_DEVCTL_BDEVICE)
233 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
234 else
235 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
236 break;
237 default:
238 break;
239 }
240 spin_unlock_irqrestore(&musb->lock, flags);
241}
242
243static irqreturn_t davinci_musb_interrupt(int irq, void *__hci)
244{
245 unsigned long flags;
246 irqreturn_t retval = IRQ_NONE;
247 struct musb *musb = __hci;
248 struct usb_otg *otg = musb->xceiv->otg;
249 void __iomem *tibase = musb->ctrl_base;
250 struct cppi *cppi;
251 u32 tmp;
252
253 spin_lock_irqsave(&musb->lock, flags);
254
255 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
256 * the Mentor registers (except for setup), use the TI ones and EOI.
257 *
258 * Docs describe irq "vector" registers associated with the CPPI and
259 * USB EOI registers. These hold a bitmask corresponding to the
260 * current IRQ, not an irq handler address. Would using those bits
261 * resolve some of the races observed in this dispatch code??
262 */
263
264 /* CPPI interrupts share the same IRQ line, but have their own
265 * mask, state, "vector", and EOI registers.
266 */
267 cppi = container_of(musb->dma_controller, struct cppi, controller);
268 if (is_cppi_enabled(musb) && musb->dma_controller && !cppi->irq)
269 retval = cppi_interrupt(irq, __hci);
270
271 /* ack and handle non-CPPI interrupts */
272 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
273 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
274 dev_dbg(musb->controller, "IRQ %08x\n", tmp);
275
276 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
277 >> DAVINCI_USB_RXINT_SHIFT;
278 musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
279 >> DAVINCI_USB_TXINT_SHIFT;
280 musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
281 >> DAVINCI_USB_USBINT_SHIFT;
282
283 /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
284 * DaVinci's missing ID change IRQ. We need an ID change IRQ to
285 * switch appropriately between halves of the OTG state machine.
286 * Managing DEVCTL.SESSION per Mentor docs requires we know its
287 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
288 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
289 */
290 if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
291 int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
292 void __iomem *mregs = musb->mregs;
293 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
294 int err = musb->int_usb & MUSB_INTR_VBUSERROR;
295
296 err = musb->int_usb & MUSB_INTR_VBUSERROR;
297 if (err) {
298 /* The Mentor core doesn't debounce VBUS as needed
299 * to cope with device connect current spikes. This
300 * means it's not uncommon for bus-powered devices
301 * to get VBUS errors during enumeration.
302 *
303 * This is a workaround, but newer RTL from Mentor
304 * seems to allow a better one: "re"starting sessions
305 * without waiting (on EVM, a **long** time) for VBUS
306 * to stop registering in devctl.
307 */
308 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
309 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
310 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
311 WARNING("VBUS error workaround (delay coming)\n");
312 } else if (drvvbus) {
313 MUSB_HST_MODE(musb);
314 otg->default_a = 1;
315 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
316 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
317 del_timer(&musb->dev_timer);
318 } else {
319 musb->is_active = 0;
320 MUSB_DEV_MODE(musb);
321 otg->default_a = 0;
322 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
323 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
324 }
325
326 /* NOTE: this must complete poweron within 100 msec
327 * (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
328 */
329 davinci_musb_source_power(musb, drvvbus, 0);
330 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
331 drvvbus ? "on" : "off",
332 usb_otg_state_string(musb->xceiv->otg->state),
333 err ? " ERROR" : "",
334 devctl);
335 retval = IRQ_HANDLED;
336 }
337
338 if (musb->int_tx || musb->int_rx || musb->int_usb)
339 retval |= musb_interrupt(musb);
340
341 /* irq stays asserted until EOI is written */
342 musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
343
344 /* poll for ID change */
345 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
346 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
347
348 spin_unlock_irqrestore(&musb->lock, flags);
349
350 return retval;
351}
352
353static int davinci_musb_set_mode(struct musb *musb, u8 mode)
354{
355 /* EVM can't do this (right?) */
356 return -EIO;
357}
358
359static int davinci_musb_init(struct musb *musb)
360{
361 void __iomem *tibase = musb->ctrl_base;
362 u32 revision;
363 int ret = -ENODEV;
364
365 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
366 if (IS_ERR_OR_NULL(musb->xceiv)) {
367 ret = -EPROBE_DEFER;
368 goto unregister;
369 }
370
371 musb->mregs += DAVINCI_BASE_OFFSET;
372
373 /* returns zero if e.g. not clocked */
374 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
375 if (revision == 0)
376 goto fail;
377
378 timer_setup(&musb->dev_timer, otg_timer, 0);
379
380 davinci_musb_source_power(musb, 0, 1);
381
382 /* dm355 EVM swaps D+/D- for signal integrity, and
383 * is clocked from the main 24 MHz crystal.
384 */
385 if (machine_is_davinci_dm355_evm()) {
386 u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
387
388 phy_ctrl &= ~(3 << 9);
389 phy_ctrl |= USBPHY_DATAPOL;
390 __raw_writel(phy_ctrl, USB_PHY_CTRL);
391 }
392
393 /* On dm355, the default-A state machine needs DRVVBUS control.
394 * If we won't be a host, there's no need to turn it on.
395 */
396 if (cpu_is_davinci_dm355()) {
397 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
398
399 deepsleep &= ~DRVVBUS_FORCE;
400 __raw_writel(deepsleep, DM355_DEEPSLEEP);
401 }
402
403 /* reset the controller */
404 musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
405
406 /* start the on-chip PHY and its PLL */
407 phy_on();
408
409 msleep(5);
410
411 /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
412 pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
413 revision, __raw_readl(USB_PHY_CTRL),
414 musb_readb(tibase, DAVINCI_USB_CTRL_REG));
415
416 musb->isr = davinci_musb_interrupt;
417 return 0;
418
419fail:
420 usb_put_phy(musb->xceiv);
421unregister:
422 usb_phy_generic_unregister();
423 return ret;
424}
425
426static int davinci_musb_exit(struct musb *musb)
427{
428 del_timer_sync(&musb->dev_timer);
429
430 /* force VBUS off */
431 if (cpu_is_davinci_dm355()) {
432 u32 deepsleep = __raw_readl(DM355_DEEPSLEEP);
433
434 deepsleep &= ~DRVVBUS_FORCE;
435 deepsleep |= DRVVBUS_OVERRIDE;
436 __raw_writel(deepsleep, DM355_DEEPSLEEP);
437 }
438
439 davinci_musb_source_power(musb, 0 /*off*/, 1);
440
441 /* delay, to avoid problems with module reload */
442 if (musb->xceiv->otg->default_a) {
443 int maxdelay = 30;
444 u8 devctl, warn = 0;
445
446 /* if there's no peripheral connected, this can take a
447 * long time to fall, especially on EVM with huge C133.
448 */
449 do {
450 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
451 if (!(devctl & MUSB_DEVCTL_VBUS))
452 break;
453 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
454 warn = devctl & MUSB_DEVCTL_VBUS;
455 dev_dbg(musb->controller, "VBUS %d\n",
456 warn >> MUSB_DEVCTL_VBUS_SHIFT);
457 }
458 msleep(1000);
459 maxdelay--;
460 } while (maxdelay > 0);
461
462 /* in OTG mode, another host might be connected */
463 if (devctl & MUSB_DEVCTL_VBUS)
464 dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
465 }
466
467 phy_off();
468
469 usb_put_phy(musb->xceiv);
470
471 return 0;
472}
473
474static const struct musb_platform_ops davinci_ops = {
475 .quirks = MUSB_DMA_CPPI,
476 .init = davinci_musb_init,
477 .exit = davinci_musb_exit,
478
479#ifdef CONFIG_USB_TI_CPPI_DMA
480 .dma_init = cppi_dma_controller_create,
481 .dma_exit = cppi_dma_controller_destroy,
482#endif
483 .enable = davinci_musb_enable,
484 .disable = davinci_musb_disable,
485
486 .set_mode = davinci_musb_set_mode,
487
488 .set_vbus = davinci_musb_set_vbus,
489};
490
491static const struct platform_device_info davinci_dev_info = {
492 .name = "musb-hdrc",
493 .id = PLATFORM_DEVID_AUTO,
494 .dma_mask = DMA_BIT_MASK(32),
495};
496
497static int davinci_probe(struct platform_device *pdev)
498{
499 struct resource musb_resources[3];
500 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
501 struct platform_device *musb;
502 struct davinci_glue *glue;
503 struct platform_device_info pinfo;
504 struct clk *clk;
505
506 int ret = -ENOMEM;
507
508 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
509 if (!glue)
510 goto err0;
511
512 clk = devm_clk_get(&pdev->dev, "usb");
513 if (IS_ERR(clk)) {
514 dev_err(&pdev->dev, "failed to get clock\n");
515 ret = PTR_ERR(clk);
516 goto err0;
517 }
518
519 ret = clk_enable(clk);
520 if (ret) {
521 dev_err(&pdev->dev, "failed to enable clock\n");
522 goto err0;
523 }
524
525 glue->dev = &pdev->dev;
526 glue->clk = clk;
527
528 pdata->platform_ops = &davinci_ops;
529
530 usb_phy_generic_register();
531 platform_set_drvdata(pdev, glue);
532
533 memset(musb_resources, 0x00, sizeof(*musb_resources) *
534 ARRAY_SIZE(musb_resources));
535
536 musb_resources[0].name = pdev->resource[0].name;
537 musb_resources[0].start = pdev->resource[0].start;
538 musb_resources[0].end = pdev->resource[0].end;
539 musb_resources[0].flags = pdev->resource[0].flags;
540
541 musb_resources[1].name = pdev->resource[1].name;
542 musb_resources[1].start = pdev->resource[1].start;
543 musb_resources[1].end = pdev->resource[1].end;
544 musb_resources[1].flags = pdev->resource[1].flags;
545
546 /*
547 * For DM6467 3 resources are passed. A placeholder for the 3rd
548 * resource is always there, so it's safe to always copy it...
549 */
550 musb_resources[2].name = pdev->resource[2].name;
551 musb_resources[2].start = pdev->resource[2].start;
552 musb_resources[2].end = pdev->resource[2].end;
553 musb_resources[2].flags = pdev->resource[2].flags;
554
555 pinfo = davinci_dev_info;
556 pinfo.parent = &pdev->dev;
557 pinfo.res = musb_resources;
558 pinfo.num_res = ARRAY_SIZE(musb_resources);
559 pinfo.data = pdata;
560 pinfo.size_data = sizeof(*pdata);
561
562 glue->musb = musb = platform_device_register_full(&pinfo);
563 if (IS_ERR(musb)) {
564 ret = PTR_ERR(musb);
565 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
566 goto err1;
567 }
568
569 return 0;
570
571err1:
572 clk_disable(clk);
573
574err0:
575 return ret;
576}
577
578static int davinci_remove(struct platform_device *pdev)
579{
580 struct davinci_glue *glue = platform_get_drvdata(pdev);
581
582 platform_device_unregister(glue->musb);
583 usb_phy_generic_unregister();
584 clk_disable(glue->clk);
585
586 return 0;
587}
588
589static struct platform_driver davinci_driver = {
590 .probe = davinci_probe,
591 .remove = davinci_remove,
592 .driver = {
593 .name = "musb-davinci",
594 },
595};
596
597MODULE_DESCRIPTION("DaVinci MUSB Glue Layer");
598MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
599MODULE_LICENSE("GPL v2");
600module_platform_driver(davinci_driver);