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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2004-2016 Synopsys, Inc.
4 */
5
6#include <linux/kernel.h>
7#include <linux/module.h>
8#include <linux/of_device.h>
9#include <linux/usb/of.h>
10
11#include "core.h"
12
13static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
14{
15 struct dwc2_core_params *p = &hsotg->params;
16
17 p->host_rx_fifo_size = 774;
18 p->max_transfer_size = 65535;
19 p->max_packet_count = 511;
20 p->ahbcfg = 0x10;
21}
22
23static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
24{
25 struct dwc2_core_params *p = &hsotg->params;
26
27 p->otg_caps.hnp_support = false;
28 p->otg_caps.srp_support = false;
29 p->speed = DWC2_SPEED_PARAM_HIGH;
30 p->host_rx_fifo_size = 512;
31 p->host_nperio_tx_fifo_size = 512;
32 p->host_perio_tx_fifo_size = 512;
33 p->max_transfer_size = 65535;
34 p->max_packet_count = 511;
35 p->host_channels = 16;
36 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
37 p->phy_utmi_width = 8;
38 p->i2c_enable = false;
39 p->reload_ctl = false;
40 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
41 GAHBCFG_HBSTLEN_SHIFT;
42 p->change_speed_quirk = true;
43 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
44}
45
46static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg)
47{
48 struct dwc2_core_params *p = &hsotg->params;
49
50 p->otg_caps.hnp_support = false;
51 p->speed = DWC2_SPEED_PARAM_HIGH;
52 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
53 p->phy_utmi_width = 16;
54 p->activate_ingenic_overcurrent_detection =
55 !device_property_read_bool(hsotg->dev, "disable-over-current");
56}
57
58static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg)
59{
60 struct dwc2_core_params *p = &hsotg->params;
61
62 p->otg_caps.hnp_support = false;
63 p->speed = DWC2_SPEED_PARAM_HIGH;
64 p->host_channels = 16;
65 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
66 p->phy_utmi_width = 16;
67 p->activate_ingenic_overcurrent_detection =
68 !device_property_read_bool(hsotg->dev, "disable-over-current");
69}
70
71static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg)
72{
73 struct dwc2_core_params *p = &hsotg->params;
74
75 p->otg_caps.hnp_support = false;
76 p->speed = DWC2_SPEED_PARAM_HIGH;
77 p->host_rx_fifo_size = 1024;
78 p->host_nperio_tx_fifo_size = 1024;
79 p->host_perio_tx_fifo_size = 1024;
80 p->host_channels = 16;
81 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
82 p->phy_utmi_width = 16;
83 p->activate_ingenic_overcurrent_detection =
84 !device_property_read_bool(hsotg->dev, "disable-over-current");
85}
86
87static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
88{
89 struct dwc2_core_params *p = &hsotg->params;
90
91 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
92 p->no_clock_gating = true;
93 p->phy_utmi_width = 8;
94}
95
96static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg)
97{
98 struct dwc2_core_params *p = &hsotg->params;
99
100 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
101 p->no_clock_gating = true;
102}
103
104static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
105{
106 struct dwc2_core_params *p = &hsotg->params;
107
108 p->otg_caps.hnp_support = false;
109 p->otg_caps.srp_support = false;
110 p->host_rx_fifo_size = 525;
111 p->host_nperio_tx_fifo_size = 128;
112 p->host_perio_tx_fifo_size = 256;
113 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
114 GAHBCFG_HBSTLEN_SHIFT;
115 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
116 p->lpm = false;
117 p->lpm_clock_gating = false;
118 p->besl = false;
119 p->hird_threshold_en = false;
120}
121
122static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
123{
124 struct dwc2_core_params *p = &hsotg->params;
125
126 p->otg_caps.hnp_support = false;
127 p->otg_caps.srp_support = false;
128 p->host_rx_fifo_size = 288;
129 p->host_nperio_tx_fifo_size = 128;
130 p->host_perio_tx_fifo_size = 96;
131 p->max_transfer_size = 65535;
132 p->max_packet_count = 511;
133 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
134 GAHBCFG_HBSTLEN_SHIFT;
135}
136
137static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
138{
139 struct dwc2_core_params *p = &hsotg->params;
140
141 p->otg_caps.hnp_support = false;
142 p->otg_caps.srp_support = false;
143 p->speed = DWC2_SPEED_PARAM_HIGH;
144 p->host_rx_fifo_size = 512;
145 p->host_nperio_tx_fifo_size = 500;
146 p->host_perio_tx_fifo_size = 500;
147 p->host_channels = 16;
148 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
149 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
150 GAHBCFG_HBSTLEN_SHIFT;
151 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
152}
153
154static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
155{
156 struct dwc2_core_params *p = &hsotg->params;
157
158 p->lpm = false;
159 p->lpm_clock_gating = false;
160 p->besl = false;
161 p->hird_threshold_en = false;
162}
163
164static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
165{
166 struct dwc2_core_params *p = &hsotg->params;
167
168 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
169}
170
171static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
172{
173 struct dwc2_core_params *p = &hsotg->params;
174
175 p->otg_caps.hnp_support = false;
176 p->otg_caps.srp_support = false;
177 p->speed = DWC2_SPEED_PARAM_FULL;
178 p->host_rx_fifo_size = 128;
179 p->host_nperio_tx_fifo_size = 96;
180 p->host_perio_tx_fifo_size = 96;
181 p->max_packet_count = 256;
182 p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
183 p->i2c_enable = false;
184 p->activate_stm_fs_transceiver = true;
185}
186
187static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
188{
189 struct dwc2_core_params *p = &hsotg->params;
190
191 p->host_rx_fifo_size = 622;
192 p->host_nperio_tx_fifo_size = 128;
193 p->host_perio_tx_fifo_size = 256;
194}
195
196static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
197{
198 struct dwc2_core_params *p = &hsotg->params;
199
200 p->otg_caps.hnp_support = false;
201 p->otg_caps.srp_support = false;
202 p->otg_caps.otg_rev = 0x200;
203 p->speed = DWC2_SPEED_PARAM_FULL;
204 p->host_rx_fifo_size = 128;
205 p->host_nperio_tx_fifo_size = 96;
206 p->host_perio_tx_fifo_size = 96;
207 p->max_packet_count = 256;
208 p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
209 p->i2c_enable = false;
210 p->activate_stm_fs_transceiver = true;
211 p->activate_stm_id_vb_detection = true;
212 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
213 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
214 p->host_support_fs_ls_low_power = true;
215 p->host_ls_low_power_phy_clk = true;
216}
217
218static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
219{
220 struct dwc2_core_params *p = &hsotg->params;
221
222 p->otg_caps.hnp_support = false;
223 p->otg_caps.srp_support = false;
224 p->otg_caps.otg_rev = 0x200;
225 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
226 p->host_rx_fifo_size = 440;
227 p->host_nperio_tx_fifo_size = 256;
228 p->host_perio_tx_fifo_size = 256;
229 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
230 p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
231 p->lpm = false;
232 p->lpm_clock_gating = false;
233 p->besl = false;
234 p->hird_threshold_en = false;
235}
236
237const struct of_device_id dwc2_of_match_table[] = {
238 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
239 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
240 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params },
241 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params },
242 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params },
243 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params },
244 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params },
245 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
246 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
247 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
248 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
249 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
250 { .compatible = "snps,dwc2" },
251 { .compatible = "samsung,s3c6400-hsotg",
252 .data = dwc2_set_s3c6400_params },
253 { .compatible = "amlogic,meson8-usb",
254 .data = dwc2_set_amlogic_params },
255 { .compatible = "amlogic,meson8b-usb",
256 .data = dwc2_set_amlogic_params },
257 { .compatible = "amlogic,meson-gxbb-usb",
258 .data = dwc2_set_amlogic_params },
259 { .compatible = "amlogic,meson-g12a-usb",
260 .data = dwc2_set_amlogic_g12a_params },
261 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
262 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
263 { .compatible = "st,stm32f4x9-fsotg",
264 .data = dwc2_set_stm32f4x9_fsotg_params },
265 { .compatible = "st,stm32f4x9-hsotg" },
266 { .compatible = "st,stm32f7-hsotg",
267 .data = dwc2_set_stm32f7_hsotg_params },
268 { .compatible = "st,stm32mp15-fsotg",
269 .data = dwc2_set_stm32mp15_fsotg_params },
270 { .compatible = "st,stm32mp15-hsotg",
271 .data = dwc2_set_stm32mp15_hsotg_params },
272 { .compatible = "intel,socfpga-agilex-hsotg",
273 .data = dwc2_set_socfpga_agilex_params },
274 {},
275};
276MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
277
278const struct acpi_device_id dwc2_acpi_match[] = {
279 { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params },
280 { },
281};
282MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match);
283
284static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
285{
286 switch (hsotg->hw_params.op_mode) {
287 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
288 hsotg->params.otg_caps.hnp_support = true;
289 hsotg->params.otg_caps.srp_support = true;
290 break;
291 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
292 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
293 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
294 hsotg->params.otg_caps.hnp_support = false;
295 hsotg->params.otg_caps.srp_support = true;
296 break;
297 default:
298 hsotg->params.otg_caps.hnp_support = false;
299 hsotg->params.otg_caps.srp_support = false;
300 break;
301 }
302}
303
304static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
305{
306 int val;
307 u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
308
309 val = DWC2_PHY_TYPE_PARAM_FS;
310 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
311 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
312 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
313 val = DWC2_PHY_TYPE_PARAM_UTMI;
314 else
315 val = DWC2_PHY_TYPE_PARAM_ULPI;
316 }
317
318 if (dwc2_is_fs_iot(hsotg))
319 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
320
321 hsotg->params.phy_type = val;
322}
323
324static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
325{
326 int val;
327
328 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
329 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
330
331 if (dwc2_is_fs_iot(hsotg))
332 val = DWC2_SPEED_PARAM_FULL;
333
334 if (dwc2_is_hs_iot(hsotg))
335 val = DWC2_SPEED_PARAM_HIGH;
336
337 hsotg->params.speed = val;
338}
339
340static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
341{
342 int val;
343
344 val = (hsotg->hw_params.utmi_phy_data_width ==
345 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
346
347 if (hsotg->phy) {
348 /*
349 * If using the generic PHY framework, check if the PHY bus
350 * width is 8-bit and set the phyif appropriately.
351 */
352 if (phy_get_bus_width(hsotg->phy) == 8)
353 val = 8;
354 }
355
356 hsotg->params.phy_utmi_width = val;
357}
358
359static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
360{
361 struct dwc2_core_params *p = &hsotg->params;
362 int depth_average;
363 int fifo_count;
364 int i;
365
366 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
367
368 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
369 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
370 for (i = 1; i <= fifo_count; i++)
371 p->g_tx_fifo_size[i] = depth_average;
372}
373
374static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
375{
376 int val;
377
378 if (hsotg->hw_params.hibernation)
379 val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
380 else if (hsotg->hw_params.power_optimized)
381 val = DWC2_POWER_DOWN_PARAM_PARTIAL;
382 else
383 val = DWC2_POWER_DOWN_PARAM_NONE;
384
385 hsotg->params.power_down = val;
386}
387
388static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
389{
390 struct dwc2_core_params *p = &hsotg->params;
391
392 p->lpm = hsotg->hw_params.lpm_mode;
393 if (p->lpm) {
394 p->lpm_clock_gating = true;
395 p->besl = true;
396 p->hird_threshold_en = true;
397 p->hird_threshold = 4;
398 } else {
399 p->lpm_clock_gating = false;
400 p->besl = false;
401 p->hird_threshold_en = false;
402 }
403}
404
405/**
406 * dwc2_set_default_params() - Set all core parameters to their
407 * auto-detected default values.
408 *
409 * @hsotg: Programming view of the DWC_otg controller
410 *
411 */
412static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
413{
414 struct dwc2_hw_params *hw = &hsotg->hw_params;
415 struct dwc2_core_params *p = &hsotg->params;
416 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
417
418 dwc2_set_param_otg_cap(hsotg);
419 dwc2_set_param_phy_type(hsotg);
420 dwc2_set_param_speed(hsotg);
421 dwc2_set_param_phy_utmi_width(hsotg);
422 dwc2_set_param_power_down(hsotg);
423 dwc2_set_param_lpm(hsotg);
424 p->phy_ulpi_ddr = false;
425 p->phy_ulpi_ext_vbus = false;
426
427 p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
428 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
429 p->i2c_enable = hw->i2c_enable;
430 p->acg_enable = hw->acg_enable;
431 p->ulpi_fs_ls = false;
432 p->ts_dline = false;
433 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
434 p->uframe_sched = true;
435 p->external_id_pin_ctl = false;
436 p->ipg_isoc_en = false;
437 p->service_interval = false;
438 p->max_packet_count = hw->max_packet_count;
439 p->max_transfer_size = hw->max_transfer_size;
440 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
441 p->ref_clk_per = 33333;
442 p->sof_cnt_wkup_alert = 100;
443
444 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
445 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
446 p->host_dma = dma_capable;
447 p->dma_desc_enable = false;
448 p->dma_desc_fs_enable = false;
449 p->host_support_fs_ls_low_power = false;
450 p->host_ls_low_power_phy_clk = false;
451 p->host_channels = hw->host_channels;
452 p->host_rx_fifo_size = hw->rx_fifo_size;
453 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
454 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
455 }
456
457 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
458 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
459 p->g_dma = dma_capable;
460 p->g_dma_desc = hw->dma_desc_enable;
461
462 /*
463 * The values for g_rx_fifo_size (2048) and
464 * g_np_tx_fifo_size (1024) come from the legacy s3c
465 * gadget driver. These defaults have been hard-coded
466 * for some time so many platforms depend on these
467 * values. Leave them as defaults for now and only
468 * auto-detect if the hardware does not support the
469 * default.
470 */
471 p->g_rx_fifo_size = 2048;
472 p->g_np_tx_fifo_size = 1024;
473 dwc2_set_param_tx_fifo_sizes(hsotg);
474 }
475}
476
477/**
478 * dwc2_get_device_properties() - Read in device properties.
479 *
480 * @hsotg: Programming view of the DWC_otg controller
481 *
482 * Read in the device properties and adjust core parameters if needed.
483 */
484static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
485{
486 struct dwc2_core_params *p = &hsotg->params;
487 int num;
488
489 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
490 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
491 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
492 &p->g_rx_fifo_size);
493
494 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
495 &p->g_np_tx_fifo_size);
496
497 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
498 if (num > 0) {
499 num = min(num, 15);
500 memset(p->g_tx_fifo_size, 0,
501 sizeof(p->g_tx_fifo_size));
502 device_property_read_u32_array(hsotg->dev,
503 "g-tx-fifo-size",
504 &p->g_tx_fifo_size[1],
505 num);
506 }
507
508 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps);
509 }
510
511 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
512 p->oc_disable = true;
513}
514
515static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
516{
517 int valid = 1;
518
519 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) {
520 /* check HNP && SRP capable */
521 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
522 valid = 0;
523 } else if (!hsotg->params.otg_caps.hnp_support) {
524 /* check SRP only capable */
525 if (hsotg->params.otg_caps.srp_support) {
526 switch (hsotg->hw_params.op_mode) {
527 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
528 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
529 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
530 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
531 break;
532 default:
533 valid = 0;
534 break;
535 }
536 }
537 /* else: NO HNP && NO SRP capable: always valid */
538 } else {
539 valid = 0;
540 }
541
542 if (!valid)
543 dwc2_set_param_otg_cap(hsotg);
544}
545
546static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
547{
548 int valid = 0;
549 u32 hs_phy_type;
550 u32 fs_phy_type;
551
552 hs_phy_type = hsotg->hw_params.hs_phy_type;
553 fs_phy_type = hsotg->hw_params.fs_phy_type;
554
555 switch (hsotg->params.phy_type) {
556 case DWC2_PHY_TYPE_PARAM_FS:
557 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
558 valid = 1;
559 break;
560 case DWC2_PHY_TYPE_PARAM_UTMI:
561 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
562 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
563 valid = 1;
564 break;
565 case DWC2_PHY_TYPE_PARAM_ULPI:
566 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
567 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
568 valid = 1;
569 break;
570 default:
571 break;
572 }
573
574 if (!valid)
575 dwc2_set_param_phy_type(hsotg);
576}
577
578static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
579{
580 int valid = 1;
581 int phy_type = hsotg->params.phy_type;
582 int speed = hsotg->params.speed;
583
584 switch (speed) {
585 case DWC2_SPEED_PARAM_HIGH:
586 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
587 (phy_type == DWC2_PHY_TYPE_PARAM_FS))
588 valid = 0;
589 break;
590 case DWC2_SPEED_PARAM_FULL:
591 case DWC2_SPEED_PARAM_LOW:
592 break;
593 default:
594 valid = 0;
595 break;
596 }
597
598 if (!valid)
599 dwc2_set_param_speed(hsotg);
600}
601
602static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
603{
604 int valid = 0;
605 int param = hsotg->params.phy_utmi_width;
606 int width = hsotg->hw_params.utmi_phy_data_width;
607
608 switch (width) {
609 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
610 valid = (param == 8);
611 break;
612 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
613 valid = (param == 16);
614 break;
615 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
616 valid = (param == 8 || param == 16);
617 break;
618 }
619
620 if (!valid)
621 dwc2_set_param_phy_utmi_width(hsotg);
622}
623
624static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
625{
626 int param = hsotg->params.power_down;
627
628 switch (param) {
629 case DWC2_POWER_DOWN_PARAM_NONE:
630 break;
631 case DWC2_POWER_DOWN_PARAM_PARTIAL:
632 if (hsotg->hw_params.power_optimized)
633 break;
634 dev_dbg(hsotg->dev,
635 "Partial power down isn't supported by HW\n");
636 param = DWC2_POWER_DOWN_PARAM_NONE;
637 break;
638 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
639 if (hsotg->hw_params.hibernation)
640 break;
641 dev_dbg(hsotg->dev,
642 "Hibernation isn't supported by HW\n");
643 param = DWC2_POWER_DOWN_PARAM_NONE;
644 break;
645 default:
646 dev_err(hsotg->dev,
647 "%s: Invalid parameter power_down=%d\n",
648 __func__, param);
649 param = DWC2_POWER_DOWN_PARAM_NONE;
650 break;
651 }
652
653 hsotg->params.power_down = param;
654}
655
656static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
657{
658 int fifo_count;
659 int fifo;
660 int min;
661 u32 total = 0;
662 u32 dptxfszn;
663
664 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
665 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
666
667 for (fifo = 1; fifo <= fifo_count; fifo++)
668 total += hsotg->params.g_tx_fifo_size[fifo];
669
670 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
671 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
672 __func__);
673 dwc2_set_param_tx_fifo_sizes(hsotg);
674 }
675
676 for (fifo = 1; fifo <= fifo_count; fifo++) {
677 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
678
679 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
680 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) {
681 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
682 __func__, fifo,
683 hsotg->params.g_tx_fifo_size[fifo]);
684 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
685 }
686 }
687}
688
689#define CHECK_RANGE(_param, _min, _max, _def) do { \
690 if ((int)(hsotg->params._param) < (_min) || \
691 (hsotg->params._param) > (_max)) { \
692 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
693 __func__, #_param, hsotg->params._param); \
694 hsotg->params._param = (_def); \
695 } \
696 } while (0)
697
698#define CHECK_BOOL(_param, _check) do { \
699 if (hsotg->params._param && !(_check)) { \
700 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
701 __func__, #_param, hsotg->params._param); \
702 hsotg->params._param = false; \
703 } \
704 } while (0)
705
706static void dwc2_check_params(struct dwc2_hsotg *hsotg)
707{
708 struct dwc2_hw_params *hw = &hsotg->hw_params;
709 struct dwc2_core_params *p = &hsotg->params;
710 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
711
712 dwc2_check_param_otg_cap(hsotg);
713 dwc2_check_param_phy_type(hsotg);
714 dwc2_check_param_speed(hsotg);
715 dwc2_check_param_phy_utmi_width(hsotg);
716 dwc2_check_param_power_down(hsotg);
717 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
718 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
719 CHECK_BOOL(i2c_enable, hw->i2c_enable);
720 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
721 CHECK_BOOL(acg_enable, hw->acg_enable);
722 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
723 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
724 CHECK_BOOL(lpm, hw->lpm_mode);
725 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
726 CHECK_BOOL(besl, hsotg->params.lpm);
727 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
728 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
729 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
730 CHECK_BOOL(service_interval, hw->service_interval_mode);
731 CHECK_RANGE(max_packet_count,
732 15, hw->max_packet_count,
733 hw->max_packet_count);
734 CHECK_RANGE(max_transfer_size,
735 2047, hw->max_transfer_size,
736 hw->max_transfer_size);
737
738 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
739 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
740 CHECK_BOOL(host_dma, dma_capable);
741 CHECK_BOOL(dma_desc_enable, p->host_dma);
742 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
743 CHECK_BOOL(host_ls_low_power_phy_clk,
744 p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
745 CHECK_RANGE(host_channels,
746 1, hw->host_channels,
747 hw->host_channels);
748 CHECK_RANGE(host_rx_fifo_size,
749 16, hw->rx_fifo_size,
750 hw->rx_fifo_size);
751 CHECK_RANGE(host_nperio_tx_fifo_size,
752 16, hw->host_nperio_tx_fifo_size,
753 hw->host_nperio_tx_fifo_size);
754 CHECK_RANGE(host_perio_tx_fifo_size,
755 16, hw->host_perio_tx_fifo_size,
756 hw->host_perio_tx_fifo_size);
757 }
758
759 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
760 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
761 CHECK_BOOL(g_dma, dma_capable);
762 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
763 CHECK_RANGE(g_rx_fifo_size,
764 16, hw->rx_fifo_size,
765 hw->rx_fifo_size);
766 CHECK_RANGE(g_np_tx_fifo_size,
767 16, hw->dev_nperio_tx_fifo_size,
768 hw->dev_nperio_tx_fifo_size);
769 dwc2_check_param_tx_fifo_sizes(hsotg);
770 }
771}
772
773/*
774 * Gets host hardware parameters. Forces host mode if not currently in
775 * host mode. Should be called immediately after a core soft reset in
776 * order to get the reset values.
777 */
778static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
779{
780 struct dwc2_hw_params *hw = &hsotg->hw_params;
781 u32 gnptxfsiz;
782 u32 hptxfsiz;
783
784 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
785 return;
786
787 dwc2_force_mode(hsotg, true);
788
789 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
790 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
791
792 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
793 FIFOSIZE_DEPTH_SHIFT;
794 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
795 FIFOSIZE_DEPTH_SHIFT;
796}
797
798/*
799 * Gets device hardware parameters. Forces device mode if not
800 * currently in device mode. Should be called immediately after a core
801 * soft reset in order to get the reset values.
802 */
803static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
804{
805 struct dwc2_hw_params *hw = &hsotg->hw_params;
806 u32 gnptxfsiz;
807 int fifo, fifo_count;
808
809 if (hsotg->dr_mode == USB_DR_MODE_HOST)
810 return;
811
812 dwc2_force_mode(hsotg, false);
813
814 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
815
816 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
817
818 for (fifo = 1; fifo <= fifo_count; fifo++) {
819 hw->g_tx_fifo_size[fifo] =
820 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
821 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
822 }
823
824 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
825 FIFOSIZE_DEPTH_SHIFT;
826}
827
828/**
829 * dwc2_get_hwparams() - During device initialization, read various hardware
830 * configuration registers and interpret the contents.
831 *
832 * @hsotg: Programming view of the DWC_otg controller
833 *
834 */
835int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
836{
837 struct dwc2_hw_params *hw = &hsotg->hw_params;
838 unsigned int width;
839 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
840 u32 grxfsiz;
841
842 hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
843 hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
844 hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
845 hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
846 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
847
848 /* hwcfg1 */
849 hw->dev_ep_dirs = hwcfg1;
850
851 /* hwcfg2 */
852 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
853 GHWCFG2_OP_MODE_SHIFT;
854 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
855 GHWCFG2_ARCHITECTURE_SHIFT;
856 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
857 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
858 GHWCFG2_NUM_HOST_CHAN_SHIFT);
859 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
860 GHWCFG2_HS_PHY_TYPE_SHIFT;
861 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
862 GHWCFG2_FS_PHY_TYPE_SHIFT;
863 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
864 GHWCFG2_NUM_DEV_EP_SHIFT;
865 hw->nperio_tx_q_depth =
866 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
867 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
868 hw->host_perio_tx_q_depth =
869 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
870 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
871 hw->dev_token_q_depth =
872 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
873 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
874
875 /* hwcfg3 */
876 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
877 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
878 hw->max_transfer_size = (1 << (width + 11)) - 1;
879 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
880 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
881 hw->max_packet_count = (1 << (width + 4)) - 1;
882 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
883 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
884 GHWCFG3_DFIFO_DEPTH_SHIFT;
885 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
886
887 /* hwcfg4 */
888 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
889 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
890 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
891 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
892 GHWCFG4_NUM_IN_EPS_SHIFT;
893 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
894 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
895 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
896 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
897 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
898 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
899 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
900 hw->service_interval_mode = !!(hwcfg4 &
901 GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
902
903 /* fifo sizes */
904 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
905 GRXFSIZ_DEPTH_SHIFT;
906 /*
907 * Host specific hardware parameters. Reading these parameters
908 * requires the controller to be in host mode. The mode will
909 * be forced, if necessary, to read these values.
910 */
911 dwc2_get_host_hwparams(hsotg);
912 dwc2_get_dev_hwparams(hsotg);
913
914 return 0;
915}
916
917typedef void (*set_params_cb)(struct dwc2_hsotg *data);
918
919int dwc2_init_params(struct dwc2_hsotg *hsotg)
920{
921 const struct of_device_id *match;
922 set_params_cb set_params;
923
924 dwc2_set_default_params(hsotg);
925 dwc2_get_device_properties(hsotg);
926
927 match = of_match_device(dwc2_of_match_table, hsotg->dev);
928 if (match && match->data) {
929 set_params = match->data;
930 set_params(hsotg);
931 } else {
932 const struct acpi_device_id *amatch;
933
934 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev);
935 if (amatch && amatch->driver_data) {
936 set_params = (set_params_cb)amatch->driver_data;
937 set_params(hsotg);
938 }
939 }
940
941 dwc2_check_params(hsotg);
942
943 return 0;
944}
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2004-2016 Synopsys, Inc.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The names of the above-listed copyright holders may not be used
15 * to endorse or promote products derived from this software without
16 * specific prior written permission.
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation; either version 2 of the License, or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
24 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
27 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
30 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
31 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
32 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/of_device.h>
39
40#include "core.h"
41
42static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
43{
44 struct dwc2_core_params *p = &hsotg->params;
45
46 p->host_rx_fifo_size = 774;
47 p->max_transfer_size = 65535;
48 p->max_packet_count = 511;
49 p->ahbcfg = 0x10;
50 p->uframe_sched = false;
51}
52
53static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
54{
55 struct dwc2_core_params *p = &hsotg->params;
56
57 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
58 p->speed = DWC2_SPEED_PARAM_HIGH;
59 p->host_rx_fifo_size = 512;
60 p->host_nperio_tx_fifo_size = 512;
61 p->host_perio_tx_fifo_size = 512;
62 p->max_transfer_size = 65535;
63 p->max_packet_count = 511;
64 p->host_channels = 16;
65 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
66 p->phy_utmi_width = 8;
67 p->i2c_enable = false;
68 p->reload_ctl = false;
69 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
70 GAHBCFG_HBSTLEN_SHIFT;
71 p->uframe_sched = false;
72 p->change_speed_quirk = true;
73}
74
75static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
76{
77 struct dwc2_core_params *p = &hsotg->params;
78
79 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
80 p->host_rx_fifo_size = 525;
81 p->host_nperio_tx_fifo_size = 128;
82 p->host_perio_tx_fifo_size = 256;
83 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
84 GAHBCFG_HBSTLEN_SHIFT;
85}
86
87static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
88{
89 struct dwc2_core_params *p = &hsotg->params;
90
91 p->otg_cap = 2;
92 p->host_rx_fifo_size = 288;
93 p->host_nperio_tx_fifo_size = 128;
94 p->host_perio_tx_fifo_size = 96;
95 p->max_transfer_size = 65535;
96 p->max_packet_count = 511;
97 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
98 GAHBCFG_HBSTLEN_SHIFT;
99}
100
101static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
102{
103 struct dwc2_core_params *p = &hsotg->params;
104
105 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
106 p->speed = DWC2_SPEED_PARAM_HIGH;
107 p->host_rx_fifo_size = 512;
108 p->host_nperio_tx_fifo_size = 500;
109 p->host_perio_tx_fifo_size = 500;
110 p->host_channels = 16;
111 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
112 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
113 GAHBCFG_HBSTLEN_SHIFT;
114 p->uframe_sched = false;
115}
116
117static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
118{
119 struct dwc2_core_params *p = &hsotg->params;
120
121 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
122}
123
124static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
125{
126 struct dwc2_core_params *p = &hsotg->params;
127
128 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
129 p->speed = DWC2_SPEED_PARAM_FULL;
130 p->host_rx_fifo_size = 128;
131 p->host_nperio_tx_fifo_size = 96;
132 p->host_perio_tx_fifo_size = 96;
133 p->max_packet_count = 256;
134 p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
135 p->i2c_enable = false;
136 p->uframe_sched = false;
137 p->activate_stm_fs_transceiver = true;
138}
139
140static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
141{
142 struct dwc2_core_params *p = &hsotg->params;
143
144 p->host_rx_fifo_size = 622;
145 p->host_nperio_tx_fifo_size = 128;
146 p->host_perio_tx_fifo_size = 256;
147}
148
149const struct of_device_id dwc2_of_match_table[] = {
150 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
151 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
152 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
153 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
154 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
155 { .compatible = "snps,dwc2" },
156 { .compatible = "samsung,s3c6400-hsotg" },
157 { .compatible = "amlogic,meson8-usb",
158 .data = dwc2_set_amlogic_params },
159 { .compatible = "amlogic,meson8b-usb",
160 .data = dwc2_set_amlogic_params },
161 { .compatible = "amlogic,meson-gxbb-usb",
162 .data = dwc2_set_amlogic_params },
163 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
164 { .compatible = "st,stm32f4x9-fsotg",
165 .data = dwc2_set_stm32f4x9_fsotg_params },
166 { .compatible = "st,stm32f4x9-hsotg" },
167 { .compatible = "st,stm32f7-hsotg",
168 .data = dwc2_set_stm32f7_hsotg_params },
169 {},
170};
171MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
172
173static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
174{
175 u8 val;
176
177 switch (hsotg->hw_params.op_mode) {
178 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
179 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
180 break;
181 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
182 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
183 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
184 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
185 break;
186 default:
187 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
188 break;
189 }
190
191 hsotg->params.otg_cap = val;
192}
193
194static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
195{
196 int val;
197 u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
198
199 val = DWC2_PHY_TYPE_PARAM_FS;
200 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
201 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
202 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
203 val = DWC2_PHY_TYPE_PARAM_UTMI;
204 else
205 val = DWC2_PHY_TYPE_PARAM_ULPI;
206 }
207
208 if (dwc2_is_fs_iot(hsotg))
209 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
210
211 hsotg->params.phy_type = val;
212}
213
214static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
215{
216 int val;
217
218 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
219 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
220
221 if (dwc2_is_fs_iot(hsotg))
222 val = DWC2_SPEED_PARAM_FULL;
223
224 if (dwc2_is_hs_iot(hsotg))
225 val = DWC2_SPEED_PARAM_HIGH;
226
227 hsotg->params.speed = val;
228}
229
230static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
231{
232 int val;
233
234 val = (hsotg->hw_params.utmi_phy_data_width ==
235 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
236
237 hsotg->params.phy_utmi_width = val;
238}
239
240static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
241{
242 struct dwc2_core_params *p = &hsotg->params;
243 int depth_average;
244 int fifo_count;
245 int i;
246
247 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
248
249 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
250 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
251 for (i = 1; i <= fifo_count; i++)
252 p->g_tx_fifo_size[i] = depth_average;
253}
254
255static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
256{
257 int val;
258
259 if (hsotg->hw_params.hibernation)
260 val = 2;
261 else if (hsotg->hw_params.power_optimized)
262 val = 1;
263 else
264 val = 0;
265
266 hsotg->params.power_down = val;
267}
268
269/**
270 * dwc2_set_default_params() - Set all core parameters to their
271 * auto-detected default values.
272 */
273static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
274{
275 struct dwc2_hw_params *hw = &hsotg->hw_params;
276 struct dwc2_core_params *p = &hsotg->params;
277 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
278
279 dwc2_set_param_otg_cap(hsotg);
280 dwc2_set_param_phy_type(hsotg);
281 dwc2_set_param_speed(hsotg);
282 dwc2_set_param_phy_utmi_width(hsotg);
283 dwc2_set_param_power_down(hsotg);
284 p->phy_ulpi_ddr = false;
285 p->phy_ulpi_ext_vbus = false;
286
287 p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
288 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
289 p->i2c_enable = hw->i2c_enable;
290 p->acg_enable = hw->acg_enable;
291 p->ulpi_fs_ls = false;
292 p->ts_dline = false;
293 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
294 p->uframe_sched = true;
295 p->external_id_pin_ctl = false;
296 p->lpm = true;
297 p->lpm_clock_gating = true;
298 p->besl = true;
299 p->hird_threshold_en = true;
300 p->hird_threshold = 4;
301 p->max_packet_count = hw->max_packet_count;
302 p->max_transfer_size = hw->max_transfer_size;
303 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
304
305 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
306 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
307 p->host_dma = dma_capable;
308 p->dma_desc_enable = false;
309 p->dma_desc_fs_enable = false;
310 p->host_support_fs_ls_low_power = false;
311 p->host_ls_low_power_phy_clk = false;
312 p->host_channels = hw->host_channels;
313 p->host_rx_fifo_size = hw->rx_fifo_size;
314 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
315 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
316 }
317
318 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
319 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
320 p->g_dma = dma_capable;
321 p->g_dma_desc = hw->dma_desc_enable;
322
323 /*
324 * The values for g_rx_fifo_size (2048) and
325 * g_np_tx_fifo_size (1024) come from the legacy s3c
326 * gadget driver. These defaults have been hard-coded
327 * for some time so many platforms depend on these
328 * values. Leave them as defaults for now and only
329 * auto-detect if the hardware does not support the
330 * default.
331 */
332 p->g_rx_fifo_size = 2048;
333 p->g_np_tx_fifo_size = 1024;
334 dwc2_set_param_tx_fifo_sizes(hsotg);
335 }
336}
337
338/**
339 * dwc2_get_device_properties() - Read in device properties.
340 *
341 * Read in the device properties and adjust core parameters if needed.
342 */
343static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
344{
345 struct dwc2_core_params *p = &hsotg->params;
346 int num;
347
348 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
349 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
350 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
351 &p->g_rx_fifo_size);
352
353 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
354 &p->g_np_tx_fifo_size);
355
356 num = device_property_read_u32_array(hsotg->dev,
357 "g-tx-fifo-size",
358 NULL, 0);
359
360 if (num > 0) {
361 num = min(num, 15);
362 memset(p->g_tx_fifo_size, 0,
363 sizeof(p->g_tx_fifo_size));
364 device_property_read_u32_array(hsotg->dev,
365 "g-tx-fifo-size",
366 &p->g_tx_fifo_size[1],
367 num);
368 }
369 }
370
371 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
372 p->oc_disable = true;
373}
374
375static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
376{
377 int valid = 1;
378
379 switch (hsotg->params.otg_cap) {
380 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
381 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
382 valid = 0;
383 break;
384 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
385 switch (hsotg->hw_params.op_mode) {
386 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
387 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
388 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
389 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
390 break;
391 default:
392 valid = 0;
393 break;
394 }
395 break;
396 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
397 /* always valid */
398 break;
399 default:
400 valid = 0;
401 break;
402 }
403
404 if (!valid)
405 dwc2_set_param_otg_cap(hsotg);
406}
407
408static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
409{
410 int valid = 0;
411 u32 hs_phy_type;
412 u32 fs_phy_type;
413
414 hs_phy_type = hsotg->hw_params.hs_phy_type;
415 fs_phy_type = hsotg->hw_params.fs_phy_type;
416
417 switch (hsotg->params.phy_type) {
418 case DWC2_PHY_TYPE_PARAM_FS:
419 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
420 valid = 1;
421 break;
422 case DWC2_PHY_TYPE_PARAM_UTMI:
423 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
424 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
425 valid = 1;
426 break;
427 case DWC2_PHY_TYPE_PARAM_ULPI:
428 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
429 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
430 valid = 1;
431 break;
432 default:
433 break;
434 }
435
436 if (!valid)
437 dwc2_set_param_phy_type(hsotg);
438}
439
440static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
441{
442 int valid = 1;
443 int phy_type = hsotg->params.phy_type;
444 int speed = hsotg->params.speed;
445
446 switch (speed) {
447 case DWC2_SPEED_PARAM_HIGH:
448 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
449 (phy_type == DWC2_PHY_TYPE_PARAM_FS))
450 valid = 0;
451 break;
452 case DWC2_SPEED_PARAM_FULL:
453 case DWC2_SPEED_PARAM_LOW:
454 break;
455 default:
456 valid = 0;
457 break;
458 }
459
460 if (!valid)
461 dwc2_set_param_speed(hsotg);
462}
463
464static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
465{
466 int valid = 0;
467 int param = hsotg->params.phy_utmi_width;
468 int width = hsotg->hw_params.utmi_phy_data_width;
469
470 switch (width) {
471 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
472 valid = (param == 8);
473 break;
474 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
475 valid = (param == 16);
476 break;
477 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
478 valid = (param == 8 || param == 16);
479 break;
480 }
481
482 if (!valid)
483 dwc2_set_param_phy_utmi_width(hsotg);
484}
485
486static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
487{
488 int param = hsotg->params.power_down;
489
490 switch (param) {
491 case DWC2_POWER_DOWN_PARAM_NONE:
492 break;
493 case DWC2_POWER_DOWN_PARAM_PARTIAL:
494 if (hsotg->hw_params.power_optimized)
495 break;
496 dev_dbg(hsotg->dev,
497 "Partial power down isn't supported by HW\n");
498 param = DWC2_POWER_DOWN_PARAM_NONE;
499 break;
500 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
501 if (hsotg->hw_params.hibernation)
502 break;
503 dev_dbg(hsotg->dev,
504 "Hibernation isn't supported by HW\n");
505 param = DWC2_POWER_DOWN_PARAM_NONE;
506 break;
507 default:
508 dev_err(hsotg->dev,
509 "%s: Invalid parameter power_down=%d\n",
510 __func__, param);
511 param = DWC2_POWER_DOWN_PARAM_NONE;
512 break;
513 }
514
515 hsotg->params.power_down = param;
516}
517
518static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
519{
520 int fifo_count;
521 int fifo;
522 int min;
523 u32 total = 0;
524 u32 dptxfszn;
525
526 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
527 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
528
529 for (fifo = 1; fifo <= fifo_count; fifo++)
530 total += hsotg->params.g_tx_fifo_size[fifo];
531
532 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
533 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
534 __func__);
535 dwc2_set_param_tx_fifo_sizes(hsotg);
536 }
537
538 for (fifo = 1; fifo <= fifo_count; fifo++) {
539 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
540
541 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
542 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) {
543 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
544 __func__, fifo,
545 hsotg->params.g_tx_fifo_size[fifo]);
546 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
547 }
548 }
549}
550
551#define CHECK_RANGE(_param, _min, _max, _def) do { \
552 if ((hsotg->params._param) < (_min) || \
553 (hsotg->params._param) > (_max)) { \
554 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
555 __func__, #_param, hsotg->params._param); \
556 hsotg->params._param = (_def); \
557 } \
558 } while (0)
559
560#define CHECK_BOOL(_param, _check) do { \
561 if (hsotg->params._param && !(_check)) { \
562 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
563 __func__, #_param, hsotg->params._param); \
564 hsotg->params._param = false; \
565 } \
566 } while (0)
567
568static void dwc2_check_params(struct dwc2_hsotg *hsotg)
569{
570 struct dwc2_hw_params *hw = &hsotg->hw_params;
571 struct dwc2_core_params *p = &hsotg->params;
572 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
573
574 dwc2_check_param_otg_cap(hsotg);
575 dwc2_check_param_phy_type(hsotg);
576 dwc2_check_param_speed(hsotg);
577 dwc2_check_param_phy_utmi_width(hsotg);
578 dwc2_check_param_power_down(hsotg);
579 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
580 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
581 CHECK_BOOL(i2c_enable, hw->i2c_enable);
582 CHECK_BOOL(acg_enable, hw->acg_enable);
583 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
584 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
585 CHECK_BOOL(lpm, hw->lpm_mode);
586 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
587 CHECK_BOOL(besl, hsotg->params.lpm);
588 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
589 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
590 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
591 CHECK_RANGE(max_packet_count,
592 15, hw->max_packet_count,
593 hw->max_packet_count);
594 CHECK_RANGE(max_transfer_size,
595 2047, hw->max_transfer_size,
596 hw->max_transfer_size);
597
598 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
599 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
600 CHECK_BOOL(host_dma, dma_capable);
601 CHECK_BOOL(dma_desc_enable, p->host_dma);
602 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
603 CHECK_BOOL(host_ls_low_power_phy_clk,
604 p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
605 CHECK_RANGE(host_channels,
606 1, hw->host_channels,
607 hw->host_channels);
608 CHECK_RANGE(host_rx_fifo_size,
609 16, hw->rx_fifo_size,
610 hw->rx_fifo_size);
611 CHECK_RANGE(host_nperio_tx_fifo_size,
612 16, hw->host_nperio_tx_fifo_size,
613 hw->host_nperio_tx_fifo_size);
614 CHECK_RANGE(host_perio_tx_fifo_size,
615 16, hw->host_perio_tx_fifo_size,
616 hw->host_perio_tx_fifo_size);
617 }
618
619 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
620 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
621 CHECK_BOOL(g_dma, dma_capable);
622 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
623 CHECK_RANGE(g_rx_fifo_size,
624 16, hw->rx_fifo_size,
625 hw->rx_fifo_size);
626 CHECK_RANGE(g_np_tx_fifo_size,
627 16, hw->dev_nperio_tx_fifo_size,
628 hw->dev_nperio_tx_fifo_size);
629 dwc2_check_param_tx_fifo_sizes(hsotg);
630 }
631}
632
633/*
634 * Gets host hardware parameters. Forces host mode if not currently in
635 * host mode. Should be called immediately after a core soft reset in
636 * order to get the reset values.
637 */
638static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
639{
640 struct dwc2_hw_params *hw = &hsotg->hw_params;
641 u32 gnptxfsiz;
642 u32 hptxfsiz;
643
644 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
645 return;
646
647 dwc2_force_mode(hsotg, true);
648
649 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
650 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
651
652 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
653 FIFOSIZE_DEPTH_SHIFT;
654 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
655 FIFOSIZE_DEPTH_SHIFT;
656}
657
658/*
659 * Gets device hardware parameters. Forces device mode if not
660 * currently in device mode. Should be called immediately after a core
661 * soft reset in order to get the reset values.
662 */
663static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
664{
665 struct dwc2_hw_params *hw = &hsotg->hw_params;
666 u32 gnptxfsiz;
667 int fifo, fifo_count;
668
669 if (hsotg->dr_mode == USB_DR_MODE_HOST)
670 return;
671
672 dwc2_force_mode(hsotg, false);
673
674 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
675
676 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
677
678 for (fifo = 1; fifo <= fifo_count; fifo++) {
679 hw->g_tx_fifo_size[fifo] =
680 (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) &
681 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
682 }
683
684 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
685 FIFOSIZE_DEPTH_SHIFT;
686}
687
688/**
689 * During device initialization, read various hardware configuration
690 * registers and interpret the contents.
691 */
692int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
693{
694 struct dwc2_hw_params *hw = &hsotg->hw_params;
695 unsigned int width;
696 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
697 u32 grxfsiz;
698
699 /*
700 * Attempt to ensure this device is really a DWC_otg Controller.
701 * Read and verify the GSNPSID register contents. The value should be
702 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
703 */
704
705 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
706 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
707 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
708 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
709 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
710 hw->snpsid);
711 return -ENODEV;
712 }
713
714 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
715 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
716 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
717
718 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
719 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
720 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
721 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
722 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
723
724 /* hwcfg1 */
725 hw->dev_ep_dirs = hwcfg1;
726
727 /* hwcfg2 */
728 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
729 GHWCFG2_OP_MODE_SHIFT;
730 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
731 GHWCFG2_ARCHITECTURE_SHIFT;
732 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
733 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
734 GHWCFG2_NUM_HOST_CHAN_SHIFT);
735 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
736 GHWCFG2_HS_PHY_TYPE_SHIFT;
737 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
738 GHWCFG2_FS_PHY_TYPE_SHIFT;
739 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
740 GHWCFG2_NUM_DEV_EP_SHIFT;
741 hw->nperio_tx_q_depth =
742 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
743 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
744 hw->host_perio_tx_q_depth =
745 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
746 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
747 hw->dev_token_q_depth =
748 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
749 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
750
751 /* hwcfg3 */
752 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
753 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
754 hw->max_transfer_size = (1 << (width + 11)) - 1;
755 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
756 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
757 hw->max_packet_count = (1 << (width + 4)) - 1;
758 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
759 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
760 GHWCFG3_DFIFO_DEPTH_SHIFT;
761 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
762
763 /* hwcfg4 */
764 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
765 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
766 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
767 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
768 GHWCFG4_NUM_IN_EPS_SHIFT;
769 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
770 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
771 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
772 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
773 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
774 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
775
776 /* fifo sizes */
777 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
778 GRXFSIZ_DEPTH_SHIFT;
779 /*
780 * Host specific hardware parameters. Reading these parameters
781 * requires the controller to be in host mode. The mode will
782 * be forced, if necessary, to read these values.
783 */
784 dwc2_get_host_hwparams(hsotg);
785 dwc2_get_dev_hwparams(hsotg);
786
787 return 0;
788}
789
790int dwc2_init_params(struct dwc2_hsotg *hsotg)
791{
792 const struct of_device_id *match;
793 void (*set_params)(void *data);
794
795 dwc2_set_default_params(hsotg);
796 dwc2_get_device_properties(hsotg);
797
798 match = of_match_device(dwc2_of_match_table, hsotg->dev);
799 if (match && match->data) {
800 set_params = match->data;
801 set_params(hsotg);
802 }
803
804 dwc2_check_params(hsotg);
805
806 return 0;
807}