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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4/* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
5#define __DISABLE_TRACE_MMIO__
6
7#include <linux/clk.h>
8#include <linux/console.h>
9#include <linux/io.h>
10#include <linux/iopoll.h>
11#include <linux/irq.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/pm_opp.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/pm_wakeirq.h>
19#include <linux/qcom-geni-se.h>
20#include <linux/serial.h>
21#include <linux/serial_core.h>
22#include <linux/slab.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <dt-bindings/interconnect/qcom,icc.h>
26
27/* UART specific GENI registers */
28#define SE_UART_LOOPBACK_CFG 0x22c
29#define SE_UART_IO_MACRO_CTRL 0x240
30#define SE_UART_TX_TRANS_CFG 0x25c
31#define SE_UART_TX_WORD_LEN 0x268
32#define SE_UART_TX_STOP_BIT_LEN 0x26c
33#define SE_UART_TX_TRANS_LEN 0x270
34#define SE_UART_RX_TRANS_CFG 0x280
35#define SE_UART_RX_WORD_LEN 0x28c
36#define SE_UART_RX_STALE_CNT 0x294
37#define SE_UART_TX_PARITY_CFG 0x2a4
38#define SE_UART_RX_PARITY_CFG 0x2a8
39#define SE_UART_MANUAL_RFR 0x2ac
40
41/* SE_UART_TRANS_CFG */
42#define UART_TX_PAR_EN BIT(0)
43#define UART_CTS_MASK BIT(1)
44
45/* SE_UART_TX_WORD_LEN */
46#define TX_WORD_LEN_MSK GENMASK(9, 0)
47
48/* SE_UART_TX_STOP_BIT_LEN */
49#define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
50#define TX_STOP_BIT_LEN_1 0
51#define TX_STOP_BIT_LEN_1_5 1
52#define TX_STOP_BIT_LEN_2 2
53
54/* SE_UART_TX_TRANS_LEN */
55#define TX_TRANS_LEN_MSK GENMASK(23, 0)
56
57/* SE_UART_RX_TRANS_CFG */
58#define UART_RX_INS_STATUS_BIT BIT(2)
59#define UART_RX_PAR_EN BIT(3)
60
61/* SE_UART_RX_WORD_LEN */
62#define RX_WORD_LEN_MASK GENMASK(9, 0)
63
64/* SE_UART_RX_STALE_CNT */
65#define RX_STALE_CNT GENMASK(23, 0)
66
67/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
68#define PAR_CALC_EN BIT(0)
69#define PAR_MODE_MSK GENMASK(2, 1)
70#define PAR_MODE_SHFT 1
71#define PAR_EVEN 0x00
72#define PAR_ODD 0x01
73#define PAR_SPACE 0x10
74#define PAR_MARK 0x11
75
76/* SE_UART_MANUAL_RFR register fields */
77#define UART_MANUAL_RFR_EN BIT(31)
78#define UART_RFR_NOT_READY BIT(1)
79#define UART_RFR_READY BIT(0)
80
81/* UART M_CMD OP codes */
82#define UART_START_TX 0x1
83#define UART_START_BREAK 0x4
84#define UART_STOP_BREAK 0x5
85/* UART S_CMD OP codes */
86#define UART_START_READ 0x1
87#define UART_PARAM 0x1
88
89#define UART_OVERSAMPLING 32
90#define STALE_TIMEOUT 16
91#define DEFAULT_BITS_PER_CHAR 10
92#define GENI_UART_CONS_PORTS 1
93#define GENI_UART_PORTS 3
94#define DEF_FIFO_DEPTH_WORDS 16
95#define DEF_TX_WM 2
96#define DEF_FIFO_WIDTH_BITS 32
97#define UART_RX_WM 2
98
99/* SE_UART_LOOPBACK_CFG */
100#define RX_TX_SORTED BIT(0)
101#define CTS_RTS_SORTED BIT(1)
102#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
103
104/* UART pin swap value */
105#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
106#define IO_MACRO_IO0_SEL 0x3
107#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
108#define IO_MACRO_IO2_IO3_SWAP 0x4640
109
110/* We always configure 4 bytes per FIFO word */
111#define BYTES_PER_FIFO_WORD 4
112
113struct qcom_geni_private_data {
114 /* NOTE: earlycon port will have NULL here */
115 struct uart_driver *drv;
116
117 u32 poll_cached_bytes;
118 unsigned int poll_cached_bytes_cnt;
119
120 u32 write_cached_bytes;
121 unsigned int write_cached_bytes_cnt;
122};
123
124struct qcom_geni_serial_port {
125 struct uart_port uport;
126 struct geni_se se;
127 const char *name;
128 u32 tx_fifo_depth;
129 u32 tx_fifo_width;
130 u32 rx_fifo_depth;
131 bool setup;
132 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
133 unsigned int baud;
134 void *rx_fifo;
135 u32 loopback;
136 bool brk;
137
138 unsigned int tx_remaining;
139 int wakeup_irq;
140 bool rx_tx_swap;
141 bool cts_rts_swap;
142
143 struct qcom_geni_private_data private_data;
144};
145
146static const struct uart_ops qcom_geni_console_pops;
147static const struct uart_ops qcom_geni_uart_pops;
148static struct uart_driver qcom_geni_console_driver;
149static struct uart_driver qcom_geni_uart_driver;
150static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
151static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
152static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
153static void qcom_geni_serial_stop_rx(struct uart_port *uport);
154static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
155
156#define to_dev_port(ptr, member) \
157 container_of(ptr, struct qcom_geni_serial_port, member)
158
159static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
160 [0] = {
161 .uport = {
162 .iotype = UPIO_MEM,
163 .ops = &qcom_geni_uart_pops,
164 .flags = UPF_BOOT_AUTOCONF,
165 .line = 0,
166 },
167 },
168 [1] = {
169 .uport = {
170 .iotype = UPIO_MEM,
171 .ops = &qcom_geni_uart_pops,
172 .flags = UPF_BOOT_AUTOCONF,
173 .line = 1,
174 },
175 },
176 [2] = {
177 .uport = {
178 .iotype = UPIO_MEM,
179 .ops = &qcom_geni_uart_pops,
180 .flags = UPF_BOOT_AUTOCONF,
181 .line = 2,
182 },
183 },
184};
185
186static struct qcom_geni_serial_port qcom_geni_console_port = {
187 .uport = {
188 .iotype = UPIO_MEM,
189 .ops = &qcom_geni_console_pops,
190 .flags = UPF_BOOT_AUTOCONF,
191 .line = 0,
192 },
193};
194
195static int qcom_geni_serial_request_port(struct uart_port *uport)
196{
197 struct platform_device *pdev = to_platform_device(uport->dev);
198 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
199
200 uport->membase = devm_platform_ioremap_resource(pdev, 0);
201 if (IS_ERR(uport->membase))
202 return PTR_ERR(uport->membase);
203 port->se.base = uport->membase;
204 return 0;
205}
206
207static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
208{
209 if (cfg_flags & UART_CONFIG_TYPE) {
210 uport->type = PORT_MSM;
211 qcom_geni_serial_request_port(uport);
212 }
213}
214
215static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
216{
217 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
218 u32 geni_ios;
219
220 if (uart_console(uport)) {
221 mctrl |= TIOCM_CTS;
222 } else {
223 geni_ios = readl(uport->membase + SE_GENI_IOS);
224 if (!(geni_ios & IO2_DATA_IN))
225 mctrl |= TIOCM_CTS;
226 }
227
228 return mctrl;
229}
230
231static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
232 unsigned int mctrl)
233{
234 u32 uart_manual_rfr = 0;
235 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
236
237 if (uart_console(uport))
238 return;
239
240 if (mctrl & TIOCM_LOOP)
241 port->loopback = RX_TX_CTS_RTS_SORTED;
242
243 if (!(mctrl & TIOCM_RTS) && !uport->suspended)
244 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
245 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
246}
247
248static const char *qcom_geni_serial_get_type(struct uart_port *uport)
249{
250 return "MSM";
251}
252
253static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
254{
255 struct qcom_geni_serial_port *port;
256 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
257
258 if (line < 0 || line >= nr_ports)
259 return ERR_PTR(-ENXIO);
260
261 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
262 return port;
263}
264
265static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
266 int offset, int field, bool set)
267{
268 u32 reg;
269 struct qcom_geni_serial_port *port;
270 unsigned int baud;
271 unsigned int fifo_bits;
272 unsigned long timeout_us = 20000;
273 struct qcom_geni_private_data *private_data = uport->private_data;
274
275 if (private_data->drv) {
276 port = to_dev_port(uport, uport);
277 baud = port->baud;
278 if (!baud)
279 baud = 115200;
280 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
281 /*
282 * Total polling iterations based on FIFO worth of bytes to be
283 * sent at current baud. Add a little fluff to the wait.
284 */
285 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
286 }
287
288 /*
289 * Use custom implementation instead of readl_poll_atomic since ktimer
290 * is not ready at the time of early console.
291 */
292 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
293 while (timeout_us) {
294 reg = readl(uport->membase + offset);
295 if ((bool)(reg & field) == set)
296 return true;
297 udelay(10);
298 timeout_us -= 10;
299 }
300 return false;
301}
302
303static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
304{
305 u32 m_cmd;
306
307 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
308 m_cmd = UART_START_TX << M_OPCODE_SHFT;
309 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
310}
311
312static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
313{
314 int done;
315 u32 irq_clear = M_CMD_DONE_EN;
316
317 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
318 M_CMD_DONE_EN, true);
319 if (!done) {
320 writel(M_GENI_CMD_ABORT, uport->membase +
321 SE_GENI_M_CMD_CTRL_REG);
322 irq_clear |= M_CMD_ABORT_EN;
323 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
324 M_CMD_ABORT_EN, true);
325 }
326 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
327}
328
329static void qcom_geni_serial_abort_rx(struct uart_port *uport)
330{
331 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
332
333 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
334 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
335 S_GENI_CMD_ABORT, false);
336 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
337 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
338}
339
340#ifdef CONFIG_CONSOLE_POLL
341
342static int qcom_geni_serial_get_char(struct uart_port *uport)
343{
344 struct qcom_geni_private_data *private_data = uport->private_data;
345 u32 status;
346 u32 word_cnt;
347 int ret;
348
349 if (!private_data->poll_cached_bytes_cnt) {
350 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
351 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
352
353 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
354 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
355
356 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
357 word_cnt = status & RX_FIFO_WC_MSK;
358 if (!word_cnt)
359 return NO_POLL_CHAR;
360
361 if (word_cnt == 1 && (status & RX_LAST))
362 /*
363 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
364 * treated as if it was BYTES_PER_FIFO_WORD.
365 */
366 private_data->poll_cached_bytes_cnt =
367 (status & RX_LAST_BYTE_VALID_MSK) >>
368 RX_LAST_BYTE_VALID_SHFT;
369
370 if (private_data->poll_cached_bytes_cnt == 0)
371 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
372
373 private_data->poll_cached_bytes =
374 readl(uport->membase + SE_GENI_RX_FIFOn);
375 }
376
377 private_data->poll_cached_bytes_cnt--;
378 ret = private_data->poll_cached_bytes & 0xff;
379 private_data->poll_cached_bytes >>= 8;
380
381 return ret;
382}
383
384static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
385 unsigned char c)
386{
387 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
388 qcom_geni_serial_setup_tx(uport, 1);
389 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
390 M_TX_FIFO_WATERMARK_EN, true));
391 writel(c, uport->membase + SE_GENI_TX_FIFOn);
392 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
393 qcom_geni_serial_poll_tx_done(uport);
394}
395#endif
396
397#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
398static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch)
399{
400 struct qcom_geni_private_data *private_data = uport->private_data;
401
402 private_data->write_cached_bytes =
403 (private_data->write_cached_bytes >> 8) | (ch << 24);
404 private_data->write_cached_bytes_cnt++;
405
406 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
407 writel(private_data->write_cached_bytes,
408 uport->membase + SE_GENI_TX_FIFOn);
409 private_data->write_cached_bytes_cnt = 0;
410 }
411}
412
413static void
414__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
415 unsigned int count)
416{
417 struct qcom_geni_private_data *private_data = uport->private_data;
418
419 int i;
420 u32 bytes_to_send = count;
421
422 for (i = 0; i < count; i++) {
423 /*
424 * uart_console_write() adds a carriage return for each newline.
425 * Account for additional bytes to be written.
426 */
427 if (s[i] == '\n')
428 bytes_to_send++;
429 }
430
431 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
432 qcom_geni_serial_setup_tx(uport, bytes_to_send);
433 for (i = 0; i < count; ) {
434 size_t chars_to_write = 0;
435 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
436
437 /*
438 * If the WM bit never set, then the Tx state machine is not
439 * in a valid state, so break, cancel/abort any existing
440 * command. Unfortunately the current data being written is
441 * lost.
442 */
443 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
444 M_TX_FIFO_WATERMARK_EN, true))
445 break;
446 chars_to_write = min_t(size_t, count - i, avail / 2);
447 uart_console_write(uport, s + i, chars_to_write,
448 qcom_geni_serial_wr_char);
449 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
450 SE_GENI_M_IRQ_CLEAR);
451 i += chars_to_write;
452 }
453
454 if (private_data->write_cached_bytes_cnt) {
455 private_data->write_cached_bytes >>= BITS_PER_BYTE *
456 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
457 writel(private_data->write_cached_bytes,
458 uport->membase + SE_GENI_TX_FIFOn);
459 private_data->write_cached_bytes_cnt = 0;
460 }
461
462 qcom_geni_serial_poll_tx_done(uport);
463}
464
465static void qcom_geni_serial_console_write(struct console *co, const char *s,
466 unsigned int count)
467{
468 struct uart_port *uport;
469 struct qcom_geni_serial_port *port;
470 bool locked = true;
471 unsigned long flags;
472 u32 geni_status;
473 u32 irq_en;
474
475 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
476
477 port = get_port_from_line(co->index, true);
478 if (IS_ERR(port))
479 return;
480
481 uport = &port->uport;
482 if (oops_in_progress)
483 locked = spin_trylock_irqsave(&uport->lock, flags);
484 else
485 spin_lock_irqsave(&uport->lock, flags);
486
487 geni_status = readl(uport->membase + SE_GENI_STATUS);
488
489 /* Cancel the current write to log the fault */
490 if (!locked) {
491 geni_se_cancel_m_cmd(&port->se);
492 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
493 M_CMD_CANCEL_EN, true)) {
494 geni_se_abort_m_cmd(&port->se);
495 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
496 M_CMD_ABORT_EN, true);
497 writel(M_CMD_ABORT_EN, uport->membase +
498 SE_GENI_M_IRQ_CLEAR);
499 }
500 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
501 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
502 /*
503 * It seems we can't interrupt existing transfers if all data
504 * has been sent, in which case we need to look for done first.
505 */
506 qcom_geni_serial_poll_tx_done(uport);
507
508 if (!uart_circ_empty(&uport->state->xmit)) {
509 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
510 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
511 uport->membase + SE_GENI_M_IRQ_EN);
512 }
513 }
514
515 __qcom_geni_serial_console_write(uport, s, count);
516
517 if (port->tx_remaining)
518 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
519
520 if (locked)
521 spin_unlock_irqrestore(&uport->lock, flags);
522}
523
524static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
525{
526 u32 i;
527 unsigned char buf[sizeof(u32)];
528 struct tty_port *tport;
529 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
530
531 tport = &uport->state->port;
532 for (i = 0; i < bytes; ) {
533 int c;
534 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
535
536 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
537 i += chunk;
538 if (drop)
539 continue;
540
541 for (c = 0; c < chunk; c++) {
542 int sysrq;
543
544 uport->icount.rx++;
545 if (port->brk && buf[c] == 0) {
546 port->brk = false;
547 if (uart_handle_break(uport))
548 continue;
549 }
550
551 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
552
553 if (!sysrq)
554 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
555 }
556 }
557 if (!drop)
558 tty_flip_buffer_push(tport);
559 return 0;
560}
561#else
562static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
563{
564 return -EPERM;
565}
566
567#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
568
569static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
570{
571 struct tty_port *tport;
572 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
573 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
574 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
575 int ret;
576
577 tport = &uport->state->port;
578 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
579 if (drop)
580 return 0;
581
582 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
583 if (ret != bytes) {
584 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
585 __func__, ret, bytes);
586 WARN_ON_ONCE(1);
587 }
588 uport->icount.rx += ret;
589 tty_flip_buffer_push(tport);
590 return ret;
591}
592
593static void qcom_geni_serial_start_tx(struct uart_port *uport)
594{
595 u32 irq_en;
596 u32 status;
597
598 status = readl(uport->membase + SE_GENI_STATUS);
599 if (status & M_GENI_CMD_ACTIVE)
600 return;
601
602 if (!qcom_geni_serial_tx_empty(uport))
603 return;
604
605 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
606 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
607
608 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
609 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
610}
611
612static void qcom_geni_serial_stop_tx(struct uart_port *uport)
613{
614 u32 irq_en;
615 u32 status;
616 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
617
618 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
619 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
620 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
621 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
622 status = readl(uport->membase + SE_GENI_STATUS);
623 /* Possible stop tx is called multiple times. */
624 if (!(status & M_GENI_CMD_ACTIVE))
625 return;
626
627 geni_se_cancel_m_cmd(&port->se);
628 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
629 M_CMD_CANCEL_EN, true)) {
630 geni_se_abort_m_cmd(&port->se);
631 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
632 M_CMD_ABORT_EN, true);
633 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
634 }
635 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
636}
637
638static void qcom_geni_serial_start_rx(struct uart_port *uport)
639{
640 u32 irq_en;
641 u32 status;
642 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
643
644 status = readl(uport->membase + SE_GENI_STATUS);
645 if (status & S_GENI_CMD_ACTIVE)
646 qcom_geni_serial_stop_rx(uport);
647
648 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
649
650 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
651 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
652 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
653
654 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
655 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
656 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
657}
658
659static void qcom_geni_serial_stop_rx(struct uart_port *uport)
660{
661 u32 irq_en;
662 u32 status;
663 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
664 u32 s_irq_status;
665
666 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
667 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
668 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
669
670 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
671 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
672 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
673
674 status = readl(uport->membase + SE_GENI_STATUS);
675 /* Possible stop rx is called multiple times. */
676 if (!(status & S_GENI_CMD_ACTIVE))
677 return;
678
679 geni_se_cancel_s_cmd(&port->se);
680 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
681 S_CMD_CANCEL_EN, true);
682 /*
683 * If timeout occurs secondary engine remains active
684 * and Abort sequence is executed.
685 */
686 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
687 /* Flush the Rx buffer */
688 if (s_irq_status & S_RX_FIFO_LAST_EN)
689 qcom_geni_serial_handle_rx(uport, true);
690 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
691
692 status = readl(uport->membase + SE_GENI_STATUS);
693 if (status & S_GENI_CMD_ACTIVE)
694 qcom_geni_serial_abort_rx(uport);
695}
696
697static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
698{
699 u32 status;
700 u32 word_cnt;
701 u32 last_word_byte_cnt;
702 u32 last_word_partial;
703 u32 total_bytes;
704 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
705
706 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
707 word_cnt = status & RX_FIFO_WC_MSK;
708 last_word_partial = status & RX_LAST;
709 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
710 RX_LAST_BYTE_VALID_SHFT;
711
712 if (!word_cnt)
713 return;
714 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
715 if (last_word_partial && last_word_byte_cnt)
716 total_bytes += last_word_byte_cnt;
717 else
718 total_bytes += BYTES_PER_FIFO_WORD;
719 port->handle_rx(uport, total_bytes, drop);
720}
721
722static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
723 bool active)
724{
725 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
726 struct circ_buf *xmit = &uport->state->xmit;
727 size_t avail;
728 size_t remaining;
729 size_t pending;
730 int i;
731 u32 status;
732 u32 irq_en;
733 unsigned int chunk;
734 int tail;
735
736 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
737
738 /* Complete the current tx command before taking newly added data */
739 if (active)
740 pending = port->tx_remaining;
741 else
742 pending = uart_circ_chars_pending(xmit);
743
744 /* All data has been transmitted and acknowledged as received */
745 if (!pending && !status && done) {
746 qcom_geni_serial_stop_tx(uport);
747 goto out_write_wakeup;
748 }
749
750 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
751 avail *= BYTES_PER_FIFO_WORD;
752
753 tail = xmit->tail;
754 chunk = min(avail, pending);
755 if (!chunk)
756 goto out_write_wakeup;
757
758 if (!port->tx_remaining) {
759 qcom_geni_serial_setup_tx(uport, pending);
760 port->tx_remaining = pending;
761
762 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
763 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
764 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
765 uport->membase + SE_GENI_M_IRQ_EN);
766 }
767
768 remaining = chunk;
769 for (i = 0; i < chunk; ) {
770 unsigned int tx_bytes;
771 u8 buf[sizeof(u32)];
772 int c;
773
774 memset(buf, 0, sizeof(buf));
775 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
776
777 for (c = 0; c < tx_bytes ; c++) {
778 buf[c] = xmit->buf[tail++];
779 tail &= UART_XMIT_SIZE - 1;
780 }
781
782 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
783
784 i += tx_bytes;
785 uport->icount.tx += tx_bytes;
786 remaining -= tx_bytes;
787 port->tx_remaining -= tx_bytes;
788 }
789
790 xmit->tail = tail;
791
792 /*
793 * The tx fifo watermark is level triggered and latched. Though we had
794 * cleared it in qcom_geni_serial_isr it will have already reasserted
795 * so we must clear it again here after our writes.
796 */
797 writel(M_TX_FIFO_WATERMARK_EN,
798 uport->membase + SE_GENI_M_IRQ_CLEAR);
799
800out_write_wakeup:
801 if (!port->tx_remaining) {
802 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
803 if (irq_en & M_TX_FIFO_WATERMARK_EN)
804 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
805 uport->membase + SE_GENI_M_IRQ_EN);
806 }
807
808 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
809 uart_write_wakeup(uport);
810}
811
812static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
813{
814 u32 m_irq_en;
815 u32 m_irq_status;
816 u32 s_irq_status;
817 u32 geni_status;
818 struct uart_port *uport = dev;
819 bool drop_rx = false;
820 struct tty_port *tport = &uport->state->port;
821 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
822
823 if (uport->suspended)
824 return IRQ_NONE;
825
826 spin_lock(&uport->lock);
827
828 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
829 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
830 geni_status = readl(uport->membase + SE_GENI_STATUS);
831 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
832 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
833 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
834
835 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
836 goto out_unlock;
837
838 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
839 uport->icount.overrun++;
840 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
841 }
842
843 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
844 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
845 geni_status & M_GENI_CMD_ACTIVE);
846
847 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
848 if (s_irq_status & S_GP_IRQ_0_EN)
849 uport->icount.parity++;
850 drop_rx = true;
851 } else if (s_irq_status & S_GP_IRQ_2_EN ||
852 s_irq_status & S_GP_IRQ_3_EN) {
853 uport->icount.brk++;
854 port->brk = true;
855 }
856
857 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
858 s_irq_status & S_RX_FIFO_LAST_EN)
859 qcom_geni_serial_handle_rx(uport, drop_rx);
860
861out_unlock:
862 uart_unlock_and_check_sysrq(uport);
863
864 return IRQ_HANDLED;
865}
866
867static int setup_fifos(struct qcom_geni_serial_port *port)
868{
869 struct uart_port *uport;
870 u32 old_rx_fifo_depth = port->rx_fifo_depth;
871
872 uport = &port->uport;
873 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
874 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
875 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
876 uport->fifosize =
877 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
878
879 if (port->rx_fifo && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) {
880 port->rx_fifo = devm_krealloc(uport->dev, port->rx_fifo,
881 port->rx_fifo_depth * sizeof(u32),
882 GFP_KERNEL);
883 if (!port->rx_fifo)
884 return -ENOMEM;
885 }
886
887 return 0;
888}
889
890
891static void qcom_geni_serial_shutdown(struct uart_port *uport)
892{
893 disable_irq(uport->irq);
894}
895
896static int qcom_geni_serial_port_setup(struct uart_port *uport)
897{
898 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
899 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
900 u32 proto;
901 u32 pin_swap;
902 int ret;
903
904 proto = geni_se_read_proto(&port->se);
905 if (proto != GENI_SE_UART) {
906 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
907 return -ENXIO;
908 }
909
910 qcom_geni_serial_stop_rx(uport);
911
912 ret = setup_fifos(port);
913 if (ret)
914 return ret;
915
916 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
917
918 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
919 if (port->rx_tx_swap) {
920 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
921 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
922 }
923 if (port->cts_rts_swap) {
924 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
925 pin_swap |= IO_MACRO_IO0_SEL;
926 }
927 /* Configure this register if RX-TX, CTS-RTS pins are swapped */
928 if (port->rx_tx_swap || port->cts_rts_swap)
929 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
930
931 /*
932 * Make an unconditional cancel on the main sequencer to reset
933 * it else we could end up in data loss scenarios.
934 */
935 if (uart_console(uport))
936 qcom_geni_serial_poll_tx_done(uport);
937 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
938 false, true, true);
939 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
940 geni_se_select_mode(&port->se, GENI_SE_FIFO);
941 qcom_geni_serial_start_rx(uport);
942 port->setup = true;
943
944 return 0;
945}
946
947static int qcom_geni_serial_startup(struct uart_port *uport)
948{
949 int ret;
950 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
951
952 if (!port->setup) {
953 ret = qcom_geni_serial_port_setup(uport);
954 if (ret)
955 return ret;
956 }
957 enable_irq(uport->irq);
958
959 return 0;
960}
961
962static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk,
963 unsigned int *clk_div, unsigned int percent_tol)
964{
965 unsigned long freq;
966 unsigned long div, maxdiv;
967 u64 mult;
968 unsigned long offset, abs_tol, achieved;
969
970 abs_tol = div_u64((u64)desired_clk * percent_tol, 100);
971 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
972 div = 1;
973 while (div <= maxdiv) {
974 mult = (u64)div * desired_clk;
975 if (mult != (unsigned long)mult)
976 break;
977
978 offset = div * abs_tol;
979 freq = clk_round_rate(clk, mult - offset);
980
981 /* Can only get lower if we're done */
982 if (freq < mult - offset)
983 break;
984
985 /*
986 * Re-calculate div in case rounding skipped rates but we
987 * ended up at a good one, then check for a match.
988 */
989 div = DIV_ROUND_CLOSEST(freq, desired_clk);
990 achieved = DIV_ROUND_CLOSEST(freq, div);
991 if (achieved <= desired_clk + abs_tol &&
992 achieved >= desired_clk - abs_tol) {
993 *clk_div = div;
994 return freq;
995 }
996
997 div = DIV_ROUND_UP(freq, desired_clk);
998 }
999
1000 return 0;
1001}
1002
1003static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
1004 unsigned int sampling_rate, unsigned int *clk_div)
1005{
1006 unsigned long ser_clk;
1007 unsigned long desired_clk;
1008
1009 desired_clk = baud * sampling_rate;
1010 if (!desired_clk)
1011 return 0;
1012
1013 /*
1014 * try to find a clock rate within 2% tolerance, then within 5%
1015 */
1016 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2);
1017 if (!ser_clk)
1018 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5);
1019
1020 return ser_clk;
1021}
1022
1023static void qcom_geni_serial_set_termios(struct uart_port *uport,
1024 struct ktermios *termios,
1025 const struct ktermios *old)
1026{
1027 unsigned int baud;
1028 u32 bits_per_char;
1029 u32 tx_trans_cfg;
1030 u32 tx_parity_cfg;
1031 u32 rx_trans_cfg;
1032 u32 rx_parity_cfg;
1033 u32 stop_bit_len;
1034 unsigned int clk_div;
1035 u32 ser_clk_cfg;
1036 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1037 unsigned long clk_rate;
1038 u32 ver, sampling_rate;
1039 unsigned int avg_bw_core;
1040
1041 qcom_geni_serial_stop_rx(uport);
1042 /* baud rate */
1043 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1044 port->baud = baud;
1045
1046 sampling_rate = UART_OVERSAMPLING;
1047 /* Sampling rate is halved for IP versions >= 2.5 */
1048 ver = geni_se_get_qup_hw_version(&port->se);
1049 if (ver >= QUP_SE_VERSION_2_5)
1050 sampling_rate /= 2;
1051
1052 clk_rate = get_clk_div_rate(port->se.clk, baud,
1053 sampling_rate, &clk_div);
1054 if (!clk_rate) {
1055 dev_err(port->se.dev,
1056 "Couldn't find suitable clock rate for %u\n",
1057 baud * sampling_rate);
1058 goto out_restart_rx;
1059 }
1060
1061 dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n",
1062 baud * sampling_rate, clk_rate, clk_div);
1063
1064 uport->uartclk = clk_rate;
1065 dev_pm_opp_set_rate(uport->dev, clk_rate);
1066 ser_clk_cfg = SER_CLK_EN;
1067 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1068
1069 /*
1070 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1071 * only.
1072 */
1073 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1074 : GENI_DEFAULT_BW;
1075 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1076 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1077 geni_icc_set_bw(&port->se);
1078
1079 /* parity */
1080 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1081 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1082 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1083 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1084 if (termios->c_cflag & PARENB) {
1085 tx_trans_cfg |= UART_TX_PAR_EN;
1086 rx_trans_cfg |= UART_RX_PAR_EN;
1087 tx_parity_cfg |= PAR_CALC_EN;
1088 rx_parity_cfg |= PAR_CALC_EN;
1089 if (termios->c_cflag & PARODD) {
1090 tx_parity_cfg |= PAR_ODD;
1091 rx_parity_cfg |= PAR_ODD;
1092 } else if (termios->c_cflag & CMSPAR) {
1093 tx_parity_cfg |= PAR_SPACE;
1094 rx_parity_cfg |= PAR_SPACE;
1095 } else {
1096 tx_parity_cfg |= PAR_EVEN;
1097 rx_parity_cfg |= PAR_EVEN;
1098 }
1099 } else {
1100 tx_trans_cfg &= ~UART_TX_PAR_EN;
1101 rx_trans_cfg &= ~UART_RX_PAR_EN;
1102 tx_parity_cfg &= ~PAR_CALC_EN;
1103 rx_parity_cfg &= ~PAR_CALC_EN;
1104 }
1105
1106 /* bits per char */
1107 bits_per_char = tty_get_char_size(termios->c_cflag);
1108
1109 /* stop bits */
1110 if (termios->c_cflag & CSTOPB)
1111 stop_bit_len = TX_STOP_BIT_LEN_2;
1112 else
1113 stop_bit_len = TX_STOP_BIT_LEN_1;
1114
1115 /* flow control, clear the CTS_MASK bit if using flow control. */
1116 if (termios->c_cflag & CRTSCTS)
1117 tx_trans_cfg &= ~UART_CTS_MASK;
1118 else
1119 tx_trans_cfg |= UART_CTS_MASK;
1120
1121 if (baud)
1122 uart_update_timeout(uport, termios->c_cflag, baud);
1123
1124 if (!uart_console(uport))
1125 writel(port->loopback,
1126 uport->membase + SE_UART_LOOPBACK_CFG);
1127 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1128 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1129 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1130 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1131 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1132 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1133 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1134 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1135 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1136out_restart_rx:
1137 qcom_geni_serial_start_rx(uport);
1138}
1139
1140static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1141{
1142 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1143}
1144
1145#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1146static int qcom_geni_console_setup(struct console *co, char *options)
1147{
1148 struct uart_port *uport;
1149 struct qcom_geni_serial_port *port;
1150 int baud = 115200;
1151 int bits = 8;
1152 int parity = 'n';
1153 int flow = 'n';
1154 int ret;
1155
1156 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1157 return -ENXIO;
1158
1159 port = get_port_from_line(co->index, true);
1160 if (IS_ERR(port)) {
1161 pr_err("Invalid line %d\n", co->index);
1162 return PTR_ERR(port);
1163 }
1164
1165 uport = &port->uport;
1166
1167 if (unlikely(!uport->membase))
1168 return -ENXIO;
1169
1170 if (!port->setup) {
1171 ret = qcom_geni_serial_port_setup(uport);
1172 if (ret)
1173 return ret;
1174 }
1175
1176 if (options)
1177 uart_parse_options(options, &baud, &parity, &bits, &flow);
1178
1179 return uart_set_options(uport, co, baud, parity, bits, flow);
1180}
1181
1182static void qcom_geni_serial_earlycon_write(struct console *con,
1183 const char *s, unsigned int n)
1184{
1185 struct earlycon_device *dev = con->data;
1186
1187 __qcom_geni_serial_console_write(&dev->port, s, n);
1188}
1189
1190#ifdef CONFIG_CONSOLE_POLL
1191static int qcom_geni_serial_earlycon_read(struct console *con,
1192 char *s, unsigned int n)
1193{
1194 struct earlycon_device *dev = con->data;
1195 struct uart_port *uport = &dev->port;
1196 int num_read = 0;
1197 int ch;
1198
1199 while (num_read < n) {
1200 ch = qcom_geni_serial_get_char(uport);
1201 if (ch == NO_POLL_CHAR)
1202 break;
1203 s[num_read++] = ch;
1204 }
1205
1206 return num_read;
1207}
1208
1209static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1210 struct console *con)
1211{
1212 geni_se_setup_s_cmd(se, UART_START_READ, 0);
1213 con->read = qcom_geni_serial_earlycon_read;
1214}
1215#else
1216static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1217 struct console *con) { }
1218#endif
1219
1220static struct qcom_geni_private_data earlycon_private_data;
1221
1222static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1223 const char *opt)
1224{
1225 struct uart_port *uport = &dev->port;
1226 u32 tx_trans_cfg;
1227 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1228 u32 rx_trans_cfg = 0;
1229 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1230 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1231 u32 bits_per_char;
1232 struct geni_se se;
1233
1234 if (!uport->membase)
1235 return -EINVAL;
1236
1237 uport->private_data = &earlycon_private_data;
1238
1239 memset(&se, 0, sizeof(se));
1240 se.base = uport->membase;
1241 if (geni_se_read_proto(&se) != GENI_SE_UART)
1242 return -ENXIO;
1243 /*
1244 * Ignore Flow control.
1245 * n = 8.
1246 */
1247 tx_trans_cfg = UART_CTS_MASK;
1248 bits_per_char = BITS_PER_BYTE;
1249
1250 /*
1251 * Make an unconditional cancel on the main sequencer to reset
1252 * it else we could end up in data loss scenarios.
1253 */
1254 qcom_geni_serial_poll_tx_done(uport);
1255 qcom_geni_serial_abort_rx(uport);
1256 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1257 false, true, true);
1258 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1259 geni_se_select_mode(&se, GENI_SE_FIFO);
1260
1261 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1262 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1263 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1264 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1265 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1266 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1267 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1268
1269 dev->con->write = qcom_geni_serial_earlycon_write;
1270 dev->con->setup = NULL;
1271 qcom_geni_serial_enable_early_read(&se, dev->con);
1272
1273 return 0;
1274}
1275OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1276 qcom_geni_serial_earlycon_setup);
1277
1278static int __init console_register(struct uart_driver *drv)
1279{
1280 return uart_register_driver(drv);
1281}
1282
1283static void console_unregister(struct uart_driver *drv)
1284{
1285 uart_unregister_driver(drv);
1286}
1287
1288static struct console cons_ops = {
1289 .name = "ttyMSM",
1290 .write = qcom_geni_serial_console_write,
1291 .device = uart_console_device,
1292 .setup = qcom_geni_console_setup,
1293 .flags = CON_PRINTBUFFER,
1294 .index = -1,
1295 .data = &qcom_geni_console_driver,
1296};
1297
1298static struct uart_driver qcom_geni_console_driver = {
1299 .owner = THIS_MODULE,
1300 .driver_name = "qcom_geni_console",
1301 .dev_name = "ttyMSM",
1302 .nr = GENI_UART_CONS_PORTS,
1303 .cons = &cons_ops,
1304};
1305#else
1306static int console_register(struct uart_driver *drv)
1307{
1308 return 0;
1309}
1310
1311static void console_unregister(struct uart_driver *drv)
1312{
1313}
1314#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1315
1316static struct uart_driver qcom_geni_uart_driver = {
1317 .owner = THIS_MODULE,
1318 .driver_name = "qcom_geni_uart",
1319 .dev_name = "ttyHS",
1320 .nr = GENI_UART_PORTS,
1321};
1322
1323static void qcom_geni_serial_pm(struct uart_port *uport,
1324 unsigned int new_state, unsigned int old_state)
1325{
1326 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1327
1328 /* If we've never been called, treat it as off */
1329 if (old_state == UART_PM_STATE_UNDEFINED)
1330 old_state = UART_PM_STATE_OFF;
1331
1332 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1333 geni_icc_enable(&port->se);
1334 geni_se_resources_on(&port->se);
1335 } else if (new_state == UART_PM_STATE_OFF &&
1336 old_state == UART_PM_STATE_ON) {
1337 geni_se_resources_off(&port->se);
1338 geni_icc_disable(&port->se);
1339 }
1340}
1341
1342static const struct uart_ops qcom_geni_console_pops = {
1343 .tx_empty = qcom_geni_serial_tx_empty,
1344 .stop_tx = qcom_geni_serial_stop_tx,
1345 .start_tx = qcom_geni_serial_start_tx,
1346 .stop_rx = qcom_geni_serial_stop_rx,
1347 .start_rx = qcom_geni_serial_start_rx,
1348 .set_termios = qcom_geni_serial_set_termios,
1349 .startup = qcom_geni_serial_startup,
1350 .request_port = qcom_geni_serial_request_port,
1351 .config_port = qcom_geni_serial_config_port,
1352 .shutdown = qcom_geni_serial_shutdown,
1353 .type = qcom_geni_serial_get_type,
1354 .set_mctrl = qcom_geni_serial_set_mctrl,
1355 .get_mctrl = qcom_geni_serial_get_mctrl,
1356#ifdef CONFIG_CONSOLE_POLL
1357 .poll_get_char = qcom_geni_serial_get_char,
1358 .poll_put_char = qcom_geni_serial_poll_put_char,
1359#endif
1360 .pm = qcom_geni_serial_pm,
1361};
1362
1363static const struct uart_ops qcom_geni_uart_pops = {
1364 .tx_empty = qcom_geni_serial_tx_empty,
1365 .stop_tx = qcom_geni_serial_stop_tx,
1366 .start_tx = qcom_geni_serial_start_tx,
1367 .stop_rx = qcom_geni_serial_stop_rx,
1368 .set_termios = qcom_geni_serial_set_termios,
1369 .startup = qcom_geni_serial_startup,
1370 .request_port = qcom_geni_serial_request_port,
1371 .config_port = qcom_geni_serial_config_port,
1372 .shutdown = qcom_geni_serial_shutdown,
1373 .type = qcom_geni_serial_get_type,
1374 .set_mctrl = qcom_geni_serial_set_mctrl,
1375 .get_mctrl = qcom_geni_serial_get_mctrl,
1376 .pm = qcom_geni_serial_pm,
1377};
1378
1379static int qcom_geni_serial_probe(struct platform_device *pdev)
1380{
1381 int ret = 0;
1382 int line;
1383 struct qcom_geni_serial_port *port;
1384 struct uart_port *uport;
1385 struct resource *res;
1386 int irq;
1387 bool console = false;
1388 struct uart_driver *drv;
1389
1390 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1391 console = true;
1392
1393 if (console) {
1394 drv = &qcom_geni_console_driver;
1395 line = of_alias_get_id(pdev->dev.of_node, "serial");
1396 } else {
1397 drv = &qcom_geni_uart_driver;
1398 line = of_alias_get_id(pdev->dev.of_node, "serial");
1399 if (line == -ENODEV) /* compat with non-standard aliases */
1400 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1401 }
1402
1403 port = get_port_from_line(line, console);
1404 if (IS_ERR(port)) {
1405 dev_err(&pdev->dev, "Invalid line %d\n", line);
1406 return PTR_ERR(port);
1407 }
1408
1409 uport = &port->uport;
1410 /* Don't allow 2 drivers to access the same port */
1411 if (uport->private_data)
1412 return -ENODEV;
1413
1414 uport->dev = &pdev->dev;
1415 port->se.dev = &pdev->dev;
1416 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1417 port->se.clk = devm_clk_get(&pdev->dev, "se");
1418 if (IS_ERR(port->se.clk)) {
1419 ret = PTR_ERR(port->se.clk);
1420 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1421 return ret;
1422 }
1423
1424 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1425 if (!res)
1426 return -EINVAL;
1427 uport->mapbase = res->start;
1428
1429 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1430 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1431 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1432
1433 if (!console) {
1434 port->rx_fifo = devm_kcalloc(uport->dev,
1435 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1436 if (!port->rx_fifo)
1437 return -ENOMEM;
1438 }
1439
1440 ret = geni_icc_get(&port->se, NULL);
1441 if (ret)
1442 return ret;
1443 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1444 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1445
1446 /* Set BW for register access */
1447 ret = geni_icc_set_bw(&port->se);
1448 if (ret)
1449 return ret;
1450
1451 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1452 "qcom_geni_serial_%s%d",
1453 uart_console(uport) ? "console" : "uart", uport->line);
1454 if (!port->name)
1455 return -ENOMEM;
1456
1457 irq = platform_get_irq(pdev, 0);
1458 if (irq < 0)
1459 return irq;
1460 uport->irq = irq;
1461 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1462
1463 if (!console)
1464 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1465
1466 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1467 port->rx_tx_swap = true;
1468
1469 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1470 port->cts_rts_swap = true;
1471
1472 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1473 if (ret)
1474 return ret;
1475 /* OPP table is optional */
1476 ret = devm_pm_opp_of_add_table(&pdev->dev);
1477 if (ret && ret != -ENODEV) {
1478 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1479 return ret;
1480 }
1481
1482 port->private_data.drv = drv;
1483 uport->private_data = &port->private_data;
1484 platform_set_drvdata(pdev, port);
1485 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1486
1487 ret = uart_add_one_port(drv, uport);
1488 if (ret)
1489 return ret;
1490
1491 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1492 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1493 IRQF_TRIGGER_HIGH, port->name, uport);
1494 if (ret) {
1495 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1496 uart_remove_one_port(drv, uport);
1497 return ret;
1498 }
1499
1500 /*
1501 * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1502 * enabled/disabled from dev_pm_arm_wake_irq during system
1503 * suspend/resume respectively.
1504 */
1505 pm_runtime_set_active(&pdev->dev);
1506
1507 if (port->wakeup_irq > 0) {
1508 device_init_wakeup(&pdev->dev, true);
1509 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1510 port->wakeup_irq);
1511 if (ret) {
1512 device_init_wakeup(&pdev->dev, false);
1513 uart_remove_one_port(drv, uport);
1514 return ret;
1515 }
1516 }
1517
1518 return 0;
1519}
1520
1521static int qcom_geni_serial_remove(struct platform_device *pdev)
1522{
1523 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1524 struct uart_driver *drv = port->private_data.drv;
1525
1526 dev_pm_clear_wake_irq(&pdev->dev);
1527 device_init_wakeup(&pdev->dev, false);
1528 uart_remove_one_port(drv, &port->uport);
1529
1530 return 0;
1531}
1532
1533static int qcom_geni_serial_sys_suspend(struct device *dev)
1534{
1535 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1536 struct uart_port *uport = &port->uport;
1537 struct qcom_geni_private_data *private_data = uport->private_data;
1538
1539 /*
1540 * This is done so we can hit the lowest possible state in suspend
1541 * even with no_console_suspend
1542 */
1543 if (uart_console(uport)) {
1544 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY);
1545 geni_icc_set_bw(&port->se);
1546 }
1547 return uart_suspend_port(private_data->drv, uport);
1548}
1549
1550static int qcom_geni_serial_sys_resume(struct device *dev)
1551{
1552 int ret;
1553 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1554 struct uart_port *uport = &port->uport;
1555 struct qcom_geni_private_data *private_data = uport->private_data;
1556
1557 ret = uart_resume_port(private_data->drv, uport);
1558 if (uart_console(uport)) {
1559 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);
1560 geni_icc_set_bw(&port->se);
1561 }
1562 return ret;
1563}
1564
1565static int qcom_geni_serial_sys_hib_resume(struct device *dev)
1566{
1567 int ret = 0;
1568 struct uart_port *uport;
1569 struct qcom_geni_private_data *private_data;
1570 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1571
1572 uport = &port->uport;
1573 private_data = uport->private_data;
1574
1575 if (uart_console(uport)) {
1576 geni_icc_set_tag(&port->se, 0x7);
1577 geni_icc_set_bw(&port->se);
1578 ret = uart_resume_port(private_data->drv, uport);
1579 /*
1580 * For hibernation usecase clients for
1581 * console UART won't call port setup during restore,
1582 * hence call port setup for console uart.
1583 */
1584 qcom_geni_serial_port_setup(uport);
1585 } else {
1586 /*
1587 * Peripheral register settings are lost during hibernation.
1588 * Update setup flag such that port setup happens again
1589 * during next session. Clients of HS-UART will close and
1590 * open the port during hibernation.
1591 */
1592 port->setup = false;
1593 }
1594 return ret;
1595}
1596
1597static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1598 .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1599 .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume),
1600 .freeze = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1601 .poweroff = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1602 .restore = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume),
1603 .thaw = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume),
1604};
1605
1606static const struct of_device_id qcom_geni_serial_match_table[] = {
1607 { .compatible = "qcom,geni-debug-uart", },
1608 { .compatible = "qcom,geni-uart", },
1609 {}
1610};
1611MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1612
1613static struct platform_driver qcom_geni_serial_platform_driver = {
1614 .remove = qcom_geni_serial_remove,
1615 .probe = qcom_geni_serial_probe,
1616 .driver = {
1617 .name = "qcom_geni_serial",
1618 .of_match_table = qcom_geni_serial_match_table,
1619 .pm = &qcom_geni_serial_pm_ops,
1620 },
1621};
1622
1623static int __init qcom_geni_serial_init(void)
1624{
1625 int ret;
1626
1627 ret = console_register(&qcom_geni_console_driver);
1628 if (ret)
1629 return ret;
1630
1631 ret = uart_register_driver(&qcom_geni_uart_driver);
1632 if (ret) {
1633 console_unregister(&qcom_geni_console_driver);
1634 return ret;
1635 }
1636
1637 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1638 if (ret) {
1639 console_unregister(&qcom_geni_console_driver);
1640 uart_unregister_driver(&qcom_geni_uart_driver);
1641 }
1642 return ret;
1643}
1644module_init(qcom_geni_serial_init);
1645
1646static void __exit qcom_geni_serial_exit(void)
1647{
1648 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1649 console_unregister(&qcom_geni_console_driver);
1650 uart_unregister_driver(&qcom_geni_uart_driver);
1651}
1652module_exit(qcom_geni_serial_exit);
1653
1654MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1655MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4#include <linux/clk.h>
5#include <linux/console.h>
6#include <linux/io.h>
7#include <linux/iopoll.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12#include <linux/qcom-geni-se.h>
13#include <linux/serial.h>
14#include <linux/serial_core.h>
15#include <linux/slab.h>
16#include <linux/tty.h>
17#include <linux/tty_flip.h>
18
19/* UART specific GENI registers */
20#define SE_UART_TX_TRANS_CFG 0x25c
21#define SE_UART_TX_WORD_LEN 0x268
22#define SE_UART_TX_STOP_BIT_LEN 0x26c
23#define SE_UART_TX_TRANS_LEN 0x270
24#define SE_UART_RX_TRANS_CFG 0x280
25#define SE_UART_RX_WORD_LEN 0x28c
26#define SE_UART_RX_STALE_CNT 0x294
27#define SE_UART_TX_PARITY_CFG 0x2a4
28#define SE_UART_RX_PARITY_CFG 0x2a8
29
30/* SE_UART_TRANS_CFG */
31#define UART_TX_PAR_EN BIT(0)
32#define UART_CTS_MASK BIT(1)
33
34/* SE_UART_TX_WORD_LEN */
35#define TX_WORD_LEN_MSK GENMASK(9, 0)
36
37/* SE_UART_TX_STOP_BIT_LEN */
38#define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
39#define TX_STOP_BIT_LEN_1 0
40#define TX_STOP_BIT_LEN_1_5 1
41#define TX_STOP_BIT_LEN_2 2
42
43/* SE_UART_TX_TRANS_LEN */
44#define TX_TRANS_LEN_MSK GENMASK(23, 0)
45
46/* SE_UART_RX_TRANS_CFG */
47#define UART_RX_INS_STATUS_BIT BIT(2)
48#define UART_RX_PAR_EN BIT(3)
49
50/* SE_UART_RX_WORD_LEN */
51#define RX_WORD_LEN_MASK GENMASK(9, 0)
52
53/* SE_UART_RX_STALE_CNT */
54#define RX_STALE_CNT GENMASK(23, 0)
55
56/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
57#define PAR_CALC_EN BIT(0)
58#define PAR_MODE_MSK GENMASK(2, 1)
59#define PAR_MODE_SHFT 1
60#define PAR_EVEN 0x00
61#define PAR_ODD 0x01
62#define PAR_SPACE 0x10
63#define PAR_MARK 0x11
64
65/* UART M_CMD OP codes */
66#define UART_START_TX 0x1
67#define UART_START_BREAK 0x4
68#define UART_STOP_BREAK 0x5
69/* UART S_CMD OP codes */
70#define UART_START_READ 0x1
71#define UART_PARAM 0x1
72
73#define UART_OVERSAMPLING 32
74#define STALE_TIMEOUT 16
75#define DEFAULT_BITS_PER_CHAR 10
76#define GENI_UART_CONS_PORTS 1
77#define DEF_FIFO_DEPTH_WORDS 16
78#define DEF_TX_WM 2
79#define DEF_FIFO_WIDTH_BITS 32
80#define UART_CONSOLE_RX_WM 2
81
82#ifdef CONFIG_CONSOLE_POLL
83#define RX_BYTES_PW 1
84#else
85#define RX_BYTES_PW 4
86#endif
87
88struct qcom_geni_serial_port {
89 struct uart_port uport;
90 struct geni_se se;
91 char name[20];
92 u32 tx_fifo_depth;
93 u32 tx_fifo_width;
94 u32 rx_fifo_depth;
95 u32 tx_wm;
96 u32 rx_wm;
97 u32 rx_rfr;
98 enum geni_se_xfer_mode xfer_mode;
99 bool setup;
100 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
101 unsigned int xmit_size;
102 unsigned int baud;
103 unsigned int tx_bytes_pw;
104 unsigned int rx_bytes_pw;
105 bool brk;
106};
107
108static const struct uart_ops qcom_geni_serial_pops;
109static struct uart_driver qcom_geni_console_driver;
110static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
111static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
112static void qcom_geni_serial_stop_rx(struct uart_port *uport);
113
114static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
115 32000000, 48000000, 64000000, 80000000,
116 96000000, 100000000};
117
118#define to_dev_port(ptr, member) \
119 container_of(ptr, struct qcom_geni_serial_port, member)
120
121static struct qcom_geni_serial_port qcom_geni_console_port;
122
123static int qcom_geni_serial_request_port(struct uart_port *uport)
124{
125 struct platform_device *pdev = to_platform_device(uport->dev);
126 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
127 struct resource *res;
128
129 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
130 uport->membase = devm_ioremap_resource(&pdev->dev, res);
131 if (IS_ERR(uport->membase))
132 return PTR_ERR(uport->membase);
133 port->se.base = uport->membase;
134 return 0;
135}
136
137static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
138{
139 if (cfg_flags & UART_CONFIG_TYPE) {
140 uport->type = PORT_MSM;
141 qcom_geni_serial_request_port(uport);
142 }
143}
144
145static unsigned int qcom_geni_cons_get_mctrl(struct uart_port *uport)
146{
147 return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
148}
149
150static void qcom_geni_cons_set_mctrl(struct uart_port *uport,
151 unsigned int mctrl)
152{
153}
154
155static const char *qcom_geni_serial_get_type(struct uart_port *uport)
156{
157 return "MSM";
158}
159
160static struct qcom_geni_serial_port *get_port_from_line(int line)
161{
162 if (line < 0 || line >= GENI_UART_CONS_PORTS)
163 return ERR_PTR(-ENXIO);
164 return &qcom_geni_console_port;
165}
166
167static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
168 int offset, int field, bool set)
169{
170 u32 reg;
171 struct qcom_geni_serial_port *port;
172 unsigned int baud;
173 unsigned int fifo_bits;
174 unsigned long timeout_us = 20000;
175
176 /* Ensure polling is not re-ordered before the prior writes/reads */
177 mb();
178
179 if (uport->private_data) {
180 port = to_dev_port(uport, uport);
181 baud = port->baud;
182 if (!baud)
183 baud = 115200;
184 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
185 /*
186 * Total polling iterations based on FIFO worth of bytes to be
187 * sent at current baud. Add a little fluff to the wait.
188 */
189 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
190 }
191
192 return !readl_poll_timeout_atomic(uport->membase + offset, reg,
193 (bool)(reg & field) == set, 10, timeout_us);
194}
195
196static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
197{
198 u32 m_cmd;
199
200 writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
201 m_cmd = UART_START_TX << M_OPCODE_SHFT;
202 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
203}
204
205static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
206{
207 int done;
208 u32 irq_clear = M_CMD_DONE_EN;
209
210 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
211 M_CMD_DONE_EN, true);
212 if (!done) {
213 writel_relaxed(M_GENI_CMD_ABORT, uport->membase +
214 SE_GENI_M_CMD_CTRL_REG);
215 irq_clear |= M_CMD_ABORT_EN;
216 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
217 M_CMD_ABORT_EN, true);
218 }
219 writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
220}
221
222static void qcom_geni_serial_abort_rx(struct uart_port *uport)
223{
224 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
225
226 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
227 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
228 S_GENI_CMD_ABORT, false);
229 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
230 writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
231}
232
233#ifdef CONFIG_CONSOLE_POLL
234static int qcom_geni_serial_get_char(struct uart_port *uport)
235{
236 u32 rx_fifo;
237 u32 status;
238
239 status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
240 writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
241
242 status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
243 writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
244
245 /*
246 * Ensure the writes to clear interrupts is not re-ordered after
247 * reading the data.
248 */
249 mb();
250
251 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
252 if (!(status & RX_FIFO_WC_MSK))
253 return NO_POLL_CHAR;
254
255 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
256 return rx_fifo & 0xff;
257}
258
259static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
260 unsigned char c)
261{
262 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
263
264 writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG);
265 qcom_geni_serial_setup_tx(uport, 1);
266 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
267 M_TX_FIFO_WATERMARK_EN, true));
268 writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn);
269 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
270 SE_GENI_M_IRQ_CLEAR);
271 qcom_geni_serial_poll_tx_done(uport);
272}
273#endif
274
275#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
276static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
277{
278 writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn);
279}
280
281static void
282__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
283 unsigned int count)
284{
285 int i;
286 u32 bytes_to_send = count;
287
288 for (i = 0; i < count; i++) {
289 if (s[i] == '\n')
290 bytes_to_send++;
291 }
292
293 writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
294 qcom_geni_serial_setup_tx(uport, bytes_to_send);
295 for (i = 0; i < count; ) {
296 size_t chars_to_write = 0;
297 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
298
299 /*
300 * If the WM bit never set, then the Tx state machine is not
301 * in a valid state, so break, cancel/abort any existing
302 * command. Unfortunately the current data being written is
303 * lost.
304 */
305 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
306 M_TX_FIFO_WATERMARK_EN, true))
307 break;
308 chars_to_write = min_t(size_t, (size_t)(count - i), avail / 2);
309 uart_console_write(uport, s + i, chars_to_write,
310 qcom_geni_serial_wr_char);
311 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
312 SE_GENI_M_IRQ_CLEAR);
313 i += chars_to_write;
314 }
315 qcom_geni_serial_poll_tx_done(uport);
316}
317
318static void qcom_geni_serial_console_write(struct console *co, const char *s,
319 unsigned int count)
320{
321 struct uart_port *uport;
322 struct qcom_geni_serial_port *port;
323 bool locked = true;
324 unsigned long flags;
325
326 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
327
328 port = get_port_from_line(co->index);
329 if (IS_ERR(port))
330 return;
331
332 uport = &port->uport;
333 if (oops_in_progress)
334 locked = spin_trylock_irqsave(&uport->lock, flags);
335 else
336 spin_lock_irqsave(&uport->lock, flags);
337
338 /* Cancel the current write to log the fault */
339 if (!locked) {
340 geni_se_cancel_m_cmd(&port->se);
341 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
342 M_CMD_CANCEL_EN, true)) {
343 geni_se_abort_m_cmd(&port->se);
344 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
345 M_CMD_ABORT_EN, true);
346 writel_relaxed(M_CMD_ABORT_EN, uport->membase +
347 SE_GENI_M_IRQ_CLEAR);
348 }
349 writel_relaxed(M_CMD_CANCEL_EN, uport->membase +
350 SE_GENI_M_IRQ_CLEAR);
351 }
352
353 __qcom_geni_serial_console_write(uport, s, count);
354 if (locked)
355 spin_unlock_irqrestore(&uport->lock, flags);
356}
357
358static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
359{
360 u32 i;
361 unsigned char buf[sizeof(u32)];
362 struct tty_port *tport;
363 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
364
365 tport = &uport->state->port;
366 for (i = 0; i < bytes; ) {
367 int c;
368 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
369
370 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
371 i += chunk;
372 if (drop)
373 continue;
374
375 for (c = 0; c < chunk; c++) {
376 int sysrq;
377
378 uport->icount.rx++;
379 if (port->brk && buf[c] == 0) {
380 port->brk = false;
381 if (uart_handle_break(uport))
382 continue;
383 }
384
385 sysrq = uart_handle_sysrq_char(uport, buf[c]);
386 if (!sysrq)
387 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
388 }
389 }
390 if (!drop)
391 tty_flip_buffer_push(tport);
392 return 0;
393}
394#else
395static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
396{
397 return -EPERM;
398}
399
400#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
401
402static void qcom_geni_serial_start_tx(struct uart_port *uport)
403{
404 u32 irq_en;
405 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
406 u32 status;
407
408 if (port->xfer_mode == GENI_SE_FIFO) {
409 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
410 if (status & M_GENI_CMD_ACTIVE)
411 return;
412
413 if (!qcom_geni_serial_tx_empty(uport))
414 return;
415
416 /*
417 * Ensure writing to IRQ_EN & watermark registers are not
418 * re-ordered before checking the status of the Serial
419 * Engine and TX FIFO
420 */
421 mb();
422
423 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
424 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
425
426 writel_relaxed(port->tx_wm, uport->membase +
427 SE_GENI_TX_WATERMARK_REG);
428 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
429 }
430}
431
432static void qcom_geni_serial_stop_tx(struct uart_port *uport)
433{
434 u32 irq_en;
435 u32 status;
436 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
437
438 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
439 irq_en &= ~M_CMD_DONE_EN;
440 if (port->xfer_mode == GENI_SE_FIFO) {
441 irq_en &= ~M_TX_FIFO_WATERMARK_EN;
442 writel_relaxed(0, uport->membase +
443 SE_GENI_TX_WATERMARK_REG);
444 }
445 port->xmit_size = 0;
446 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
447 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
448 /* Possible stop tx is called multiple times. */
449 if (!(status & M_GENI_CMD_ACTIVE))
450 return;
451
452 /*
453 * Ensure cancel command write is not re-ordered before checking
454 * the status of the Primary Sequencer.
455 */
456 mb();
457
458 geni_se_cancel_m_cmd(&port->se);
459 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
460 M_CMD_CANCEL_EN, true)) {
461 geni_se_abort_m_cmd(&port->se);
462 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
463 M_CMD_ABORT_EN, true);
464 writel_relaxed(M_CMD_ABORT_EN, uport->membase +
465 SE_GENI_M_IRQ_CLEAR);
466 }
467 writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
468}
469
470static void qcom_geni_serial_start_rx(struct uart_port *uport)
471{
472 u32 irq_en;
473 u32 status;
474 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
475
476 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
477 if (status & S_GENI_CMD_ACTIVE)
478 qcom_geni_serial_stop_rx(uport);
479
480 /*
481 * Ensure setup command write is not re-ordered before checking
482 * the status of the Secondary Sequencer.
483 */
484 mb();
485
486 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
487
488 if (port->xfer_mode == GENI_SE_FIFO) {
489 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
490 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
491 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
492
493 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
494 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
495 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
496 }
497}
498
499static void qcom_geni_serial_stop_rx(struct uart_port *uport)
500{
501 u32 irq_en;
502 u32 status;
503 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
504 u32 irq_clear = S_CMD_DONE_EN;
505
506 if (port->xfer_mode == GENI_SE_FIFO) {
507 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
508 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
509 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
510
511 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
512 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
513 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
514 }
515
516 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
517 /* Possible stop rx is called multiple times. */
518 if (!(status & S_GENI_CMD_ACTIVE))
519 return;
520
521 /*
522 * Ensure cancel command write is not re-ordered before checking
523 * the status of the Secondary Sequencer.
524 */
525 mb();
526
527 geni_se_cancel_s_cmd(&port->se);
528 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
529 S_GENI_CMD_CANCEL, false);
530 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
531 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
532 if (status & S_GENI_CMD_ACTIVE)
533 qcom_geni_serial_abort_rx(uport);
534}
535
536static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
537{
538 u32 status;
539 u32 word_cnt;
540 u32 last_word_byte_cnt;
541 u32 last_word_partial;
542 u32 total_bytes;
543 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
544
545 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
546 word_cnt = status & RX_FIFO_WC_MSK;
547 last_word_partial = status & RX_LAST;
548 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
549 RX_LAST_BYTE_VALID_SHFT;
550
551 if (!word_cnt)
552 return;
553 total_bytes = port->rx_bytes_pw * (word_cnt - 1);
554 if (last_word_partial && last_word_byte_cnt)
555 total_bytes += last_word_byte_cnt;
556 else
557 total_bytes += port->rx_bytes_pw;
558 port->handle_rx(uport, total_bytes, drop);
559}
560
561static void qcom_geni_serial_handle_tx(struct uart_port *uport)
562{
563 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
564 struct circ_buf *xmit = &uport->state->xmit;
565 size_t avail;
566 size_t remaining;
567 int i;
568 u32 status;
569 unsigned int chunk;
570 int tail;
571
572 chunk = uart_circ_chars_pending(xmit);
573 status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
574 /* Both FIFO and framework buffer are drained */
575 if (chunk == port->xmit_size && !status) {
576 port->xmit_size = 0;
577 uart_circ_clear(xmit);
578 qcom_geni_serial_stop_tx(uport);
579 goto out_write_wakeup;
580 }
581 chunk -= port->xmit_size;
582
583 avail = (port->tx_fifo_depth - port->tx_wm) * port->tx_bytes_pw;
584 tail = (xmit->tail + port->xmit_size) & (UART_XMIT_SIZE - 1);
585 if (chunk > (UART_XMIT_SIZE - tail))
586 chunk = UART_XMIT_SIZE - tail;
587 if (chunk > avail)
588 chunk = avail;
589
590 if (!chunk)
591 goto out_write_wakeup;
592
593 qcom_geni_serial_setup_tx(uport, chunk);
594
595 remaining = chunk;
596 for (i = 0; i < chunk; ) {
597 unsigned int tx_bytes;
598 unsigned int buf = 0;
599 int c;
600
601 tx_bytes = min_t(size_t, remaining, (size_t)port->tx_bytes_pw);
602 for (c = 0; c < tx_bytes ; c++)
603 buf |= (xmit->buf[tail + c] << (c * BITS_PER_BYTE));
604
605 writel_relaxed(buf, uport->membase + SE_GENI_TX_FIFOn);
606
607 i += tx_bytes;
608 tail = (tail + tx_bytes) & (UART_XMIT_SIZE - 1);
609 uport->icount.tx += tx_bytes;
610 remaining -= tx_bytes;
611 }
612 qcom_geni_serial_poll_tx_done(uport);
613 port->xmit_size += chunk;
614out_write_wakeup:
615 uart_write_wakeup(uport);
616}
617
618static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
619{
620 unsigned int m_irq_status;
621 unsigned int s_irq_status;
622 struct uart_port *uport = dev;
623 unsigned long flags;
624 unsigned int m_irq_en;
625 bool drop_rx = false;
626 struct tty_port *tport = &uport->state->port;
627 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
628
629 if (uport->suspended)
630 return IRQ_HANDLED;
631
632 spin_lock_irqsave(&uport->lock, flags);
633 m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
634 s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
635 m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
636 writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
637 writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
638
639 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
640 goto out_unlock;
641
642 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
643 uport->icount.overrun++;
644 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
645 }
646
647 if (m_irq_status & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN) &&
648 m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
649 qcom_geni_serial_handle_tx(uport);
650
651 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
652 if (s_irq_status & S_GP_IRQ_0_EN)
653 uport->icount.parity++;
654 drop_rx = true;
655 } else if (s_irq_status & S_GP_IRQ_2_EN ||
656 s_irq_status & S_GP_IRQ_3_EN) {
657 uport->icount.brk++;
658 port->brk = true;
659 }
660
661 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
662 s_irq_status & S_RX_FIFO_LAST_EN)
663 qcom_geni_serial_handle_rx(uport, drop_rx);
664
665out_unlock:
666 spin_unlock_irqrestore(&uport->lock, flags);
667 return IRQ_HANDLED;
668}
669
670static int get_tx_fifo_size(struct qcom_geni_serial_port *port)
671{
672 struct uart_port *uport;
673
674 if (!port)
675 return -ENODEV;
676
677 uport = &port->uport;
678 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
679 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
680 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
681 uport->fifosize =
682 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
683 return 0;
684}
685
686static void set_rfr_wm(struct qcom_geni_serial_port *port)
687{
688 /*
689 * Set RFR (Flow off) to FIFO_DEPTH - 2.
690 * RX WM level at 10% RX_FIFO_DEPTH.
691 * TX WM level at 10% TX_FIFO_DEPTH.
692 */
693 port->rx_rfr = port->rx_fifo_depth - 2;
694 port->rx_wm = UART_CONSOLE_RX_WM;
695 port->tx_wm = DEF_TX_WM;
696}
697
698static void qcom_geni_serial_shutdown(struct uart_port *uport)
699{
700 unsigned long flags;
701
702 /* Stop the console before stopping the current tx */
703 console_stop(uport->cons);
704
705 disable_irq(uport->irq);
706 free_irq(uport->irq, uport);
707 spin_lock_irqsave(&uport->lock, flags);
708 qcom_geni_serial_stop_tx(uport);
709 qcom_geni_serial_stop_rx(uport);
710 spin_unlock_irqrestore(&uport->lock, flags);
711}
712
713static int qcom_geni_serial_port_setup(struct uart_port *uport)
714{
715 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
716 unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
717
718 set_rfr_wm(port);
719 writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
720 /*
721 * Make an unconditional cancel on the main sequencer to reset
722 * it else we could end up in data loss scenarios.
723 */
724 port->xfer_mode = GENI_SE_FIFO;
725 qcom_geni_serial_poll_tx_done(uport);
726 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
727 false, true, false);
728 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
729 false, false, true);
730 geni_se_init(&port->se, port->rx_wm, port->rx_rfr);
731 geni_se_select_mode(&port->se, port->xfer_mode);
732 port->setup = true;
733 return 0;
734}
735
736static int qcom_geni_serial_startup(struct uart_port *uport)
737{
738 int ret;
739 u32 proto;
740 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
741
742 scnprintf(port->name, sizeof(port->name),
743 "qcom_serial_geni%d", uport->line);
744
745 proto = geni_se_read_proto(&port->se);
746 if (proto != GENI_SE_UART) {
747 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
748 return -ENXIO;
749 }
750
751 get_tx_fifo_size(port);
752 if (!port->setup) {
753 ret = qcom_geni_serial_port_setup(uport);
754 if (ret)
755 return ret;
756 }
757
758 ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
759 port->name, uport);
760 if (ret)
761 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
762 return ret;
763}
764
765static unsigned long get_clk_cfg(unsigned long clk_freq)
766{
767 int i;
768
769 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
770 if (!(root_freq[i] % clk_freq))
771 return root_freq[i];
772 }
773 return 0;
774}
775
776static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
777{
778 unsigned long ser_clk;
779 unsigned long desired_clk;
780
781 desired_clk = baud * UART_OVERSAMPLING;
782 ser_clk = get_clk_cfg(desired_clk);
783 if (!ser_clk) {
784 pr_err("%s: Can't find matching DFS entry for baud %d\n",
785 __func__, baud);
786 return ser_clk;
787 }
788
789 *clk_div = ser_clk / desired_clk;
790 return ser_clk;
791}
792
793static void qcom_geni_serial_set_termios(struct uart_port *uport,
794 struct ktermios *termios, struct ktermios *old)
795{
796 unsigned int baud;
797 unsigned int bits_per_char;
798 unsigned int tx_trans_cfg;
799 unsigned int tx_parity_cfg;
800 unsigned int rx_trans_cfg;
801 unsigned int rx_parity_cfg;
802 unsigned int stop_bit_len;
803 unsigned int clk_div;
804 unsigned long ser_clk_cfg;
805 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
806 unsigned long clk_rate;
807
808 qcom_geni_serial_stop_rx(uport);
809 /* baud rate */
810 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
811 port->baud = baud;
812 clk_rate = get_clk_div_rate(baud, &clk_div);
813 if (!clk_rate)
814 goto out_restart_rx;
815
816 uport->uartclk = clk_rate;
817 clk_set_rate(port->se.clk, clk_rate);
818 ser_clk_cfg = SER_CLK_EN;
819 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
820
821 /* parity */
822 tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG);
823 tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG);
824 rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG);
825 rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG);
826 if (termios->c_cflag & PARENB) {
827 tx_trans_cfg |= UART_TX_PAR_EN;
828 rx_trans_cfg |= UART_RX_PAR_EN;
829 tx_parity_cfg |= PAR_CALC_EN;
830 rx_parity_cfg |= PAR_CALC_EN;
831 if (termios->c_cflag & PARODD) {
832 tx_parity_cfg |= PAR_ODD;
833 rx_parity_cfg |= PAR_ODD;
834 } else if (termios->c_cflag & CMSPAR) {
835 tx_parity_cfg |= PAR_SPACE;
836 rx_parity_cfg |= PAR_SPACE;
837 } else {
838 tx_parity_cfg |= PAR_EVEN;
839 rx_parity_cfg |= PAR_EVEN;
840 }
841 } else {
842 tx_trans_cfg &= ~UART_TX_PAR_EN;
843 rx_trans_cfg &= ~UART_RX_PAR_EN;
844 tx_parity_cfg &= ~PAR_CALC_EN;
845 rx_parity_cfg &= ~PAR_CALC_EN;
846 }
847
848 /* bits per char */
849 switch (termios->c_cflag & CSIZE) {
850 case CS5:
851 bits_per_char = 5;
852 break;
853 case CS6:
854 bits_per_char = 6;
855 break;
856 case CS7:
857 bits_per_char = 7;
858 break;
859 case CS8:
860 default:
861 bits_per_char = 8;
862 break;
863 }
864
865 /* stop bits */
866 if (termios->c_cflag & CSTOPB)
867 stop_bit_len = TX_STOP_BIT_LEN_2;
868 else
869 stop_bit_len = TX_STOP_BIT_LEN_1;
870
871 /* flow control, clear the CTS_MASK bit if using flow control. */
872 if (termios->c_cflag & CRTSCTS)
873 tx_trans_cfg &= ~UART_CTS_MASK;
874 else
875 tx_trans_cfg |= UART_CTS_MASK;
876
877 if (baud)
878 uart_update_timeout(uport, termios->c_cflag, baud);
879
880 writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
881 writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
882 writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
883 writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
884 writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
885 writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
886 writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
887 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
888 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
889out_restart_rx:
890 qcom_geni_serial_start_rx(uport);
891}
892
893static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
894{
895 return !readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
896}
897
898#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
899static int __init qcom_geni_console_setup(struct console *co, char *options)
900{
901 struct uart_port *uport;
902 struct qcom_geni_serial_port *port;
903 int baud;
904 int bits = 8;
905 int parity = 'n';
906 int flow = 'n';
907
908 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
909 return -ENXIO;
910
911 port = get_port_from_line(co->index);
912 if (IS_ERR(port)) {
913 pr_err("Invalid line %d(%d)\n", co->index, (int)PTR_ERR(port));
914 return PTR_ERR(port);
915 }
916
917 uport = &port->uport;
918
919 if (unlikely(!uport->membase))
920 return -ENXIO;
921
922 if (geni_se_resources_on(&port->se)) {
923 dev_err(port->se.dev, "Error turning on resources\n");
924 return -ENXIO;
925 }
926
927 if (unlikely(geni_se_read_proto(&port->se) != GENI_SE_UART)) {
928 geni_se_resources_off(&port->se);
929 return -ENXIO;
930 }
931
932 if (!port->setup) {
933 port->tx_bytes_pw = 1;
934 port->rx_bytes_pw = RX_BYTES_PW;
935 qcom_geni_serial_stop_rx(uport);
936 qcom_geni_serial_port_setup(uport);
937 }
938
939 if (options)
940 uart_parse_options(options, &baud, &parity, &bits, &flow);
941
942 return uart_set_options(uport, co, baud, parity, bits, flow);
943}
944
945static int __init console_register(struct uart_driver *drv)
946{
947 return uart_register_driver(drv);
948}
949
950static void console_unregister(struct uart_driver *drv)
951{
952 uart_unregister_driver(drv);
953}
954
955static struct console cons_ops = {
956 .name = "ttyMSM",
957 .write = qcom_geni_serial_console_write,
958 .device = uart_console_device,
959 .setup = qcom_geni_console_setup,
960 .flags = CON_PRINTBUFFER,
961 .index = -1,
962 .data = &qcom_geni_console_driver,
963};
964
965static struct uart_driver qcom_geni_console_driver = {
966 .owner = THIS_MODULE,
967 .driver_name = "qcom_geni_console",
968 .dev_name = "ttyMSM",
969 .nr = GENI_UART_CONS_PORTS,
970 .cons = &cons_ops,
971};
972#else
973static int console_register(struct uart_driver *drv)
974{
975 return 0;
976}
977
978static void console_unregister(struct uart_driver *drv)
979{
980}
981#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
982
983static void qcom_geni_serial_cons_pm(struct uart_port *uport,
984 unsigned int new_state, unsigned int old_state)
985{
986 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
987
988 if (unlikely(!uart_console(uport)))
989 return;
990
991 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
992 geni_se_resources_on(&port->se);
993 else if (new_state == UART_PM_STATE_OFF &&
994 old_state == UART_PM_STATE_ON)
995 geni_se_resources_off(&port->se);
996}
997
998static const struct uart_ops qcom_geni_console_pops = {
999 .tx_empty = qcom_geni_serial_tx_empty,
1000 .stop_tx = qcom_geni_serial_stop_tx,
1001 .start_tx = qcom_geni_serial_start_tx,
1002 .stop_rx = qcom_geni_serial_stop_rx,
1003 .set_termios = qcom_geni_serial_set_termios,
1004 .startup = qcom_geni_serial_startup,
1005 .request_port = qcom_geni_serial_request_port,
1006 .config_port = qcom_geni_serial_config_port,
1007 .shutdown = qcom_geni_serial_shutdown,
1008 .type = qcom_geni_serial_get_type,
1009 .set_mctrl = qcom_geni_cons_set_mctrl,
1010 .get_mctrl = qcom_geni_cons_get_mctrl,
1011#ifdef CONFIG_CONSOLE_POLL
1012 .poll_get_char = qcom_geni_serial_get_char,
1013 .poll_put_char = qcom_geni_serial_poll_put_char,
1014#endif
1015 .pm = qcom_geni_serial_cons_pm,
1016};
1017
1018static int qcom_geni_serial_probe(struct platform_device *pdev)
1019{
1020 int ret = 0;
1021 int line = -1;
1022 struct qcom_geni_serial_port *port;
1023 struct uart_port *uport;
1024 struct resource *res;
1025 int irq;
1026
1027 if (pdev->dev.of_node)
1028 line = of_alias_get_id(pdev->dev.of_node, "serial");
1029 else
1030 line = pdev->id;
1031
1032 if (line < 0 || line >= GENI_UART_CONS_PORTS)
1033 return -ENXIO;
1034 port = get_port_from_line(line);
1035 if (IS_ERR(port)) {
1036 ret = PTR_ERR(port);
1037 dev_err(&pdev->dev, "Invalid line %d(%d)\n", line, ret);
1038 return ret;
1039 }
1040
1041 uport = &port->uport;
1042 /* Don't allow 2 drivers to access the same port */
1043 if (uport->private_data)
1044 return -ENODEV;
1045
1046 uport->dev = &pdev->dev;
1047 port->se.dev = &pdev->dev;
1048 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1049 port->se.clk = devm_clk_get(&pdev->dev, "se");
1050 if (IS_ERR(port->se.clk)) {
1051 ret = PTR_ERR(port->se.clk);
1052 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1053 return ret;
1054 }
1055
1056 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1057 if (!res)
1058 return -EINVAL;
1059 uport->mapbase = res->start;
1060
1061 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1062 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1063 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1064
1065 irq = platform_get_irq(pdev, 0);
1066 if (irq < 0) {
1067 dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
1068 return irq;
1069 }
1070 uport->irq = irq;
1071
1072 uport->private_data = &qcom_geni_console_driver;
1073 platform_set_drvdata(pdev, port);
1074 port->handle_rx = handle_rx_console;
1075 port->setup = false;
1076 return uart_add_one_port(&qcom_geni_console_driver, uport);
1077}
1078
1079static int qcom_geni_serial_remove(struct platform_device *pdev)
1080{
1081 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1082 struct uart_driver *drv = port->uport.private_data;
1083
1084 uart_remove_one_port(drv, &port->uport);
1085 return 0;
1086}
1087
1088static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev)
1089{
1090 struct platform_device *pdev = to_platform_device(dev);
1091 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1092 struct uart_port *uport = &port->uport;
1093
1094 uart_suspend_port(uport->private_data, uport);
1095 return 0;
1096}
1097
1098static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev)
1099{
1100 struct platform_device *pdev = to_platform_device(dev);
1101 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1102 struct uart_port *uport = &port->uport;
1103
1104 if (console_suspend_enabled && uport->suspended) {
1105 uart_resume_port(uport->private_data, uport);
1106 disable_irq(uport->irq);
1107 }
1108 return 0;
1109}
1110
1111static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1112 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend_noirq,
1113 qcom_geni_serial_sys_resume_noirq)
1114};
1115
1116static const struct of_device_id qcom_geni_serial_match_table[] = {
1117 { .compatible = "qcom,geni-debug-uart", },
1118 {}
1119};
1120MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1121
1122static struct platform_driver qcom_geni_serial_platform_driver = {
1123 .remove = qcom_geni_serial_remove,
1124 .probe = qcom_geni_serial_probe,
1125 .driver = {
1126 .name = "qcom_geni_serial",
1127 .of_match_table = qcom_geni_serial_match_table,
1128 .pm = &qcom_geni_serial_pm_ops,
1129 },
1130};
1131
1132static int __init qcom_geni_serial_init(void)
1133{
1134 int ret;
1135
1136 qcom_geni_console_port.uport.iotype = UPIO_MEM;
1137 qcom_geni_console_port.uport.ops = &qcom_geni_console_pops;
1138 qcom_geni_console_port.uport.flags = UPF_BOOT_AUTOCONF;
1139 qcom_geni_console_port.uport.line = 0;
1140
1141 ret = console_register(&qcom_geni_console_driver);
1142 if (ret)
1143 return ret;
1144
1145 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1146 if (ret)
1147 console_unregister(&qcom_geni_console_driver);
1148 return ret;
1149}
1150module_init(qcom_geni_serial_init);
1151
1152static void __exit qcom_geni_serial_exit(void)
1153{
1154 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1155 console_unregister(&qcom_geni_console_driver);
1156}
1157module_exit(qcom_geni_serial_exit);
1158
1159MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1160MODULE_LICENSE("GPL v2");