Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2008-2014 STMicroelectronics Limited
4 *
5 * Author: Angus Clark <Angus.Clark@st.com>
6 * Patrice Chotard <patrice.chotard@st.com>
7 * Lee Jones <lee.jones@linaro.org>
8 *
9 * SPI master mode controller driver, used in STMicroelectronics devices.
10 */
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/pinctrl/consumer.h>
18#include <linux/platform_device.h>
19#include <linux/of.h>
20#include <linux/of_irq.h>
21#include <linux/pm_runtime.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/spi_bitbang.h>
24
25/* SSC registers */
26#define SSC_BRG 0x000
27#define SSC_TBUF 0x004
28#define SSC_RBUF 0x008
29#define SSC_CTL 0x00C
30#define SSC_IEN 0x010
31#define SSC_I2C 0x018
32
33/* SSC Control */
34#define SSC_CTL_DATA_WIDTH_9 0x8
35#define SSC_CTL_DATA_WIDTH_MSK 0xf
36#define SSC_CTL_BM 0xf
37#define SSC_CTL_HB BIT(4)
38#define SSC_CTL_PH BIT(5)
39#define SSC_CTL_PO BIT(6)
40#define SSC_CTL_SR BIT(7)
41#define SSC_CTL_MS BIT(8)
42#define SSC_CTL_EN BIT(9)
43#define SSC_CTL_LPB BIT(10)
44#define SSC_CTL_EN_TX_FIFO BIT(11)
45#define SSC_CTL_EN_RX_FIFO BIT(12)
46#define SSC_CTL_EN_CLST_RX BIT(13)
47
48/* SSC Interrupt Enable */
49#define SSC_IEN_TEEN BIT(2)
50
51#define FIFO_SIZE 8
52
53struct spi_st {
54 /* SSC SPI Controller */
55 void __iomem *base;
56 struct clk *clk;
57 struct device *dev;
58
59 /* SSC SPI current transaction */
60 const u8 *tx_ptr;
61 u8 *rx_ptr;
62 u16 bytes_per_word;
63 unsigned int words_remaining;
64 unsigned int baud;
65 struct completion done;
66};
67
68/* Load the TX FIFO */
69static void ssc_write_tx_fifo(struct spi_st *spi_st)
70{
71 unsigned int count, i;
72 uint32_t word = 0;
73
74 if (spi_st->words_remaining > FIFO_SIZE)
75 count = FIFO_SIZE;
76 else
77 count = spi_st->words_remaining;
78
79 for (i = 0; i < count; i++) {
80 if (spi_st->tx_ptr) {
81 if (spi_st->bytes_per_word == 1) {
82 word = *spi_st->tx_ptr++;
83 } else {
84 word = *spi_st->tx_ptr++;
85 word = *spi_st->tx_ptr++ | (word << 8);
86 }
87 }
88 writel_relaxed(word, spi_st->base + SSC_TBUF);
89 }
90}
91
92/* Read the RX FIFO */
93static void ssc_read_rx_fifo(struct spi_st *spi_st)
94{
95 unsigned int count, i;
96 uint32_t word = 0;
97
98 if (spi_st->words_remaining > FIFO_SIZE)
99 count = FIFO_SIZE;
100 else
101 count = spi_st->words_remaining;
102
103 for (i = 0; i < count; i++) {
104 word = readl_relaxed(spi_st->base + SSC_RBUF);
105
106 if (spi_st->rx_ptr) {
107 if (spi_st->bytes_per_word == 1) {
108 *spi_st->rx_ptr++ = (uint8_t)word;
109 } else {
110 *spi_st->rx_ptr++ = (word >> 8);
111 *spi_st->rx_ptr++ = word & 0xff;
112 }
113 }
114 }
115 spi_st->words_remaining -= count;
116}
117
118static int spi_st_transfer_one(struct spi_master *master,
119 struct spi_device *spi, struct spi_transfer *t)
120{
121 struct spi_st *spi_st = spi_master_get_devdata(master);
122 uint32_t ctl = 0;
123
124 /* Setup transfer */
125 spi_st->tx_ptr = t->tx_buf;
126 spi_st->rx_ptr = t->rx_buf;
127
128 if (spi->bits_per_word > 8) {
129 /*
130 * Anything greater than 8 bits-per-word requires 2
131 * bytes-per-word in the RX/TX buffers
132 */
133 spi_st->bytes_per_word = 2;
134 spi_st->words_remaining = t->len / 2;
135
136 } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) {
137 /*
138 * If transfer is even-length, and 8 bits-per-word, then
139 * implement as half-length 16 bits-per-word transfer
140 */
141 spi_st->bytes_per_word = 2;
142 spi_st->words_remaining = t->len / 2;
143
144 /* Set SSC_CTL to 16 bits-per-word */
145 ctl = readl_relaxed(spi_st->base + SSC_CTL);
146 writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL);
147
148 readl_relaxed(spi_st->base + SSC_RBUF);
149
150 } else {
151 spi_st->bytes_per_word = 1;
152 spi_st->words_remaining = t->len;
153 }
154
155 reinit_completion(&spi_st->done);
156
157 /* Start transfer by writing to the TX FIFO */
158 ssc_write_tx_fifo(spi_st);
159 writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN);
160
161 /* Wait for transfer to complete */
162 wait_for_completion(&spi_st->done);
163
164 /* Restore SSC_CTL if necessary */
165 if (ctl)
166 writel_relaxed(ctl, spi_st->base + SSC_CTL);
167
168 spi_finalize_current_transfer(spi->master);
169
170 return t->len;
171}
172
173/* the spi->mode bits understood by this driver: */
174#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH)
175static int spi_st_setup(struct spi_device *spi)
176{
177 struct spi_st *spi_st = spi_master_get_devdata(spi->master);
178 u32 spi_st_clk, sscbrg, var;
179 u32 hz = spi->max_speed_hz;
180
181 if (!hz) {
182 dev_err(&spi->dev, "max_speed_hz unspecified\n");
183 return -EINVAL;
184 }
185
186 if (!spi->cs_gpiod) {
187 dev_err(&spi->dev, "no valid gpio assigned\n");
188 return -EINVAL;
189 }
190
191 spi_st_clk = clk_get_rate(spi_st->clk);
192
193 /* Set SSC_BRF */
194 sscbrg = spi_st_clk / (2 * hz);
195 if (sscbrg < 0x07 || sscbrg > BIT(16)) {
196 dev_err(&spi->dev,
197 "baudrate %d outside valid range %d\n", sscbrg, hz);
198 return -EINVAL;
199 }
200
201 spi_st->baud = spi_st_clk / (2 * sscbrg);
202 if (sscbrg == BIT(16)) /* 16-bit counter wraps */
203 sscbrg = 0x0;
204
205 writel_relaxed(sscbrg, spi_st->base + SSC_BRG);
206
207 dev_dbg(&spi->dev,
208 "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
209 hz, spi_st->baud, sscbrg);
210
211 /* Set SSC_CTL and enable SSC */
212 var = readl_relaxed(spi_st->base + SSC_CTL);
213 var |= SSC_CTL_MS;
214
215 if (spi->mode & SPI_CPOL)
216 var |= SSC_CTL_PO;
217 else
218 var &= ~SSC_CTL_PO;
219
220 if (spi->mode & SPI_CPHA)
221 var |= SSC_CTL_PH;
222 else
223 var &= ~SSC_CTL_PH;
224
225 if ((spi->mode & SPI_LSB_FIRST) == 0)
226 var |= SSC_CTL_HB;
227 else
228 var &= ~SSC_CTL_HB;
229
230 if (spi->mode & SPI_LOOP)
231 var |= SSC_CTL_LPB;
232 else
233 var &= ~SSC_CTL_LPB;
234
235 var &= ~SSC_CTL_DATA_WIDTH_MSK;
236 var |= (spi->bits_per_word - 1);
237
238 var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
239 var |= SSC_CTL_EN;
240
241 writel_relaxed(var, spi_st->base + SSC_CTL);
242
243 /* Clear the status register */
244 readl_relaxed(spi_st->base + SSC_RBUF);
245
246 return 0;
247}
248
249/* Interrupt fired when TX shift register becomes empty */
250static irqreturn_t spi_st_irq(int irq, void *dev_id)
251{
252 struct spi_st *spi_st = (struct spi_st *)dev_id;
253
254 /* Read RX FIFO */
255 ssc_read_rx_fifo(spi_st);
256
257 /* Fill TX FIFO */
258 if (spi_st->words_remaining) {
259 ssc_write_tx_fifo(spi_st);
260 } else {
261 /* TX/RX complete */
262 writel_relaxed(0x0, spi_st->base + SSC_IEN);
263 /*
264 * read SSC_IEN to ensure that this bit is set
265 * before re-enabling interrupt
266 */
267 readl(spi_st->base + SSC_IEN);
268 complete(&spi_st->done);
269 }
270
271 return IRQ_HANDLED;
272}
273
274static int spi_st_probe(struct platform_device *pdev)
275{
276 struct device_node *np = pdev->dev.of_node;
277 struct spi_master *master;
278 struct spi_st *spi_st;
279 int irq, ret = 0;
280 u32 var;
281
282 master = spi_alloc_master(&pdev->dev, sizeof(*spi_st));
283 if (!master)
284 return -ENOMEM;
285
286 master->dev.of_node = np;
287 master->mode_bits = MODEBITS;
288 master->setup = spi_st_setup;
289 master->transfer_one = spi_st_transfer_one;
290 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
291 master->auto_runtime_pm = true;
292 master->bus_num = pdev->id;
293 master->use_gpio_descriptors = true;
294 spi_st = spi_master_get_devdata(master);
295
296 spi_st->clk = devm_clk_get(&pdev->dev, "ssc");
297 if (IS_ERR(spi_st->clk)) {
298 dev_err(&pdev->dev, "Unable to request clock\n");
299 ret = PTR_ERR(spi_st->clk);
300 goto put_master;
301 }
302
303 ret = clk_prepare_enable(spi_st->clk);
304 if (ret)
305 goto put_master;
306
307 init_completion(&spi_st->done);
308
309 /* Get resources */
310 spi_st->base = devm_platform_ioremap_resource(pdev, 0);
311 if (IS_ERR(spi_st->base)) {
312 ret = PTR_ERR(spi_st->base);
313 goto clk_disable;
314 }
315
316 /* Disable I2C and Reset SSC */
317 writel_relaxed(0x0, spi_st->base + SSC_I2C);
318 var = readw_relaxed(spi_st->base + SSC_CTL);
319 var |= SSC_CTL_SR;
320 writel_relaxed(var, spi_st->base + SSC_CTL);
321
322 udelay(1);
323 var = readl_relaxed(spi_st->base + SSC_CTL);
324 var &= ~SSC_CTL_SR;
325 writel_relaxed(var, spi_st->base + SSC_CTL);
326
327 /* Set SSC into slave mode before reconfiguring PIO pins */
328 var = readl_relaxed(spi_st->base + SSC_CTL);
329 var &= ~SSC_CTL_MS;
330 writel_relaxed(var, spi_st->base + SSC_CTL);
331
332 irq = irq_of_parse_and_map(np, 0);
333 if (!irq) {
334 dev_err(&pdev->dev, "IRQ missing or invalid\n");
335 ret = -EINVAL;
336 goto clk_disable;
337 }
338
339 ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0,
340 pdev->name, spi_st);
341 if (ret) {
342 dev_err(&pdev->dev, "Failed to request irq %d\n", irq);
343 goto clk_disable;
344 }
345
346 /* by default the device is on */
347 pm_runtime_set_active(&pdev->dev);
348 pm_runtime_enable(&pdev->dev);
349
350 platform_set_drvdata(pdev, master);
351
352 ret = devm_spi_register_master(&pdev->dev, master);
353 if (ret) {
354 dev_err(&pdev->dev, "Failed to register master\n");
355 goto rpm_disable;
356 }
357
358 return 0;
359
360rpm_disable:
361 pm_runtime_disable(&pdev->dev);
362clk_disable:
363 clk_disable_unprepare(spi_st->clk);
364put_master:
365 spi_master_put(master);
366 return ret;
367}
368
369static int spi_st_remove(struct platform_device *pdev)
370{
371 struct spi_master *master = platform_get_drvdata(pdev);
372 struct spi_st *spi_st = spi_master_get_devdata(master);
373
374 pm_runtime_disable(&pdev->dev);
375
376 clk_disable_unprepare(spi_st->clk);
377
378 pinctrl_pm_select_sleep_state(&pdev->dev);
379
380 return 0;
381}
382
383#ifdef CONFIG_PM
384static int spi_st_runtime_suspend(struct device *dev)
385{
386 struct spi_master *master = dev_get_drvdata(dev);
387 struct spi_st *spi_st = spi_master_get_devdata(master);
388
389 writel_relaxed(0, spi_st->base + SSC_IEN);
390 pinctrl_pm_select_sleep_state(dev);
391
392 clk_disable_unprepare(spi_st->clk);
393
394 return 0;
395}
396
397static int spi_st_runtime_resume(struct device *dev)
398{
399 struct spi_master *master = dev_get_drvdata(dev);
400 struct spi_st *spi_st = spi_master_get_devdata(master);
401 int ret;
402
403 ret = clk_prepare_enable(spi_st->clk);
404 pinctrl_pm_select_default_state(dev);
405
406 return ret;
407}
408#endif
409
410#ifdef CONFIG_PM_SLEEP
411static int spi_st_suspend(struct device *dev)
412{
413 struct spi_master *master = dev_get_drvdata(dev);
414 int ret;
415
416 ret = spi_master_suspend(master);
417 if (ret)
418 return ret;
419
420 return pm_runtime_force_suspend(dev);
421}
422
423static int spi_st_resume(struct device *dev)
424{
425 struct spi_master *master = dev_get_drvdata(dev);
426 int ret;
427
428 ret = spi_master_resume(master);
429 if (ret)
430 return ret;
431
432 return pm_runtime_force_resume(dev);
433}
434#endif
435
436static const struct dev_pm_ops spi_st_pm = {
437 SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume)
438 SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL)
439};
440
441static const struct of_device_id stm_spi_match[] = {
442 { .compatible = "st,comms-ssc4-spi", },
443 {},
444};
445MODULE_DEVICE_TABLE(of, stm_spi_match);
446
447static struct platform_driver spi_st_driver = {
448 .driver = {
449 .name = "spi-st",
450 .pm = &spi_st_pm,
451 .of_match_table = of_match_ptr(stm_spi_match),
452 },
453 .probe = spi_st_probe,
454 .remove = spi_st_remove,
455};
456module_platform_driver(spi_st_driver);
457
458MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
459MODULE_DESCRIPTION("STM SSC SPI driver");
460MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (c) 2008-2014 STMicroelectronics Limited
3 *
4 * Author: Angus Clark <Angus.Clark@st.com>
5 * Patrice Chotard <patrice.chotard@st.com>
6 * Lee Jones <lee.jones@linaro.org>
7 *
8 * SPI master mode controller driver, used in STMicroelectronics devices.
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License Version 2.0 only. See linux/COPYING for more information.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/platform_device.h>
21#include <linux/of.h>
22#include <linux/of_gpio.h>
23#include <linux/of_irq.h>
24#include <linux/pm_runtime.h>
25#include <linux/spi/spi.h>
26#include <linux/spi/spi_bitbang.h>
27
28/* SSC registers */
29#define SSC_BRG 0x000
30#define SSC_TBUF 0x004
31#define SSC_RBUF 0x008
32#define SSC_CTL 0x00C
33#define SSC_IEN 0x010
34#define SSC_I2C 0x018
35
36/* SSC Control */
37#define SSC_CTL_DATA_WIDTH_9 0x8
38#define SSC_CTL_DATA_WIDTH_MSK 0xf
39#define SSC_CTL_BM 0xf
40#define SSC_CTL_HB BIT(4)
41#define SSC_CTL_PH BIT(5)
42#define SSC_CTL_PO BIT(6)
43#define SSC_CTL_SR BIT(7)
44#define SSC_CTL_MS BIT(8)
45#define SSC_CTL_EN BIT(9)
46#define SSC_CTL_LPB BIT(10)
47#define SSC_CTL_EN_TX_FIFO BIT(11)
48#define SSC_CTL_EN_RX_FIFO BIT(12)
49#define SSC_CTL_EN_CLST_RX BIT(13)
50
51/* SSC Interrupt Enable */
52#define SSC_IEN_TEEN BIT(2)
53
54#define FIFO_SIZE 8
55
56struct spi_st {
57 /* SSC SPI Controller */
58 void __iomem *base;
59 struct clk *clk;
60 struct device *dev;
61
62 /* SSC SPI current transaction */
63 const u8 *tx_ptr;
64 u8 *rx_ptr;
65 u16 bytes_per_word;
66 unsigned int words_remaining;
67 unsigned int baud;
68 struct completion done;
69};
70
71/* Load the TX FIFO */
72static void ssc_write_tx_fifo(struct spi_st *spi_st)
73{
74 unsigned int count, i;
75 uint32_t word = 0;
76
77 if (spi_st->words_remaining > FIFO_SIZE)
78 count = FIFO_SIZE;
79 else
80 count = spi_st->words_remaining;
81
82 for (i = 0; i < count; i++) {
83 if (spi_st->tx_ptr) {
84 if (spi_st->bytes_per_word == 1) {
85 word = *spi_st->tx_ptr++;
86 } else {
87 word = *spi_st->tx_ptr++;
88 word = *spi_st->tx_ptr++ | (word << 8);
89 }
90 }
91 writel_relaxed(word, spi_st->base + SSC_TBUF);
92 }
93}
94
95/* Read the RX FIFO */
96static void ssc_read_rx_fifo(struct spi_st *spi_st)
97{
98 unsigned int count, i;
99 uint32_t word = 0;
100
101 if (spi_st->words_remaining > FIFO_SIZE)
102 count = FIFO_SIZE;
103 else
104 count = spi_st->words_remaining;
105
106 for (i = 0; i < count; i++) {
107 word = readl_relaxed(spi_st->base + SSC_RBUF);
108
109 if (spi_st->rx_ptr) {
110 if (spi_st->bytes_per_word == 1) {
111 *spi_st->rx_ptr++ = (uint8_t)word;
112 } else {
113 *spi_st->rx_ptr++ = (word >> 8);
114 *spi_st->rx_ptr++ = word & 0xff;
115 }
116 }
117 }
118 spi_st->words_remaining -= count;
119}
120
121static int spi_st_transfer_one(struct spi_master *master,
122 struct spi_device *spi, struct spi_transfer *t)
123{
124 struct spi_st *spi_st = spi_master_get_devdata(master);
125 uint32_t ctl = 0;
126
127 /* Setup transfer */
128 spi_st->tx_ptr = t->tx_buf;
129 spi_st->rx_ptr = t->rx_buf;
130
131 if (spi->bits_per_word > 8) {
132 /*
133 * Anything greater than 8 bits-per-word requires 2
134 * bytes-per-word in the RX/TX buffers
135 */
136 spi_st->bytes_per_word = 2;
137 spi_st->words_remaining = t->len / 2;
138
139 } else if (spi->bits_per_word == 8 && !(t->len & 0x1)) {
140 /*
141 * If transfer is even-length, and 8 bits-per-word, then
142 * implement as half-length 16 bits-per-word transfer
143 */
144 spi_st->bytes_per_word = 2;
145 spi_st->words_remaining = t->len / 2;
146
147 /* Set SSC_CTL to 16 bits-per-word */
148 ctl = readl_relaxed(spi_st->base + SSC_CTL);
149 writel_relaxed((ctl | 0xf), spi_st->base + SSC_CTL);
150
151 readl_relaxed(spi_st->base + SSC_RBUF);
152
153 } else {
154 spi_st->bytes_per_word = 1;
155 spi_st->words_remaining = t->len;
156 }
157
158 reinit_completion(&spi_st->done);
159
160 /* Start transfer by writing to the TX FIFO */
161 ssc_write_tx_fifo(spi_st);
162 writel_relaxed(SSC_IEN_TEEN, spi_st->base + SSC_IEN);
163
164 /* Wait for transfer to complete */
165 wait_for_completion(&spi_st->done);
166
167 /* Restore SSC_CTL if necessary */
168 if (ctl)
169 writel_relaxed(ctl, spi_st->base + SSC_CTL);
170
171 spi_finalize_current_transfer(spi->master);
172
173 return t->len;
174}
175
176static void spi_st_cleanup(struct spi_device *spi)
177{
178 gpio_free(spi->cs_gpio);
179}
180
181/* the spi->mode bits understood by this driver: */
182#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH)
183static int spi_st_setup(struct spi_device *spi)
184{
185 struct spi_st *spi_st = spi_master_get_devdata(spi->master);
186 u32 spi_st_clk, sscbrg, var;
187 u32 hz = spi->max_speed_hz;
188 int cs = spi->cs_gpio;
189 int ret;
190
191 if (!hz) {
192 dev_err(&spi->dev, "max_speed_hz unspecified\n");
193 return -EINVAL;
194 }
195
196 if (!gpio_is_valid(cs)) {
197 dev_err(&spi->dev, "%d is not a valid gpio\n", cs);
198 return -EINVAL;
199 }
200
201 ret = gpio_request(cs, dev_name(&spi->dev));
202 if (ret) {
203 dev_err(&spi->dev, "could not request gpio:%d\n", cs);
204 return ret;
205 }
206
207 ret = gpio_direction_output(cs, spi->mode & SPI_CS_HIGH);
208 if (ret)
209 goto out_free_gpio;
210
211 spi_st_clk = clk_get_rate(spi_st->clk);
212
213 /* Set SSC_BRF */
214 sscbrg = spi_st_clk / (2 * hz);
215 if (sscbrg < 0x07 || sscbrg > BIT(16)) {
216 dev_err(&spi->dev,
217 "baudrate %d outside valid range %d\n", sscbrg, hz);
218 ret = -EINVAL;
219 goto out_free_gpio;
220 }
221
222 spi_st->baud = spi_st_clk / (2 * sscbrg);
223 if (sscbrg == BIT(16)) /* 16-bit counter wraps */
224 sscbrg = 0x0;
225
226 writel_relaxed(sscbrg, spi_st->base + SSC_BRG);
227
228 dev_dbg(&spi->dev,
229 "setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
230 hz, spi_st->baud, sscbrg);
231
232 /* Set SSC_CTL and enable SSC */
233 var = readl_relaxed(spi_st->base + SSC_CTL);
234 var |= SSC_CTL_MS;
235
236 if (spi->mode & SPI_CPOL)
237 var |= SSC_CTL_PO;
238 else
239 var &= ~SSC_CTL_PO;
240
241 if (spi->mode & SPI_CPHA)
242 var |= SSC_CTL_PH;
243 else
244 var &= ~SSC_CTL_PH;
245
246 if ((spi->mode & SPI_LSB_FIRST) == 0)
247 var |= SSC_CTL_HB;
248 else
249 var &= ~SSC_CTL_HB;
250
251 if (spi->mode & SPI_LOOP)
252 var |= SSC_CTL_LPB;
253 else
254 var &= ~SSC_CTL_LPB;
255
256 var &= ~SSC_CTL_DATA_WIDTH_MSK;
257 var |= (spi->bits_per_word - 1);
258
259 var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
260 var |= SSC_CTL_EN;
261
262 writel_relaxed(var, spi_st->base + SSC_CTL);
263
264 /* Clear the status register */
265 readl_relaxed(spi_st->base + SSC_RBUF);
266
267 return 0;
268
269out_free_gpio:
270 gpio_free(cs);
271 return ret;
272}
273
274/* Interrupt fired when TX shift register becomes empty */
275static irqreturn_t spi_st_irq(int irq, void *dev_id)
276{
277 struct spi_st *spi_st = (struct spi_st *)dev_id;
278
279 /* Read RX FIFO */
280 ssc_read_rx_fifo(spi_st);
281
282 /* Fill TX FIFO */
283 if (spi_st->words_remaining) {
284 ssc_write_tx_fifo(spi_st);
285 } else {
286 /* TX/RX complete */
287 writel_relaxed(0x0, spi_st->base + SSC_IEN);
288 /*
289 * read SSC_IEN to ensure that this bit is set
290 * before re-enabling interrupt
291 */
292 readl(spi_st->base + SSC_IEN);
293 complete(&spi_st->done);
294 }
295
296 return IRQ_HANDLED;
297}
298
299static int spi_st_probe(struct platform_device *pdev)
300{
301 struct device_node *np = pdev->dev.of_node;
302 struct spi_master *master;
303 struct resource *res;
304 struct spi_st *spi_st;
305 int irq, ret = 0;
306 u32 var;
307
308 master = spi_alloc_master(&pdev->dev, sizeof(*spi_st));
309 if (!master)
310 return -ENOMEM;
311
312 master->dev.of_node = np;
313 master->mode_bits = MODEBITS;
314 master->setup = spi_st_setup;
315 master->cleanup = spi_st_cleanup;
316 master->transfer_one = spi_st_transfer_one;
317 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
318 master->auto_runtime_pm = true;
319 master->bus_num = pdev->id;
320 spi_st = spi_master_get_devdata(master);
321
322 spi_st->clk = devm_clk_get(&pdev->dev, "ssc");
323 if (IS_ERR(spi_st->clk)) {
324 dev_err(&pdev->dev, "Unable to request clock\n");
325 ret = PTR_ERR(spi_st->clk);
326 goto put_master;
327 }
328
329 ret = clk_prepare_enable(spi_st->clk);
330 if (ret)
331 goto put_master;
332
333 init_completion(&spi_st->done);
334
335 /* Get resources */
336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
337 spi_st->base = devm_ioremap_resource(&pdev->dev, res);
338 if (IS_ERR(spi_st->base)) {
339 ret = PTR_ERR(spi_st->base);
340 goto clk_disable;
341 }
342
343 /* Disable I2C and Reset SSC */
344 writel_relaxed(0x0, spi_st->base + SSC_I2C);
345 var = readw_relaxed(spi_st->base + SSC_CTL);
346 var |= SSC_CTL_SR;
347 writel_relaxed(var, spi_st->base + SSC_CTL);
348
349 udelay(1);
350 var = readl_relaxed(spi_st->base + SSC_CTL);
351 var &= ~SSC_CTL_SR;
352 writel_relaxed(var, spi_st->base + SSC_CTL);
353
354 /* Set SSC into slave mode before reconfiguring PIO pins */
355 var = readl_relaxed(spi_st->base + SSC_CTL);
356 var &= ~SSC_CTL_MS;
357 writel_relaxed(var, spi_st->base + SSC_CTL);
358
359 irq = irq_of_parse_and_map(np, 0);
360 if (!irq) {
361 dev_err(&pdev->dev, "IRQ missing or invalid\n");
362 ret = -EINVAL;
363 goto clk_disable;
364 }
365
366 ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0,
367 pdev->name, spi_st);
368 if (ret) {
369 dev_err(&pdev->dev, "Failed to request irq %d\n", irq);
370 goto clk_disable;
371 }
372
373 /* by default the device is on */
374 pm_runtime_set_active(&pdev->dev);
375 pm_runtime_enable(&pdev->dev);
376
377 platform_set_drvdata(pdev, master);
378
379 ret = devm_spi_register_master(&pdev->dev, master);
380 if (ret) {
381 dev_err(&pdev->dev, "Failed to register master\n");
382 goto clk_disable;
383 }
384
385 return 0;
386
387clk_disable:
388 clk_disable_unprepare(spi_st->clk);
389put_master:
390 spi_master_put(master);
391 return ret;
392}
393
394static int spi_st_remove(struct platform_device *pdev)
395{
396 struct spi_master *master = platform_get_drvdata(pdev);
397 struct spi_st *spi_st = spi_master_get_devdata(master);
398
399 clk_disable_unprepare(spi_st->clk);
400
401 pinctrl_pm_select_sleep_state(&pdev->dev);
402
403 return 0;
404}
405
406#ifdef CONFIG_PM
407static int spi_st_runtime_suspend(struct device *dev)
408{
409 struct spi_master *master = dev_get_drvdata(dev);
410 struct spi_st *spi_st = spi_master_get_devdata(master);
411
412 writel_relaxed(0, spi_st->base + SSC_IEN);
413 pinctrl_pm_select_sleep_state(dev);
414
415 clk_disable_unprepare(spi_st->clk);
416
417 return 0;
418}
419
420static int spi_st_runtime_resume(struct device *dev)
421{
422 struct spi_master *master = dev_get_drvdata(dev);
423 struct spi_st *spi_st = spi_master_get_devdata(master);
424 int ret;
425
426 ret = clk_prepare_enable(spi_st->clk);
427 pinctrl_pm_select_default_state(dev);
428
429 return ret;
430}
431#endif
432
433#ifdef CONFIG_PM_SLEEP
434static int spi_st_suspend(struct device *dev)
435{
436 struct spi_master *master = dev_get_drvdata(dev);
437 int ret;
438
439 ret = spi_master_suspend(master);
440 if (ret)
441 return ret;
442
443 return pm_runtime_force_suspend(dev);
444}
445
446static int spi_st_resume(struct device *dev)
447{
448 struct spi_master *master = dev_get_drvdata(dev);
449 int ret;
450
451 ret = spi_master_resume(master);
452 if (ret)
453 return ret;
454
455 return pm_runtime_force_resume(dev);
456}
457#endif
458
459static const struct dev_pm_ops spi_st_pm = {
460 SET_SYSTEM_SLEEP_PM_OPS(spi_st_suspend, spi_st_resume)
461 SET_RUNTIME_PM_OPS(spi_st_runtime_suspend, spi_st_runtime_resume, NULL)
462};
463
464static const struct of_device_id stm_spi_match[] = {
465 { .compatible = "st,comms-ssc4-spi", },
466 {},
467};
468MODULE_DEVICE_TABLE(of, stm_spi_match);
469
470static struct platform_driver spi_st_driver = {
471 .driver = {
472 .name = "spi-st",
473 .pm = &spi_st_pm,
474 .of_match_table = of_match_ptr(stm_spi_match),
475 },
476 .probe = spi_st_probe,
477 .remove = spi_st_remove,
478};
479module_platform_driver(spi_st_driver);
480
481MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
482MODULE_DESCRIPTION("STM SSC SPI driver");
483MODULE_LICENSE("GPL v2");