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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/mmc/host/omap.c
4 *
5 * Copyright (C) 2004 Nokia Corporation
6 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
7 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
8 * Other hacks (DMA, SD, etc) by David Brownell
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/platform_device.h>
16#include <linux/interrupt.h>
17#include <linux/dmaengine.h>
18#include <linux/dma-mapping.h>
19#include <linux/delay.h>
20#include <linux/spinlock.h>
21#include <linux/timer.h>
22#include <linux/of.h>
23#include <linux/mmc/host.h>
24#include <linux/mmc/card.h>
25#include <linux/mmc/mmc.h>
26#include <linux/clk.h>
27#include <linux/scatterlist.h>
28#include <linux/slab.h>
29#include <linux/platform_data/mmc-omap.h>
30
31
32#define OMAP_MMC_REG_CMD 0x00
33#define OMAP_MMC_REG_ARGL 0x01
34#define OMAP_MMC_REG_ARGH 0x02
35#define OMAP_MMC_REG_CON 0x03
36#define OMAP_MMC_REG_STAT 0x04
37#define OMAP_MMC_REG_IE 0x05
38#define OMAP_MMC_REG_CTO 0x06
39#define OMAP_MMC_REG_DTO 0x07
40#define OMAP_MMC_REG_DATA 0x08
41#define OMAP_MMC_REG_BLEN 0x09
42#define OMAP_MMC_REG_NBLK 0x0a
43#define OMAP_MMC_REG_BUF 0x0b
44#define OMAP_MMC_REG_SDIO 0x0d
45#define OMAP_MMC_REG_REV 0x0f
46#define OMAP_MMC_REG_RSP0 0x10
47#define OMAP_MMC_REG_RSP1 0x11
48#define OMAP_MMC_REG_RSP2 0x12
49#define OMAP_MMC_REG_RSP3 0x13
50#define OMAP_MMC_REG_RSP4 0x14
51#define OMAP_MMC_REG_RSP5 0x15
52#define OMAP_MMC_REG_RSP6 0x16
53#define OMAP_MMC_REG_RSP7 0x17
54#define OMAP_MMC_REG_IOSR 0x18
55#define OMAP_MMC_REG_SYSC 0x19
56#define OMAP_MMC_REG_SYSS 0x1a
57
58#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
59#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
60#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
61#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
62#define OMAP_MMC_STAT_A_FULL (1 << 10)
63#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
64#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
65#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
66#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
67#define OMAP_MMC_STAT_END_BUSY (1 << 4)
68#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
69#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
70#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
71
72#define mmc_omap7xx() (host->features & MMC_OMAP7XX)
73#define mmc_omap15xx() (host->features & MMC_OMAP15XX)
74#define mmc_omap16xx() (host->features & MMC_OMAP16XX)
75#define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
76#define mmc_omap1() (host->features & MMC_OMAP1_MASK)
77#define mmc_omap2() (!mmc_omap1())
78
79#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
80#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
81#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
82
83/*
84 * Command types
85 */
86#define OMAP_MMC_CMDTYPE_BC 0
87#define OMAP_MMC_CMDTYPE_BCR 1
88#define OMAP_MMC_CMDTYPE_AC 2
89#define OMAP_MMC_CMDTYPE_ADTC 3
90
91#define DRIVER_NAME "mmci-omap"
92
93/* Specifies how often in millisecs to poll for card status changes
94 * when the cover switch is open */
95#define OMAP_MMC_COVER_POLL_DELAY 500
96
97struct mmc_omap_host;
98
99struct mmc_omap_slot {
100 int id;
101 unsigned int vdd;
102 u16 saved_con;
103 u16 bus_mode;
104 u16 power_mode;
105 unsigned int fclk_freq;
106
107 struct tasklet_struct cover_tasklet;
108 struct timer_list cover_timer;
109 unsigned cover_open;
110
111 struct mmc_request *mrq;
112 struct mmc_omap_host *host;
113 struct mmc_host *mmc;
114 struct omap_mmc_slot_data *pdata;
115};
116
117struct mmc_omap_host {
118 int initialized;
119 struct mmc_request * mrq;
120 struct mmc_command * cmd;
121 struct mmc_data * data;
122 struct mmc_host * mmc;
123 struct device * dev;
124 unsigned char id; /* 16xx chips have 2 MMC blocks */
125 struct clk * iclk;
126 struct clk * fclk;
127 struct dma_chan *dma_rx;
128 u32 dma_rx_burst;
129 struct dma_chan *dma_tx;
130 u32 dma_tx_burst;
131 void __iomem *virt_base;
132 unsigned int phys_base;
133 int irq;
134 unsigned char bus_mode;
135 unsigned int reg_shift;
136
137 struct work_struct cmd_abort_work;
138 unsigned abort:1;
139 struct timer_list cmd_abort_timer;
140
141 struct work_struct slot_release_work;
142 struct mmc_omap_slot *next_slot;
143 struct work_struct send_stop_work;
144 struct mmc_data *stop_data;
145
146 unsigned int sg_len;
147 int sg_idx;
148 u16 * buffer;
149 u32 buffer_bytes_left;
150 u32 total_bytes_left;
151
152 unsigned features;
153 unsigned brs_received:1, dma_done:1;
154 unsigned dma_in_use:1;
155 spinlock_t dma_lock;
156
157 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
158 struct mmc_omap_slot *current_slot;
159 spinlock_t slot_lock;
160 wait_queue_head_t slot_wq;
161 int nr_slots;
162
163 struct timer_list clk_timer;
164 spinlock_t clk_lock; /* for changing enabled state */
165 unsigned int fclk_enabled:1;
166 struct workqueue_struct *mmc_omap_wq;
167
168 struct omap_mmc_platform_data *pdata;
169};
170
171
172static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
173{
174 unsigned long tick_ns;
175
176 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
177 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
178 ndelay(8 * tick_ns);
179 }
180}
181
182static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
183{
184 unsigned long flags;
185
186 spin_lock_irqsave(&host->clk_lock, flags);
187 if (host->fclk_enabled != enable) {
188 host->fclk_enabled = enable;
189 if (enable)
190 clk_enable(host->fclk);
191 else
192 clk_disable(host->fclk);
193 }
194 spin_unlock_irqrestore(&host->clk_lock, flags);
195}
196
197static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
198{
199 struct mmc_omap_host *host = slot->host;
200 unsigned long flags;
201
202 if (claimed)
203 goto no_claim;
204 spin_lock_irqsave(&host->slot_lock, flags);
205 while (host->mmc != NULL) {
206 spin_unlock_irqrestore(&host->slot_lock, flags);
207 wait_event(host->slot_wq, host->mmc == NULL);
208 spin_lock_irqsave(&host->slot_lock, flags);
209 }
210 host->mmc = slot->mmc;
211 spin_unlock_irqrestore(&host->slot_lock, flags);
212no_claim:
213 del_timer(&host->clk_timer);
214 if (host->current_slot != slot || !claimed)
215 mmc_omap_fclk_offdelay(host->current_slot);
216
217 if (host->current_slot != slot) {
218 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
219 if (host->pdata->switch_slot != NULL)
220 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
221 host->current_slot = slot;
222 }
223
224 if (claimed) {
225 mmc_omap_fclk_enable(host, 1);
226
227 /* Doing the dummy read here seems to work around some bug
228 * at least in OMAP24xx silicon where the command would not
229 * start after writing the CMD register. Sigh. */
230 OMAP_MMC_READ(host, CON);
231
232 OMAP_MMC_WRITE(host, CON, slot->saved_con);
233 } else
234 mmc_omap_fclk_enable(host, 0);
235}
236
237static void mmc_omap_start_request(struct mmc_omap_host *host,
238 struct mmc_request *req);
239
240static void mmc_omap_slot_release_work(struct work_struct *work)
241{
242 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
243 slot_release_work);
244 struct mmc_omap_slot *next_slot = host->next_slot;
245 struct mmc_request *rq;
246
247 host->next_slot = NULL;
248 mmc_omap_select_slot(next_slot, 1);
249
250 rq = next_slot->mrq;
251 next_slot->mrq = NULL;
252 mmc_omap_start_request(host, rq);
253}
254
255static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
256{
257 struct mmc_omap_host *host = slot->host;
258 unsigned long flags;
259 int i;
260
261 BUG_ON(slot == NULL || host->mmc == NULL);
262
263 if (clk_enabled)
264 /* Keeps clock running for at least 8 cycles on valid freq */
265 mod_timer(&host->clk_timer, jiffies + HZ/10);
266 else {
267 del_timer(&host->clk_timer);
268 mmc_omap_fclk_offdelay(slot);
269 mmc_omap_fclk_enable(host, 0);
270 }
271
272 spin_lock_irqsave(&host->slot_lock, flags);
273 /* Check for any pending requests */
274 for (i = 0; i < host->nr_slots; i++) {
275 struct mmc_omap_slot *new_slot;
276
277 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
278 continue;
279
280 BUG_ON(host->next_slot != NULL);
281 new_slot = host->slots[i];
282 /* The current slot should not have a request in queue */
283 BUG_ON(new_slot == host->current_slot);
284
285 host->next_slot = new_slot;
286 host->mmc = new_slot->mmc;
287 spin_unlock_irqrestore(&host->slot_lock, flags);
288 queue_work(host->mmc_omap_wq, &host->slot_release_work);
289 return;
290 }
291
292 host->mmc = NULL;
293 wake_up(&host->slot_wq);
294 spin_unlock_irqrestore(&host->slot_lock, flags);
295}
296
297static inline
298int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
299{
300 if (slot->pdata->get_cover_state)
301 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
302 slot->id);
303 return 0;
304}
305
306static ssize_t
307mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
308 char *buf)
309{
310 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
311 struct mmc_omap_slot *slot = mmc_priv(mmc);
312
313 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
314 "closed");
315}
316
317static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
318
319static ssize_t
320mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
321 char *buf)
322{
323 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
324 struct mmc_omap_slot *slot = mmc_priv(mmc);
325
326 return sprintf(buf, "%s\n", slot->pdata->name);
327}
328
329static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
330
331static void
332mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
333{
334 u32 cmdreg;
335 u32 resptype;
336 u32 cmdtype;
337 u16 irq_mask;
338
339 host->cmd = cmd;
340
341 resptype = 0;
342 cmdtype = 0;
343
344 /* Our hardware needs to know exact type */
345 switch (mmc_resp_type(cmd)) {
346 case MMC_RSP_NONE:
347 break;
348 case MMC_RSP_R1:
349 case MMC_RSP_R1B:
350 /* resp 1, 1b, 6, 7 */
351 resptype = 1;
352 break;
353 case MMC_RSP_R2:
354 resptype = 2;
355 break;
356 case MMC_RSP_R3:
357 resptype = 3;
358 break;
359 default:
360 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
361 break;
362 }
363
364 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
365 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
366 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
367 cmdtype = OMAP_MMC_CMDTYPE_BC;
368 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
369 cmdtype = OMAP_MMC_CMDTYPE_BCR;
370 } else {
371 cmdtype = OMAP_MMC_CMDTYPE_AC;
372 }
373
374 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
375
376 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
377 cmdreg |= 1 << 6;
378
379 if (cmd->flags & MMC_RSP_BUSY)
380 cmdreg |= 1 << 11;
381
382 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
383 cmdreg |= 1 << 15;
384
385 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
386
387 OMAP_MMC_WRITE(host, CTO, 200);
388 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
389 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
390 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
391 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
392 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
393 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
394 OMAP_MMC_STAT_END_OF_DATA;
395 if (cmd->opcode == MMC_ERASE)
396 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
397 OMAP_MMC_WRITE(host, IE, irq_mask);
398 OMAP_MMC_WRITE(host, CMD, cmdreg);
399}
400
401static void
402mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
403 int abort)
404{
405 enum dma_data_direction dma_data_dir;
406 struct device *dev = mmc_dev(host->mmc);
407 struct dma_chan *c;
408
409 if (data->flags & MMC_DATA_WRITE) {
410 dma_data_dir = DMA_TO_DEVICE;
411 c = host->dma_tx;
412 } else {
413 dma_data_dir = DMA_FROM_DEVICE;
414 c = host->dma_rx;
415 }
416 if (c) {
417 if (data->error) {
418 dmaengine_terminate_all(c);
419 /* Claim nothing transferred on error... */
420 data->bytes_xfered = 0;
421 }
422 dev = c->device->dev;
423 }
424 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
425}
426
427static void mmc_omap_send_stop_work(struct work_struct *work)
428{
429 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
430 send_stop_work);
431 struct mmc_omap_slot *slot = host->current_slot;
432 struct mmc_data *data = host->stop_data;
433 unsigned long tick_ns;
434
435 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
436 ndelay(8*tick_ns);
437
438 mmc_omap_start_command(host, data->stop);
439}
440
441static void
442mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
443{
444 if (host->dma_in_use)
445 mmc_omap_release_dma(host, data, data->error);
446
447 host->data = NULL;
448 host->sg_len = 0;
449
450 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
451 * dozens of requests until the card finishes writing data.
452 * It'd be cheaper to just wait till an EOFB interrupt arrives...
453 */
454
455 if (!data->stop) {
456 struct mmc_host *mmc;
457
458 host->mrq = NULL;
459 mmc = host->mmc;
460 mmc_omap_release_slot(host->current_slot, 1);
461 mmc_request_done(mmc, data->mrq);
462 return;
463 }
464
465 host->stop_data = data;
466 queue_work(host->mmc_omap_wq, &host->send_stop_work);
467}
468
469static void
470mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
471{
472 struct mmc_omap_slot *slot = host->current_slot;
473 unsigned int restarts, passes, timeout;
474 u16 stat = 0;
475
476 /* Sending abort takes 80 clocks. Have some extra and round up */
477 timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
478 restarts = 0;
479 while (restarts < maxloops) {
480 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
481 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
482
483 passes = 0;
484 while (passes < timeout) {
485 stat = OMAP_MMC_READ(host, STAT);
486 if (stat & OMAP_MMC_STAT_END_OF_CMD)
487 goto out;
488 udelay(1);
489 passes++;
490 }
491
492 restarts++;
493 }
494out:
495 OMAP_MMC_WRITE(host, STAT, stat);
496}
497
498static void
499mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
500{
501 if (host->dma_in_use)
502 mmc_omap_release_dma(host, data, 1);
503
504 host->data = NULL;
505 host->sg_len = 0;
506
507 mmc_omap_send_abort(host, 10000);
508}
509
510static void
511mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
512{
513 unsigned long flags;
514 int done;
515
516 if (!host->dma_in_use) {
517 mmc_omap_xfer_done(host, data);
518 return;
519 }
520 done = 0;
521 spin_lock_irqsave(&host->dma_lock, flags);
522 if (host->dma_done)
523 done = 1;
524 else
525 host->brs_received = 1;
526 spin_unlock_irqrestore(&host->dma_lock, flags);
527 if (done)
528 mmc_omap_xfer_done(host, data);
529}
530
531static void
532mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
533{
534 unsigned long flags;
535 int done;
536
537 done = 0;
538 spin_lock_irqsave(&host->dma_lock, flags);
539 if (host->brs_received)
540 done = 1;
541 else
542 host->dma_done = 1;
543 spin_unlock_irqrestore(&host->dma_lock, flags);
544 if (done)
545 mmc_omap_xfer_done(host, data);
546}
547
548static void
549mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
550{
551 host->cmd = NULL;
552
553 del_timer(&host->cmd_abort_timer);
554
555 if (cmd->flags & MMC_RSP_PRESENT) {
556 if (cmd->flags & MMC_RSP_136) {
557 /* response type 2 */
558 cmd->resp[3] =
559 OMAP_MMC_READ(host, RSP0) |
560 (OMAP_MMC_READ(host, RSP1) << 16);
561 cmd->resp[2] =
562 OMAP_MMC_READ(host, RSP2) |
563 (OMAP_MMC_READ(host, RSP3) << 16);
564 cmd->resp[1] =
565 OMAP_MMC_READ(host, RSP4) |
566 (OMAP_MMC_READ(host, RSP5) << 16);
567 cmd->resp[0] =
568 OMAP_MMC_READ(host, RSP6) |
569 (OMAP_MMC_READ(host, RSP7) << 16);
570 } else {
571 /* response types 1, 1b, 3, 4, 5, 6 */
572 cmd->resp[0] =
573 OMAP_MMC_READ(host, RSP6) |
574 (OMAP_MMC_READ(host, RSP7) << 16);
575 }
576 }
577
578 if (host->data == NULL || cmd->error) {
579 struct mmc_host *mmc;
580
581 if (host->data != NULL)
582 mmc_omap_abort_xfer(host, host->data);
583 host->mrq = NULL;
584 mmc = host->mmc;
585 mmc_omap_release_slot(host->current_slot, 1);
586 mmc_request_done(mmc, cmd->mrq);
587 }
588}
589
590/*
591 * Abort stuck command. Can occur when card is removed while it is being
592 * read.
593 */
594static void mmc_omap_abort_command(struct work_struct *work)
595{
596 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
597 cmd_abort_work);
598 BUG_ON(!host->cmd);
599
600 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
601 host->cmd->opcode);
602
603 if (host->cmd->error == 0)
604 host->cmd->error = -ETIMEDOUT;
605
606 if (host->data == NULL) {
607 struct mmc_command *cmd;
608 struct mmc_host *mmc;
609
610 cmd = host->cmd;
611 host->cmd = NULL;
612 mmc_omap_send_abort(host, 10000);
613
614 host->mrq = NULL;
615 mmc = host->mmc;
616 mmc_omap_release_slot(host->current_slot, 1);
617 mmc_request_done(mmc, cmd->mrq);
618 } else
619 mmc_omap_cmd_done(host, host->cmd);
620
621 host->abort = 0;
622 enable_irq(host->irq);
623}
624
625static void
626mmc_omap_cmd_timer(struct timer_list *t)
627{
628 struct mmc_omap_host *host = from_timer(host, t, cmd_abort_timer);
629 unsigned long flags;
630
631 spin_lock_irqsave(&host->slot_lock, flags);
632 if (host->cmd != NULL && !host->abort) {
633 OMAP_MMC_WRITE(host, IE, 0);
634 disable_irq(host->irq);
635 host->abort = 1;
636 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
637 }
638 spin_unlock_irqrestore(&host->slot_lock, flags);
639}
640
641/* PIO only */
642static void
643mmc_omap_sg_to_buf(struct mmc_omap_host *host)
644{
645 struct scatterlist *sg;
646
647 sg = host->data->sg + host->sg_idx;
648 host->buffer_bytes_left = sg->length;
649 host->buffer = sg_virt(sg);
650 if (host->buffer_bytes_left > host->total_bytes_left)
651 host->buffer_bytes_left = host->total_bytes_left;
652}
653
654static void
655mmc_omap_clk_timer(struct timer_list *t)
656{
657 struct mmc_omap_host *host = from_timer(host, t, clk_timer);
658
659 mmc_omap_fclk_enable(host, 0);
660}
661
662/* PIO only */
663static void
664mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
665{
666 int n, nwords;
667
668 if (host->buffer_bytes_left == 0) {
669 host->sg_idx++;
670 BUG_ON(host->sg_idx == host->sg_len);
671 mmc_omap_sg_to_buf(host);
672 }
673 n = 64;
674 if (n > host->buffer_bytes_left)
675 n = host->buffer_bytes_left;
676
677 /* Round up to handle odd number of bytes to transfer */
678 nwords = DIV_ROUND_UP(n, 2);
679
680 host->buffer_bytes_left -= n;
681 host->total_bytes_left -= n;
682 host->data->bytes_xfered += n;
683
684 if (write) {
685 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
686 host->buffer, nwords);
687 } else {
688 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
689 host->buffer, nwords);
690 }
691
692 host->buffer += nwords;
693}
694
695#ifdef CONFIG_MMC_DEBUG
696static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
697{
698 static const char *mmc_omap_status_bits[] = {
699 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
700 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
701 };
702 int i;
703 char res[64], *buf = res;
704
705 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
706
707 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
708 if (status & (1 << i))
709 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
710 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
711}
712#else
713static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
714{
715}
716#endif
717
718
719static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
720{
721 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
722 u16 status;
723 int end_command;
724 int end_transfer;
725 int transfer_error, cmd_error;
726
727 if (host->cmd == NULL && host->data == NULL) {
728 status = OMAP_MMC_READ(host, STAT);
729 dev_info(mmc_dev(host->slots[0]->mmc),
730 "Spurious IRQ 0x%04x\n", status);
731 if (status != 0) {
732 OMAP_MMC_WRITE(host, STAT, status);
733 OMAP_MMC_WRITE(host, IE, 0);
734 }
735 return IRQ_HANDLED;
736 }
737
738 end_command = 0;
739 end_transfer = 0;
740 transfer_error = 0;
741 cmd_error = 0;
742
743 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
744 int cmd;
745
746 OMAP_MMC_WRITE(host, STAT, status);
747 if (host->cmd != NULL)
748 cmd = host->cmd->opcode;
749 else
750 cmd = -1;
751 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
752 status, cmd);
753 mmc_omap_report_irq(host, status);
754
755 if (host->total_bytes_left) {
756 if ((status & OMAP_MMC_STAT_A_FULL) ||
757 (status & OMAP_MMC_STAT_END_OF_DATA))
758 mmc_omap_xfer_data(host, 0);
759 if (status & OMAP_MMC_STAT_A_EMPTY)
760 mmc_omap_xfer_data(host, 1);
761 }
762
763 if (status & OMAP_MMC_STAT_END_OF_DATA)
764 end_transfer = 1;
765
766 if (status & OMAP_MMC_STAT_DATA_TOUT) {
767 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
768 cmd);
769 if (host->data) {
770 host->data->error = -ETIMEDOUT;
771 transfer_error = 1;
772 }
773 }
774
775 if (status & OMAP_MMC_STAT_DATA_CRC) {
776 if (host->data) {
777 host->data->error = -EILSEQ;
778 dev_dbg(mmc_dev(host->mmc),
779 "data CRC error, bytes left %d\n",
780 host->total_bytes_left);
781 transfer_error = 1;
782 } else {
783 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
784 }
785 }
786
787 if (status & OMAP_MMC_STAT_CMD_TOUT) {
788 /* Timeouts are routine with some commands */
789 if (host->cmd) {
790 struct mmc_omap_slot *slot =
791 host->current_slot;
792 if (slot == NULL ||
793 !mmc_omap_cover_is_open(slot))
794 dev_err(mmc_dev(host->mmc),
795 "command timeout (CMD%d)\n",
796 cmd);
797 host->cmd->error = -ETIMEDOUT;
798 end_command = 1;
799 cmd_error = 1;
800 }
801 }
802
803 if (status & OMAP_MMC_STAT_CMD_CRC) {
804 if (host->cmd) {
805 dev_err(mmc_dev(host->mmc),
806 "command CRC error (CMD%d, arg 0x%08x)\n",
807 cmd, host->cmd->arg);
808 host->cmd->error = -EILSEQ;
809 end_command = 1;
810 cmd_error = 1;
811 } else
812 dev_err(mmc_dev(host->mmc),
813 "command CRC error without cmd?\n");
814 }
815
816 if (status & OMAP_MMC_STAT_CARD_ERR) {
817 dev_dbg(mmc_dev(host->mmc),
818 "ignoring card status error (CMD%d)\n",
819 cmd);
820 end_command = 1;
821 }
822
823 /*
824 * NOTE: On 1610 the END_OF_CMD may come too early when
825 * starting a write
826 */
827 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
828 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
829 end_command = 1;
830 }
831 }
832
833 if (cmd_error && host->data) {
834 del_timer(&host->cmd_abort_timer);
835 host->abort = 1;
836 OMAP_MMC_WRITE(host, IE, 0);
837 disable_irq_nosync(host->irq);
838 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
839 return IRQ_HANDLED;
840 }
841
842 if (end_command && host->cmd)
843 mmc_omap_cmd_done(host, host->cmd);
844 if (host->data != NULL) {
845 if (transfer_error)
846 mmc_omap_xfer_done(host, host->data);
847 else if (end_transfer)
848 mmc_omap_end_of_data(host, host->data);
849 }
850
851 return IRQ_HANDLED;
852}
853
854void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
855{
856 int cover_open;
857 struct mmc_omap_host *host = dev_get_drvdata(dev);
858 struct mmc_omap_slot *slot = host->slots[num];
859
860 BUG_ON(num >= host->nr_slots);
861
862 /* Other subsystems can call in here before we're initialised. */
863 if (host->nr_slots == 0 || !host->slots[num])
864 return;
865
866 cover_open = mmc_omap_cover_is_open(slot);
867 if (cover_open != slot->cover_open) {
868 slot->cover_open = cover_open;
869 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
870 }
871
872 tasklet_hi_schedule(&slot->cover_tasklet);
873}
874
875static void mmc_omap_cover_timer(struct timer_list *t)
876{
877 struct mmc_omap_slot *slot = from_timer(slot, t, cover_timer);
878 tasklet_schedule(&slot->cover_tasklet);
879}
880
881static void mmc_omap_cover_handler(struct tasklet_struct *t)
882{
883 struct mmc_omap_slot *slot = from_tasklet(slot, t, cover_tasklet);
884 int cover_open = mmc_omap_cover_is_open(slot);
885
886 mmc_detect_change(slot->mmc, 0);
887 if (!cover_open)
888 return;
889
890 /*
891 * If no card is inserted, we postpone polling until
892 * the cover has been closed.
893 */
894 if (slot->mmc->card == NULL)
895 return;
896
897 mod_timer(&slot->cover_timer,
898 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
899}
900
901static void mmc_omap_dma_callback(void *priv)
902{
903 struct mmc_omap_host *host = priv;
904 struct mmc_data *data = host->data;
905
906 /* If we got to the end of DMA, assume everything went well */
907 data->bytes_xfered += data->blocks * data->blksz;
908
909 mmc_omap_dma_done(host, data);
910}
911
912static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
913{
914 u16 reg;
915
916 reg = OMAP_MMC_READ(host, SDIO);
917 reg &= ~(1 << 5);
918 OMAP_MMC_WRITE(host, SDIO, reg);
919 /* Set maximum timeout */
920 OMAP_MMC_WRITE(host, CTO, 0xfd);
921}
922
923static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
924{
925 unsigned int timeout, cycle_ns;
926 u16 reg;
927
928 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
929 timeout = req->data->timeout_ns / cycle_ns;
930 timeout += req->data->timeout_clks;
931
932 /* Check if we need to use timeout multiplier register */
933 reg = OMAP_MMC_READ(host, SDIO);
934 if (timeout > 0xffff) {
935 reg |= (1 << 5);
936 timeout /= 1024;
937 } else
938 reg &= ~(1 << 5);
939 OMAP_MMC_WRITE(host, SDIO, reg);
940 OMAP_MMC_WRITE(host, DTO, timeout);
941}
942
943static void
944mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
945{
946 struct mmc_data *data = req->data;
947 int i, use_dma = 1, block_size;
948 struct scatterlist *sg;
949 unsigned sg_len;
950
951 host->data = data;
952 if (data == NULL) {
953 OMAP_MMC_WRITE(host, BLEN, 0);
954 OMAP_MMC_WRITE(host, NBLK, 0);
955 OMAP_MMC_WRITE(host, BUF, 0);
956 host->dma_in_use = 0;
957 set_cmd_timeout(host, req);
958 return;
959 }
960
961 block_size = data->blksz;
962
963 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
964 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
965 set_data_timeout(host, req);
966
967 /* cope with calling layer confusion; it issues "single
968 * block" writes using multi-block scatterlists.
969 */
970 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
971
972 /* Only do DMA for entire blocks */
973 for_each_sg(data->sg, sg, sg_len, i) {
974 if ((sg->length % block_size) != 0) {
975 use_dma = 0;
976 break;
977 }
978 }
979
980 host->sg_idx = 0;
981 if (use_dma) {
982 enum dma_data_direction dma_data_dir;
983 struct dma_async_tx_descriptor *tx;
984 struct dma_chan *c;
985 u32 burst, *bp;
986 u16 buf;
987
988 /*
989 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
990 * and 24xx. Use 16 or 32 word frames when the
991 * blocksize is at least that large. Blocksize is
992 * usually 512 bytes; but not for some SD reads.
993 */
994 burst = mmc_omap15xx() ? 32 : 64;
995 if (burst > data->blksz)
996 burst = data->blksz;
997
998 burst >>= 1;
999
1000 if (data->flags & MMC_DATA_WRITE) {
1001 c = host->dma_tx;
1002 bp = &host->dma_tx_burst;
1003 buf = 0x0f80 | (burst - 1) << 0;
1004 dma_data_dir = DMA_TO_DEVICE;
1005 } else {
1006 c = host->dma_rx;
1007 bp = &host->dma_rx_burst;
1008 buf = 0x800f | (burst - 1) << 8;
1009 dma_data_dir = DMA_FROM_DEVICE;
1010 }
1011
1012 if (!c)
1013 goto use_pio;
1014
1015 /* Only reconfigure if we have a different burst size */
1016 if (*bp != burst) {
1017 struct dma_slave_config cfg = {
1018 .src_addr = host->phys_base +
1019 OMAP_MMC_REG(host, DATA),
1020 .dst_addr = host->phys_base +
1021 OMAP_MMC_REG(host, DATA),
1022 .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1023 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1024 .src_maxburst = burst,
1025 .dst_maxburst = burst,
1026 };
1027
1028 if (dmaengine_slave_config(c, &cfg))
1029 goto use_pio;
1030
1031 *bp = burst;
1032 }
1033
1034 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1035 dma_data_dir);
1036 if (host->sg_len == 0)
1037 goto use_pio;
1038
1039 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1040 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1042 if (!tx)
1043 goto use_pio;
1044
1045 OMAP_MMC_WRITE(host, BUF, buf);
1046
1047 tx->callback = mmc_omap_dma_callback;
1048 tx->callback_param = host;
1049 dmaengine_submit(tx);
1050 host->brs_received = 0;
1051 host->dma_done = 0;
1052 host->dma_in_use = 1;
1053 return;
1054 }
1055 use_pio:
1056
1057 /* Revert to PIO? */
1058 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1059 host->total_bytes_left = data->blocks * block_size;
1060 host->sg_len = sg_len;
1061 mmc_omap_sg_to_buf(host);
1062 host->dma_in_use = 0;
1063}
1064
1065static void mmc_omap_start_request(struct mmc_omap_host *host,
1066 struct mmc_request *req)
1067{
1068 BUG_ON(host->mrq != NULL);
1069
1070 host->mrq = req;
1071
1072 /* only touch fifo AFTER the controller readies it */
1073 mmc_omap_prepare_data(host, req);
1074 mmc_omap_start_command(host, req->cmd);
1075 if (host->dma_in_use) {
1076 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1077 host->dma_tx : host->dma_rx;
1078
1079 dma_async_issue_pending(c);
1080 }
1081}
1082
1083static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1084{
1085 struct mmc_omap_slot *slot = mmc_priv(mmc);
1086 struct mmc_omap_host *host = slot->host;
1087 unsigned long flags;
1088
1089 spin_lock_irqsave(&host->slot_lock, flags);
1090 if (host->mmc != NULL) {
1091 BUG_ON(slot->mrq != NULL);
1092 slot->mrq = req;
1093 spin_unlock_irqrestore(&host->slot_lock, flags);
1094 return;
1095 } else
1096 host->mmc = mmc;
1097 spin_unlock_irqrestore(&host->slot_lock, flags);
1098 mmc_omap_select_slot(slot, 1);
1099 mmc_omap_start_request(host, req);
1100}
1101
1102static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1103 int vdd)
1104{
1105 struct mmc_omap_host *host;
1106
1107 host = slot->host;
1108
1109 if (slot->pdata->set_power != NULL)
1110 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1111 vdd);
1112 if (mmc_omap2()) {
1113 u16 w;
1114
1115 if (power_on) {
1116 w = OMAP_MMC_READ(host, CON);
1117 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1118 } else {
1119 w = OMAP_MMC_READ(host, CON);
1120 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1121 }
1122 }
1123}
1124
1125static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1126{
1127 struct mmc_omap_slot *slot = mmc_priv(mmc);
1128 struct mmc_omap_host *host = slot->host;
1129 int func_clk_rate = clk_get_rate(host->fclk);
1130 int dsor;
1131
1132 if (ios->clock == 0)
1133 return 0;
1134
1135 dsor = func_clk_rate / ios->clock;
1136 if (dsor < 1)
1137 dsor = 1;
1138
1139 if (func_clk_rate / dsor > ios->clock)
1140 dsor++;
1141
1142 if (dsor > 250)
1143 dsor = 250;
1144
1145 slot->fclk_freq = func_clk_rate / dsor;
1146
1147 if (ios->bus_width == MMC_BUS_WIDTH_4)
1148 dsor |= 1 << 15;
1149
1150 return dsor;
1151}
1152
1153static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1154{
1155 struct mmc_omap_slot *slot = mmc_priv(mmc);
1156 struct mmc_omap_host *host = slot->host;
1157 int i, dsor;
1158 int clk_enabled, init_stream;
1159
1160 mmc_omap_select_slot(slot, 0);
1161
1162 dsor = mmc_omap_calc_divisor(mmc, ios);
1163
1164 if (ios->vdd != slot->vdd)
1165 slot->vdd = ios->vdd;
1166
1167 clk_enabled = 0;
1168 init_stream = 0;
1169 switch (ios->power_mode) {
1170 case MMC_POWER_OFF:
1171 mmc_omap_set_power(slot, 0, ios->vdd);
1172 break;
1173 case MMC_POWER_UP:
1174 /* Cannot touch dsor yet, just power up MMC */
1175 mmc_omap_set_power(slot, 1, ios->vdd);
1176 slot->power_mode = ios->power_mode;
1177 goto exit;
1178 case MMC_POWER_ON:
1179 mmc_omap_fclk_enable(host, 1);
1180 clk_enabled = 1;
1181 dsor |= 1 << 11;
1182 if (slot->power_mode != MMC_POWER_ON)
1183 init_stream = 1;
1184 break;
1185 }
1186 slot->power_mode = ios->power_mode;
1187
1188 if (slot->bus_mode != ios->bus_mode) {
1189 if (slot->pdata->set_bus_mode != NULL)
1190 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1191 ios->bus_mode);
1192 slot->bus_mode = ios->bus_mode;
1193 }
1194
1195 /* On insanely high arm_per frequencies something sometimes
1196 * goes somehow out of sync, and the POW bit is not being set,
1197 * which results in the while loop below getting stuck.
1198 * Writing to the CON register twice seems to do the trick. */
1199 for (i = 0; i < 2; i++)
1200 OMAP_MMC_WRITE(host, CON, dsor);
1201 slot->saved_con = dsor;
1202 if (init_stream) {
1203 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1204 int usecs = 250;
1205
1206 /* Send clock cycles, poll completion */
1207 OMAP_MMC_WRITE(host, IE, 0);
1208 OMAP_MMC_WRITE(host, STAT, 0xffff);
1209 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1210 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1211 udelay(1);
1212 usecs--;
1213 }
1214 OMAP_MMC_WRITE(host, STAT, 1);
1215 }
1216
1217exit:
1218 mmc_omap_release_slot(slot, clk_enabled);
1219}
1220
1221static const struct mmc_host_ops mmc_omap_ops = {
1222 .request = mmc_omap_request,
1223 .set_ios = mmc_omap_set_ios,
1224};
1225
1226static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1227{
1228 struct mmc_omap_slot *slot = NULL;
1229 struct mmc_host *mmc;
1230 int r;
1231
1232 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1233 if (mmc == NULL)
1234 return -ENOMEM;
1235
1236 slot = mmc_priv(mmc);
1237 slot->host = host;
1238 slot->mmc = mmc;
1239 slot->id = id;
1240 slot->power_mode = MMC_POWER_UNDEFINED;
1241 slot->pdata = &host->pdata->slots[id];
1242
1243 host->slots[id] = slot;
1244
1245 mmc->caps = 0;
1246 if (host->pdata->slots[id].wires >= 4)
1247 mmc->caps |= MMC_CAP_4_BIT_DATA;
1248
1249 mmc->ops = &mmc_omap_ops;
1250 mmc->f_min = 400000;
1251
1252 if (mmc_omap2())
1253 mmc->f_max = 48000000;
1254 else
1255 mmc->f_max = 24000000;
1256 if (host->pdata->max_freq)
1257 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1258 mmc->ocr_avail = slot->pdata->ocr_mask;
1259
1260 /* Use scatterlist DMA to reduce per-transfer costs.
1261 * NOTE max_seg_size assumption that small blocks aren't
1262 * normally used (except e.g. for reading SD registers).
1263 */
1264 mmc->max_segs = 32;
1265 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1266 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1267 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1268 mmc->max_seg_size = mmc->max_req_size;
1269
1270 if (slot->pdata->get_cover_state != NULL) {
1271 timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0);
1272 tasklet_setup(&slot->cover_tasklet, mmc_omap_cover_handler);
1273 }
1274
1275 r = mmc_add_host(mmc);
1276 if (r < 0)
1277 goto err_remove_host;
1278
1279 if (slot->pdata->name != NULL) {
1280 r = device_create_file(&mmc->class_dev,
1281 &dev_attr_slot_name);
1282 if (r < 0)
1283 goto err_remove_host;
1284 }
1285
1286 if (slot->pdata->get_cover_state != NULL) {
1287 r = device_create_file(&mmc->class_dev,
1288 &dev_attr_cover_switch);
1289 if (r < 0)
1290 goto err_remove_slot_name;
1291 tasklet_schedule(&slot->cover_tasklet);
1292 }
1293
1294 return 0;
1295
1296err_remove_slot_name:
1297 if (slot->pdata->name != NULL)
1298 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1299err_remove_host:
1300 mmc_remove_host(mmc);
1301 mmc_free_host(mmc);
1302 return r;
1303}
1304
1305static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1306{
1307 struct mmc_host *mmc = slot->mmc;
1308
1309 if (slot->pdata->name != NULL)
1310 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1311 if (slot->pdata->get_cover_state != NULL)
1312 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1313
1314 tasklet_kill(&slot->cover_tasklet);
1315 del_timer_sync(&slot->cover_timer);
1316 flush_workqueue(slot->host->mmc_omap_wq);
1317
1318 mmc_remove_host(mmc);
1319 mmc_free_host(mmc);
1320}
1321
1322static int mmc_omap_probe(struct platform_device *pdev)
1323{
1324 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1325 struct mmc_omap_host *host = NULL;
1326 struct resource *res;
1327 int i, ret = 0;
1328 int irq;
1329
1330 if (pdata == NULL) {
1331 dev_err(&pdev->dev, "platform data missing\n");
1332 return -ENXIO;
1333 }
1334 if (pdata->nr_slots == 0) {
1335 dev_err(&pdev->dev, "no slots\n");
1336 return -EPROBE_DEFER;
1337 }
1338
1339 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1340 GFP_KERNEL);
1341 if (host == NULL)
1342 return -ENOMEM;
1343
1344 irq = platform_get_irq(pdev, 0);
1345 if (irq < 0)
1346 return -ENXIO;
1347
1348 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1349 host->virt_base = devm_ioremap_resource(&pdev->dev, res);
1350 if (IS_ERR(host->virt_base))
1351 return PTR_ERR(host->virt_base);
1352
1353 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1354 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1355
1356 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1357 timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0);
1358
1359 spin_lock_init(&host->clk_lock);
1360 timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0);
1361
1362 spin_lock_init(&host->dma_lock);
1363 spin_lock_init(&host->slot_lock);
1364 init_waitqueue_head(&host->slot_wq);
1365
1366 host->pdata = pdata;
1367 host->features = host->pdata->slots[0].features;
1368 host->dev = &pdev->dev;
1369 platform_set_drvdata(pdev, host);
1370
1371 host->id = pdev->id;
1372 host->irq = irq;
1373 host->phys_base = res->start;
1374 host->iclk = clk_get(&pdev->dev, "ick");
1375 if (IS_ERR(host->iclk))
1376 return PTR_ERR(host->iclk);
1377 clk_prepare_enable(host->iclk);
1378
1379 host->fclk = clk_get(&pdev->dev, "fck");
1380 if (IS_ERR(host->fclk)) {
1381 ret = PTR_ERR(host->fclk);
1382 goto err_free_iclk;
1383 }
1384
1385 ret = clk_prepare(host->fclk);
1386 if (ret)
1387 goto err_put_fclk;
1388
1389 host->dma_tx_burst = -1;
1390 host->dma_rx_burst = -1;
1391
1392 host->dma_tx = dma_request_chan(&pdev->dev, "tx");
1393 if (IS_ERR(host->dma_tx)) {
1394 ret = PTR_ERR(host->dma_tx);
1395 if (ret == -EPROBE_DEFER)
1396 goto err_free_fclk;
1397
1398 host->dma_tx = NULL;
1399 dev_warn(host->dev, "TX DMA channel request failed\n");
1400 }
1401
1402 host->dma_rx = dma_request_chan(&pdev->dev, "rx");
1403 if (IS_ERR(host->dma_rx)) {
1404 ret = PTR_ERR(host->dma_rx);
1405 if (ret == -EPROBE_DEFER) {
1406 if (host->dma_tx)
1407 dma_release_channel(host->dma_tx);
1408 goto err_free_fclk;
1409 }
1410
1411 host->dma_rx = NULL;
1412 dev_warn(host->dev, "RX DMA channel request failed\n");
1413 }
1414
1415 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1416 if (ret)
1417 goto err_free_dma;
1418
1419 if (pdata->init != NULL) {
1420 ret = pdata->init(&pdev->dev);
1421 if (ret < 0)
1422 goto err_free_irq;
1423 }
1424
1425 host->nr_slots = pdata->nr_slots;
1426 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1427
1428 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1429 if (!host->mmc_omap_wq) {
1430 ret = -ENOMEM;
1431 goto err_plat_cleanup;
1432 }
1433
1434 for (i = 0; i < pdata->nr_slots; i++) {
1435 ret = mmc_omap_new_slot(host, i);
1436 if (ret < 0) {
1437 while (--i >= 0)
1438 mmc_omap_remove_slot(host->slots[i]);
1439
1440 goto err_destroy_wq;
1441 }
1442 }
1443
1444 return 0;
1445
1446err_destroy_wq:
1447 destroy_workqueue(host->mmc_omap_wq);
1448err_plat_cleanup:
1449 if (pdata->cleanup)
1450 pdata->cleanup(&pdev->dev);
1451err_free_irq:
1452 free_irq(host->irq, host);
1453err_free_dma:
1454 if (host->dma_tx)
1455 dma_release_channel(host->dma_tx);
1456 if (host->dma_rx)
1457 dma_release_channel(host->dma_rx);
1458err_free_fclk:
1459 clk_unprepare(host->fclk);
1460err_put_fclk:
1461 clk_put(host->fclk);
1462err_free_iclk:
1463 clk_disable_unprepare(host->iclk);
1464 clk_put(host->iclk);
1465 return ret;
1466}
1467
1468static int mmc_omap_remove(struct platform_device *pdev)
1469{
1470 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1471 int i;
1472
1473 BUG_ON(host == NULL);
1474
1475 for (i = 0; i < host->nr_slots; i++)
1476 mmc_omap_remove_slot(host->slots[i]);
1477
1478 if (host->pdata->cleanup)
1479 host->pdata->cleanup(&pdev->dev);
1480
1481 mmc_omap_fclk_enable(host, 0);
1482 free_irq(host->irq, host);
1483 clk_unprepare(host->fclk);
1484 clk_put(host->fclk);
1485 clk_disable_unprepare(host->iclk);
1486 clk_put(host->iclk);
1487
1488 if (host->dma_tx)
1489 dma_release_channel(host->dma_tx);
1490 if (host->dma_rx)
1491 dma_release_channel(host->dma_rx);
1492
1493 destroy_workqueue(host->mmc_omap_wq);
1494
1495 return 0;
1496}
1497
1498#if IS_BUILTIN(CONFIG_OF)
1499static const struct of_device_id mmc_omap_match[] = {
1500 { .compatible = "ti,omap2420-mmc", },
1501 { },
1502};
1503MODULE_DEVICE_TABLE(of, mmc_omap_match);
1504#endif
1505
1506static struct platform_driver mmc_omap_driver = {
1507 .probe = mmc_omap_probe,
1508 .remove = mmc_omap_remove,
1509 .driver = {
1510 .name = DRIVER_NAME,
1511 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1512 .of_match_table = of_match_ptr(mmc_omap_match),
1513 },
1514};
1515
1516module_platform_driver(mmc_omap_driver);
1517MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1518MODULE_LICENSE("GPL");
1519MODULE_ALIAS("platform:" DRIVER_NAME);
1520MODULE_AUTHOR("Juha Yrjölä");
1/*
2 * linux/drivers/mmc/host/omap.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/ioport.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
20#include <linux/dmaengine.h>
21#include <linux/dma-mapping.h>
22#include <linux/delay.h>
23#include <linux/spinlock.h>
24#include <linux/timer.h>
25#include <linux/of.h>
26#include <linux/mmc/host.h>
27#include <linux/mmc/card.h>
28#include <linux/mmc/mmc.h>
29#include <linux/clk.h>
30#include <linux/scatterlist.h>
31#include <linux/slab.h>
32#include <linux/platform_data/mmc-omap.h>
33
34
35#define OMAP_MMC_REG_CMD 0x00
36#define OMAP_MMC_REG_ARGL 0x01
37#define OMAP_MMC_REG_ARGH 0x02
38#define OMAP_MMC_REG_CON 0x03
39#define OMAP_MMC_REG_STAT 0x04
40#define OMAP_MMC_REG_IE 0x05
41#define OMAP_MMC_REG_CTO 0x06
42#define OMAP_MMC_REG_DTO 0x07
43#define OMAP_MMC_REG_DATA 0x08
44#define OMAP_MMC_REG_BLEN 0x09
45#define OMAP_MMC_REG_NBLK 0x0a
46#define OMAP_MMC_REG_BUF 0x0b
47#define OMAP_MMC_REG_SDIO 0x0d
48#define OMAP_MMC_REG_REV 0x0f
49#define OMAP_MMC_REG_RSP0 0x10
50#define OMAP_MMC_REG_RSP1 0x11
51#define OMAP_MMC_REG_RSP2 0x12
52#define OMAP_MMC_REG_RSP3 0x13
53#define OMAP_MMC_REG_RSP4 0x14
54#define OMAP_MMC_REG_RSP5 0x15
55#define OMAP_MMC_REG_RSP6 0x16
56#define OMAP_MMC_REG_RSP7 0x17
57#define OMAP_MMC_REG_IOSR 0x18
58#define OMAP_MMC_REG_SYSC 0x19
59#define OMAP_MMC_REG_SYSS 0x1a
60
61#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
62#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
63#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
64#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
65#define OMAP_MMC_STAT_A_FULL (1 << 10)
66#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
67#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
68#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
69#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
70#define OMAP_MMC_STAT_END_BUSY (1 << 4)
71#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
72#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
73#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
74
75#define mmc_omap7xx() (host->features & MMC_OMAP7XX)
76#define mmc_omap15xx() (host->features & MMC_OMAP15XX)
77#define mmc_omap16xx() (host->features & MMC_OMAP16XX)
78#define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
79#define mmc_omap1() (host->features & MMC_OMAP1_MASK)
80#define mmc_omap2() (!mmc_omap1())
81
82#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
83#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
84#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
85
86/*
87 * Command types
88 */
89#define OMAP_MMC_CMDTYPE_BC 0
90#define OMAP_MMC_CMDTYPE_BCR 1
91#define OMAP_MMC_CMDTYPE_AC 2
92#define OMAP_MMC_CMDTYPE_ADTC 3
93
94#define DRIVER_NAME "mmci-omap"
95
96/* Specifies how often in millisecs to poll for card status changes
97 * when the cover switch is open */
98#define OMAP_MMC_COVER_POLL_DELAY 500
99
100struct mmc_omap_host;
101
102struct mmc_omap_slot {
103 int id;
104 unsigned int vdd;
105 u16 saved_con;
106 u16 bus_mode;
107 unsigned int fclk_freq;
108
109 struct tasklet_struct cover_tasklet;
110 struct timer_list cover_timer;
111 unsigned cover_open;
112
113 struct mmc_request *mrq;
114 struct mmc_omap_host *host;
115 struct mmc_host *mmc;
116 struct omap_mmc_slot_data *pdata;
117};
118
119struct mmc_omap_host {
120 int initialized;
121 struct mmc_request * mrq;
122 struct mmc_command * cmd;
123 struct mmc_data * data;
124 struct mmc_host * mmc;
125 struct device * dev;
126 unsigned char id; /* 16xx chips have 2 MMC blocks */
127 struct clk * iclk;
128 struct clk * fclk;
129 struct dma_chan *dma_rx;
130 u32 dma_rx_burst;
131 struct dma_chan *dma_tx;
132 u32 dma_tx_burst;
133 void __iomem *virt_base;
134 unsigned int phys_base;
135 int irq;
136 unsigned char bus_mode;
137 unsigned int reg_shift;
138
139 struct work_struct cmd_abort_work;
140 unsigned abort:1;
141 struct timer_list cmd_abort_timer;
142
143 struct work_struct slot_release_work;
144 struct mmc_omap_slot *next_slot;
145 struct work_struct send_stop_work;
146 struct mmc_data *stop_data;
147
148 unsigned int sg_len;
149 int sg_idx;
150 u16 * buffer;
151 u32 buffer_bytes_left;
152 u32 total_bytes_left;
153
154 unsigned features;
155 unsigned brs_received:1, dma_done:1;
156 unsigned dma_in_use:1;
157 spinlock_t dma_lock;
158
159 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
160 struct mmc_omap_slot *current_slot;
161 spinlock_t slot_lock;
162 wait_queue_head_t slot_wq;
163 int nr_slots;
164
165 struct timer_list clk_timer;
166 spinlock_t clk_lock; /* for changing enabled state */
167 unsigned int fclk_enabled:1;
168 struct workqueue_struct *mmc_omap_wq;
169
170 struct omap_mmc_platform_data *pdata;
171};
172
173
174static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
175{
176 unsigned long tick_ns;
177
178 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
179 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
180 ndelay(8 * tick_ns);
181 }
182}
183
184static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
185{
186 unsigned long flags;
187
188 spin_lock_irqsave(&host->clk_lock, flags);
189 if (host->fclk_enabled != enable) {
190 host->fclk_enabled = enable;
191 if (enable)
192 clk_enable(host->fclk);
193 else
194 clk_disable(host->fclk);
195 }
196 spin_unlock_irqrestore(&host->clk_lock, flags);
197}
198
199static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
200{
201 struct mmc_omap_host *host = slot->host;
202 unsigned long flags;
203
204 if (claimed)
205 goto no_claim;
206 spin_lock_irqsave(&host->slot_lock, flags);
207 while (host->mmc != NULL) {
208 spin_unlock_irqrestore(&host->slot_lock, flags);
209 wait_event(host->slot_wq, host->mmc == NULL);
210 spin_lock_irqsave(&host->slot_lock, flags);
211 }
212 host->mmc = slot->mmc;
213 spin_unlock_irqrestore(&host->slot_lock, flags);
214no_claim:
215 del_timer(&host->clk_timer);
216 if (host->current_slot != slot || !claimed)
217 mmc_omap_fclk_offdelay(host->current_slot);
218
219 if (host->current_slot != slot) {
220 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
221 if (host->pdata->switch_slot != NULL)
222 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
223 host->current_slot = slot;
224 }
225
226 if (claimed) {
227 mmc_omap_fclk_enable(host, 1);
228
229 /* Doing the dummy read here seems to work around some bug
230 * at least in OMAP24xx silicon where the command would not
231 * start after writing the CMD register. Sigh. */
232 OMAP_MMC_READ(host, CON);
233
234 OMAP_MMC_WRITE(host, CON, slot->saved_con);
235 } else
236 mmc_omap_fclk_enable(host, 0);
237}
238
239static void mmc_omap_start_request(struct mmc_omap_host *host,
240 struct mmc_request *req);
241
242static void mmc_omap_slot_release_work(struct work_struct *work)
243{
244 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
245 slot_release_work);
246 struct mmc_omap_slot *next_slot = host->next_slot;
247 struct mmc_request *rq;
248
249 host->next_slot = NULL;
250 mmc_omap_select_slot(next_slot, 1);
251
252 rq = next_slot->mrq;
253 next_slot->mrq = NULL;
254 mmc_omap_start_request(host, rq);
255}
256
257static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
258{
259 struct mmc_omap_host *host = slot->host;
260 unsigned long flags;
261 int i;
262
263 BUG_ON(slot == NULL || host->mmc == NULL);
264
265 if (clk_enabled)
266 /* Keeps clock running for at least 8 cycles on valid freq */
267 mod_timer(&host->clk_timer, jiffies + HZ/10);
268 else {
269 del_timer(&host->clk_timer);
270 mmc_omap_fclk_offdelay(slot);
271 mmc_omap_fclk_enable(host, 0);
272 }
273
274 spin_lock_irqsave(&host->slot_lock, flags);
275 /* Check for any pending requests */
276 for (i = 0; i < host->nr_slots; i++) {
277 struct mmc_omap_slot *new_slot;
278
279 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
280 continue;
281
282 BUG_ON(host->next_slot != NULL);
283 new_slot = host->slots[i];
284 /* The current slot should not have a request in queue */
285 BUG_ON(new_slot == host->current_slot);
286
287 host->next_slot = new_slot;
288 host->mmc = new_slot->mmc;
289 spin_unlock_irqrestore(&host->slot_lock, flags);
290 queue_work(host->mmc_omap_wq, &host->slot_release_work);
291 return;
292 }
293
294 host->mmc = NULL;
295 wake_up(&host->slot_wq);
296 spin_unlock_irqrestore(&host->slot_lock, flags);
297}
298
299static inline
300int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
301{
302 if (slot->pdata->get_cover_state)
303 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
304 slot->id);
305 return 0;
306}
307
308static ssize_t
309mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
310 char *buf)
311{
312 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
313 struct mmc_omap_slot *slot = mmc_priv(mmc);
314
315 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
316 "closed");
317}
318
319static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
320
321static ssize_t
322mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
323 char *buf)
324{
325 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
326 struct mmc_omap_slot *slot = mmc_priv(mmc);
327
328 return sprintf(buf, "%s\n", slot->pdata->name);
329}
330
331static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
332
333static void
334mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
335{
336 u32 cmdreg;
337 u32 resptype;
338 u32 cmdtype;
339 u16 irq_mask;
340
341 host->cmd = cmd;
342
343 resptype = 0;
344 cmdtype = 0;
345
346 /* Our hardware needs to know exact type */
347 switch (mmc_resp_type(cmd)) {
348 case MMC_RSP_NONE:
349 break;
350 case MMC_RSP_R1:
351 case MMC_RSP_R1B:
352 /* resp 1, 1b, 6, 7 */
353 resptype = 1;
354 break;
355 case MMC_RSP_R2:
356 resptype = 2;
357 break;
358 case MMC_RSP_R3:
359 resptype = 3;
360 break;
361 default:
362 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
363 break;
364 }
365
366 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
367 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
368 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
369 cmdtype = OMAP_MMC_CMDTYPE_BC;
370 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
371 cmdtype = OMAP_MMC_CMDTYPE_BCR;
372 } else {
373 cmdtype = OMAP_MMC_CMDTYPE_AC;
374 }
375
376 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
377
378 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
379 cmdreg |= 1 << 6;
380
381 if (cmd->flags & MMC_RSP_BUSY)
382 cmdreg |= 1 << 11;
383
384 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
385 cmdreg |= 1 << 15;
386
387 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
388
389 OMAP_MMC_WRITE(host, CTO, 200);
390 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
391 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
392 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
393 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
394 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
395 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
396 OMAP_MMC_STAT_END_OF_DATA;
397 if (cmd->opcode == MMC_ERASE)
398 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
399 OMAP_MMC_WRITE(host, IE, irq_mask);
400 OMAP_MMC_WRITE(host, CMD, cmdreg);
401}
402
403static void
404mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
405 int abort)
406{
407 enum dma_data_direction dma_data_dir;
408 struct device *dev = mmc_dev(host->mmc);
409 struct dma_chan *c;
410
411 if (data->flags & MMC_DATA_WRITE) {
412 dma_data_dir = DMA_TO_DEVICE;
413 c = host->dma_tx;
414 } else {
415 dma_data_dir = DMA_FROM_DEVICE;
416 c = host->dma_rx;
417 }
418 if (c) {
419 if (data->error) {
420 dmaengine_terminate_all(c);
421 /* Claim nothing transferred on error... */
422 data->bytes_xfered = 0;
423 }
424 dev = c->device->dev;
425 }
426 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
427}
428
429static void mmc_omap_send_stop_work(struct work_struct *work)
430{
431 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
432 send_stop_work);
433 struct mmc_omap_slot *slot = host->current_slot;
434 struct mmc_data *data = host->stop_data;
435 unsigned long tick_ns;
436
437 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
438 ndelay(8*tick_ns);
439
440 mmc_omap_start_command(host, data->stop);
441}
442
443static void
444mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
445{
446 if (host->dma_in_use)
447 mmc_omap_release_dma(host, data, data->error);
448
449 host->data = NULL;
450 host->sg_len = 0;
451
452 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
453 * dozens of requests until the card finishes writing data.
454 * It'd be cheaper to just wait till an EOFB interrupt arrives...
455 */
456
457 if (!data->stop) {
458 struct mmc_host *mmc;
459
460 host->mrq = NULL;
461 mmc = host->mmc;
462 mmc_omap_release_slot(host->current_slot, 1);
463 mmc_request_done(mmc, data->mrq);
464 return;
465 }
466
467 host->stop_data = data;
468 queue_work(host->mmc_omap_wq, &host->send_stop_work);
469}
470
471static void
472mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
473{
474 struct mmc_omap_slot *slot = host->current_slot;
475 unsigned int restarts, passes, timeout;
476 u16 stat = 0;
477
478 /* Sending abort takes 80 clocks. Have some extra and round up */
479 timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
480 restarts = 0;
481 while (restarts < maxloops) {
482 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
483 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
484
485 passes = 0;
486 while (passes < timeout) {
487 stat = OMAP_MMC_READ(host, STAT);
488 if (stat & OMAP_MMC_STAT_END_OF_CMD)
489 goto out;
490 udelay(1);
491 passes++;
492 }
493
494 restarts++;
495 }
496out:
497 OMAP_MMC_WRITE(host, STAT, stat);
498}
499
500static void
501mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
502{
503 if (host->dma_in_use)
504 mmc_omap_release_dma(host, data, 1);
505
506 host->data = NULL;
507 host->sg_len = 0;
508
509 mmc_omap_send_abort(host, 10000);
510}
511
512static void
513mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
514{
515 unsigned long flags;
516 int done;
517
518 if (!host->dma_in_use) {
519 mmc_omap_xfer_done(host, data);
520 return;
521 }
522 done = 0;
523 spin_lock_irqsave(&host->dma_lock, flags);
524 if (host->dma_done)
525 done = 1;
526 else
527 host->brs_received = 1;
528 spin_unlock_irqrestore(&host->dma_lock, flags);
529 if (done)
530 mmc_omap_xfer_done(host, data);
531}
532
533static void
534mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
535{
536 unsigned long flags;
537 int done;
538
539 done = 0;
540 spin_lock_irqsave(&host->dma_lock, flags);
541 if (host->brs_received)
542 done = 1;
543 else
544 host->dma_done = 1;
545 spin_unlock_irqrestore(&host->dma_lock, flags);
546 if (done)
547 mmc_omap_xfer_done(host, data);
548}
549
550static void
551mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
552{
553 host->cmd = NULL;
554
555 del_timer(&host->cmd_abort_timer);
556
557 if (cmd->flags & MMC_RSP_PRESENT) {
558 if (cmd->flags & MMC_RSP_136) {
559 /* response type 2 */
560 cmd->resp[3] =
561 OMAP_MMC_READ(host, RSP0) |
562 (OMAP_MMC_READ(host, RSP1) << 16);
563 cmd->resp[2] =
564 OMAP_MMC_READ(host, RSP2) |
565 (OMAP_MMC_READ(host, RSP3) << 16);
566 cmd->resp[1] =
567 OMAP_MMC_READ(host, RSP4) |
568 (OMAP_MMC_READ(host, RSP5) << 16);
569 cmd->resp[0] =
570 OMAP_MMC_READ(host, RSP6) |
571 (OMAP_MMC_READ(host, RSP7) << 16);
572 } else {
573 /* response types 1, 1b, 3, 4, 5, 6 */
574 cmd->resp[0] =
575 OMAP_MMC_READ(host, RSP6) |
576 (OMAP_MMC_READ(host, RSP7) << 16);
577 }
578 }
579
580 if (host->data == NULL || cmd->error) {
581 struct mmc_host *mmc;
582
583 if (host->data != NULL)
584 mmc_omap_abort_xfer(host, host->data);
585 host->mrq = NULL;
586 mmc = host->mmc;
587 mmc_omap_release_slot(host->current_slot, 1);
588 mmc_request_done(mmc, cmd->mrq);
589 }
590}
591
592/*
593 * Abort stuck command. Can occur when card is removed while it is being
594 * read.
595 */
596static void mmc_omap_abort_command(struct work_struct *work)
597{
598 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
599 cmd_abort_work);
600 BUG_ON(!host->cmd);
601
602 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
603 host->cmd->opcode);
604
605 if (host->cmd->error == 0)
606 host->cmd->error = -ETIMEDOUT;
607
608 if (host->data == NULL) {
609 struct mmc_command *cmd;
610 struct mmc_host *mmc;
611
612 cmd = host->cmd;
613 host->cmd = NULL;
614 mmc_omap_send_abort(host, 10000);
615
616 host->mrq = NULL;
617 mmc = host->mmc;
618 mmc_omap_release_slot(host->current_slot, 1);
619 mmc_request_done(mmc, cmd->mrq);
620 } else
621 mmc_omap_cmd_done(host, host->cmd);
622
623 host->abort = 0;
624 enable_irq(host->irq);
625}
626
627static void
628mmc_omap_cmd_timer(struct timer_list *t)
629{
630 struct mmc_omap_host *host = from_timer(host, t, cmd_abort_timer);
631 unsigned long flags;
632
633 spin_lock_irqsave(&host->slot_lock, flags);
634 if (host->cmd != NULL && !host->abort) {
635 OMAP_MMC_WRITE(host, IE, 0);
636 disable_irq(host->irq);
637 host->abort = 1;
638 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
639 }
640 spin_unlock_irqrestore(&host->slot_lock, flags);
641}
642
643/* PIO only */
644static void
645mmc_omap_sg_to_buf(struct mmc_omap_host *host)
646{
647 struct scatterlist *sg;
648
649 sg = host->data->sg + host->sg_idx;
650 host->buffer_bytes_left = sg->length;
651 host->buffer = sg_virt(sg);
652 if (host->buffer_bytes_left > host->total_bytes_left)
653 host->buffer_bytes_left = host->total_bytes_left;
654}
655
656static void
657mmc_omap_clk_timer(struct timer_list *t)
658{
659 struct mmc_omap_host *host = from_timer(host, t, clk_timer);
660
661 mmc_omap_fclk_enable(host, 0);
662}
663
664/* PIO only */
665static void
666mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
667{
668 int n, nwords;
669
670 if (host->buffer_bytes_left == 0) {
671 host->sg_idx++;
672 BUG_ON(host->sg_idx == host->sg_len);
673 mmc_omap_sg_to_buf(host);
674 }
675 n = 64;
676 if (n > host->buffer_bytes_left)
677 n = host->buffer_bytes_left;
678
679 /* Round up to handle odd number of bytes to transfer */
680 nwords = DIV_ROUND_UP(n, 2);
681
682 host->buffer_bytes_left -= n;
683 host->total_bytes_left -= n;
684 host->data->bytes_xfered += n;
685
686 if (write) {
687 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
688 host->buffer, nwords);
689 } else {
690 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
691 host->buffer, nwords);
692 }
693
694 host->buffer += nwords;
695}
696
697#ifdef CONFIG_MMC_DEBUG
698static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
699{
700 static const char *mmc_omap_status_bits[] = {
701 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
702 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
703 };
704 int i;
705 char res[64], *buf = res;
706
707 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
708
709 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
710 if (status & (1 << i))
711 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
712 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
713}
714#else
715static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
716{
717}
718#endif
719
720
721static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
722{
723 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
724 u16 status;
725 int end_command;
726 int end_transfer;
727 int transfer_error, cmd_error;
728
729 if (host->cmd == NULL && host->data == NULL) {
730 status = OMAP_MMC_READ(host, STAT);
731 dev_info(mmc_dev(host->slots[0]->mmc),
732 "Spurious IRQ 0x%04x\n", status);
733 if (status != 0) {
734 OMAP_MMC_WRITE(host, STAT, status);
735 OMAP_MMC_WRITE(host, IE, 0);
736 }
737 return IRQ_HANDLED;
738 }
739
740 end_command = 0;
741 end_transfer = 0;
742 transfer_error = 0;
743 cmd_error = 0;
744
745 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
746 int cmd;
747
748 OMAP_MMC_WRITE(host, STAT, status);
749 if (host->cmd != NULL)
750 cmd = host->cmd->opcode;
751 else
752 cmd = -1;
753 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
754 status, cmd);
755 mmc_omap_report_irq(host, status);
756
757 if (host->total_bytes_left) {
758 if ((status & OMAP_MMC_STAT_A_FULL) ||
759 (status & OMAP_MMC_STAT_END_OF_DATA))
760 mmc_omap_xfer_data(host, 0);
761 if (status & OMAP_MMC_STAT_A_EMPTY)
762 mmc_omap_xfer_data(host, 1);
763 }
764
765 if (status & OMAP_MMC_STAT_END_OF_DATA)
766 end_transfer = 1;
767
768 if (status & OMAP_MMC_STAT_DATA_TOUT) {
769 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
770 cmd);
771 if (host->data) {
772 host->data->error = -ETIMEDOUT;
773 transfer_error = 1;
774 }
775 }
776
777 if (status & OMAP_MMC_STAT_DATA_CRC) {
778 if (host->data) {
779 host->data->error = -EILSEQ;
780 dev_dbg(mmc_dev(host->mmc),
781 "data CRC error, bytes left %d\n",
782 host->total_bytes_left);
783 transfer_error = 1;
784 } else {
785 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
786 }
787 }
788
789 if (status & OMAP_MMC_STAT_CMD_TOUT) {
790 /* Timeouts are routine with some commands */
791 if (host->cmd) {
792 struct mmc_omap_slot *slot =
793 host->current_slot;
794 if (slot == NULL ||
795 !mmc_omap_cover_is_open(slot))
796 dev_err(mmc_dev(host->mmc),
797 "command timeout (CMD%d)\n",
798 cmd);
799 host->cmd->error = -ETIMEDOUT;
800 end_command = 1;
801 cmd_error = 1;
802 }
803 }
804
805 if (status & OMAP_MMC_STAT_CMD_CRC) {
806 if (host->cmd) {
807 dev_err(mmc_dev(host->mmc),
808 "command CRC error (CMD%d, arg 0x%08x)\n",
809 cmd, host->cmd->arg);
810 host->cmd->error = -EILSEQ;
811 end_command = 1;
812 cmd_error = 1;
813 } else
814 dev_err(mmc_dev(host->mmc),
815 "command CRC error without cmd?\n");
816 }
817
818 if (status & OMAP_MMC_STAT_CARD_ERR) {
819 dev_dbg(mmc_dev(host->mmc),
820 "ignoring card status error (CMD%d)\n",
821 cmd);
822 end_command = 1;
823 }
824
825 /*
826 * NOTE: On 1610 the END_OF_CMD may come too early when
827 * starting a write
828 */
829 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
830 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
831 end_command = 1;
832 }
833 }
834
835 if (cmd_error && host->data) {
836 del_timer(&host->cmd_abort_timer);
837 host->abort = 1;
838 OMAP_MMC_WRITE(host, IE, 0);
839 disable_irq_nosync(host->irq);
840 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
841 return IRQ_HANDLED;
842 }
843
844 if (end_command && host->cmd)
845 mmc_omap_cmd_done(host, host->cmd);
846 if (host->data != NULL) {
847 if (transfer_error)
848 mmc_omap_xfer_done(host, host->data);
849 else if (end_transfer)
850 mmc_omap_end_of_data(host, host->data);
851 }
852
853 return IRQ_HANDLED;
854}
855
856void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
857{
858 int cover_open;
859 struct mmc_omap_host *host = dev_get_drvdata(dev);
860 struct mmc_omap_slot *slot = host->slots[num];
861
862 BUG_ON(num >= host->nr_slots);
863
864 /* Other subsystems can call in here before we're initialised. */
865 if (host->nr_slots == 0 || !host->slots[num])
866 return;
867
868 cover_open = mmc_omap_cover_is_open(slot);
869 if (cover_open != slot->cover_open) {
870 slot->cover_open = cover_open;
871 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
872 }
873
874 tasklet_hi_schedule(&slot->cover_tasklet);
875}
876
877static void mmc_omap_cover_timer(struct timer_list *t)
878{
879 struct mmc_omap_slot *slot = from_timer(slot, t, cover_timer);
880 tasklet_schedule(&slot->cover_tasklet);
881}
882
883static void mmc_omap_cover_handler(unsigned long param)
884{
885 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
886 int cover_open = mmc_omap_cover_is_open(slot);
887
888 mmc_detect_change(slot->mmc, 0);
889 if (!cover_open)
890 return;
891
892 /*
893 * If no card is inserted, we postpone polling until
894 * the cover has been closed.
895 */
896 if (slot->mmc->card == NULL)
897 return;
898
899 mod_timer(&slot->cover_timer,
900 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
901}
902
903static void mmc_omap_dma_callback(void *priv)
904{
905 struct mmc_omap_host *host = priv;
906 struct mmc_data *data = host->data;
907
908 /* If we got to the end of DMA, assume everything went well */
909 data->bytes_xfered += data->blocks * data->blksz;
910
911 mmc_omap_dma_done(host, data);
912}
913
914static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
915{
916 u16 reg;
917
918 reg = OMAP_MMC_READ(host, SDIO);
919 reg &= ~(1 << 5);
920 OMAP_MMC_WRITE(host, SDIO, reg);
921 /* Set maximum timeout */
922 OMAP_MMC_WRITE(host, CTO, 0xff);
923}
924
925static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
926{
927 unsigned int timeout, cycle_ns;
928 u16 reg;
929
930 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
931 timeout = req->data->timeout_ns / cycle_ns;
932 timeout += req->data->timeout_clks;
933
934 /* Check if we need to use timeout multiplier register */
935 reg = OMAP_MMC_READ(host, SDIO);
936 if (timeout > 0xffff) {
937 reg |= (1 << 5);
938 timeout /= 1024;
939 } else
940 reg &= ~(1 << 5);
941 OMAP_MMC_WRITE(host, SDIO, reg);
942 OMAP_MMC_WRITE(host, DTO, timeout);
943}
944
945static void
946mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
947{
948 struct mmc_data *data = req->data;
949 int i, use_dma = 1, block_size;
950 struct scatterlist *sg;
951 unsigned sg_len;
952
953 host->data = data;
954 if (data == NULL) {
955 OMAP_MMC_WRITE(host, BLEN, 0);
956 OMAP_MMC_WRITE(host, NBLK, 0);
957 OMAP_MMC_WRITE(host, BUF, 0);
958 host->dma_in_use = 0;
959 set_cmd_timeout(host, req);
960 return;
961 }
962
963 block_size = data->blksz;
964
965 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
966 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
967 set_data_timeout(host, req);
968
969 /* cope with calling layer confusion; it issues "single
970 * block" writes using multi-block scatterlists.
971 */
972 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
973
974 /* Only do DMA for entire blocks */
975 for_each_sg(data->sg, sg, sg_len, i) {
976 if ((sg->length % block_size) != 0) {
977 use_dma = 0;
978 break;
979 }
980 }
981
982 host->sg_idx = 0;
983 if (use_dma) {
984 enum dma_data_direction dma_data_dir;
985 struct dma_async_tx_descriptor *tx;
986 struct dma_chan *c;
987 u32 burst, *bp;
988 u16 buf;
989
990 /*
991 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
992 * and 24xx. Use 16 or 32 word frames when the
993 * blocksize is at least that large. Blocksize is
994 * usually 512 bytes; but not for some SD reads.
995 */
996 burst = mmc_omap15xx() ? 32 : 64;
997 if (burst > data->blksz)
998 burst = data->blksz;
999
1000 burst >>= 1;
1001
1002 if (data->flags & MMC_DATA_WRITE) {
1003 c = host->dma_tx;
1004 bp = &host->dma_tx_burst;
1005 buf = 0x0f80 | (burst - 1) << 0;
1006 dma_data_dir = DMA_TO_DEVICE;
1007 } else {
1008 c = host->dma_rx;
1009 bp = &host->dma_rx_burst;
1010 buf = 0x800f | (burst - 1) << 8;
1011 dma_data_dir = DMA_FROM_DEVICE;
1012 }
1013
1014 if (!c)
1015 goto use_pio;
1016
1017 /* Only reconfigure if we have a different burst size */
1018 if (*bp != burst) {
1019 struct dma_slave_config cfg = {
1020 .src_addr = host->phys_base +
1021 OMAP_MMC_REG(host, DATA),
1022 .dst_addr = host->phys_base +
1023 OMAP_MMC_REG(host, DATA),
1024 .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1025 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1026 .src_maxburst = burst,
1027 .dst_maxburst = burst,
1028 };
1029
1030 if (dmaengine_slave_config(c, &cfg))
1031 goto use_pio;
1032
1033 *bp = burst;
1034 }
1035
1036 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1037 dma_data_dir);
1038 if (host->sg_len == 0)
1039 goto use_pio;
1040
1041 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1042 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1043 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1044 if (!tx)
1045 goto use_pio;
1046
1047 OMAP_MMC_WRITE(host, BUF, buf);
1048
1049 tx->callback = mmc_omap_dma_callback;
1050 tx->callback_param = host;
1051 dmaengine_submit(tx);
1052 host->brs_received = 0;
1053 host->dma_done = 0;
1054 host->dma_in_use = 1;
1055 return;
1056 }
1057 use_pio:
1058
1059 /* Revert to PIO? */
1060 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1061 host->total_bytes_left = data->blocks * block_size;
1062 host->sg_len = sg_len;
1063 mmc_omap_sg_to_buf(host);
1064 host->dma_in_use = 0;
1065}
1066
1067static void mmc_omap_start_request(struct mmc_omap_host *host,
1068 struct mmc_request *req)
1069{
1070 BUG_ON(host->mrq != NULL);
1071
1072 host->mrq = req;
1073
1074 /* only touch fifo AFTER the controller readies it */
1075 mmc_omap_prepare_data(host, req);
1076 mmc_omap_start_command(host, req->cmd);
1077 if (host->dma_in_use) {
1078 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1079 host->dma_tx : host->dma_rx;
1080
1081 dma_async_issue_pending(c);
1082 }
1083}
1084
1085static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1086{
1087 struct mmc_omap_slot *slot = mmc_priv(mmc);
1088 struct mmc_omap_host *host = slot->host;
1089 unsigned long flags;
1090
1091 spin_lock_irqsave(&host->slot_lock, flags);
1092 if (host->mmc != NULL) {
1093 BUG_ON(slot->mrq != NULL);
1094 slot->mrq = req;
1095 spin_unlock_irqrestore(&host->slot_lock, flags);
1096 return;
1097 } else
1098 host->mmc = mmc;
1099 spin_unlock_irqrestore(&host->slot_lock, flags);
1100 mmc_omap_select_slot(slot, 1);
1101 mmc_omap_start_request(host, req);
1102}
1103
1104static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1105 int vdd)
1106{
1107 struct mmc_omap_host *host;
1108
1109 host = slot->host;
1110
1111 if (slot->pdata->set_power != NULL)
1112 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1113 vdd);
1114 if (mmc_omap2()) {
1115 u16 w;
1116
1117 if (power_on) {
1118 w = OMAP_MMC_READ(host, CON);
1119 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1120 } else {
1121 w = OMAP_MMC_READ(host, CON);
1122 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1123 }
1124 }
1125}
1126
1127static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1128{
1129 struct mmc_omap_slot *slot = mmc_priv(mmc);
1130 struct mmc_omap_host *host = slot->host;
1131 int func_clk_rate = clk_get_rate(host->fclk);
1132 int dsor;
1133
1134 if (ios->clock == 0)
1135 return 0;
1136
1137 dsor = func_clk_rate / ios->clock;
1138 if (dsor < 1)
1139 dsor = 1;
1140
1141 if (func_clk_rate / dsor > ios->clock)
1142 dsor++;
1143
1144 if (dsor > 250)
1145 dsor = 250;
1146
1147 slot->fclk_freq = func_clk_rate / dsor;
1148
1149 if (ios->bus_width == MMC_BUS_WIDTH_4)
1150 dsor |= 1 << 15;
1151
1152 return dsor;
1153}
1154
1155static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1156{
1157 struct mmc_omap_slot *slot = mmc_priv(mmc);
1158 struct mmc_omap_host *host = slot->host;
1159 int i, dsor;
1160 int clk_enabled;
1161
1162 mmc_omap_select_slot(slot, 0);
1163
1164 dsor = mmc_omap_calc_divisor(mmc, ios);
1165
1166 if (ios->vdd != slot->vdd)
1167 slot->vdd = ios->vdd;
1168
1169 clk_enabled = 0;
1170 switch (ios->power_mode) {
1171 case MMC_POWER_OFF:
1172 mmc_omap_set_power(slot, 0, ios->vdd);
1173 break;
1174 case MMC_POWER_UP:
1175 /* Cannot touch dsor yet, just power up MMC */
1176 mmc_omap_set_power(slot, 1, ios->vdd);
1177 goto exit;
1178 case MMC_POWER_ON:
1179 mmc_omap_fclk_enable(host, 1);
1180 clk_enabled = 1;
1181 dsor |= 1 << 11;
1182 break;
1183 }
1184
1185 if (slot->bus_mode != ios->bus_mode) {
1186 if (slot->pdata->set_bus_mode != NULL)
1187 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1188 ios->bus_mode);
1189 slot->bus_mode = ios->bus_mode;
1190 }
1191
1192 /* On insanely high arm_per frequencies something sometimes
1193 * goes somehow out of sync, and the POW bit is not being set,
1194 * which results in the while loop below getting stuck.
1195 * Writing to the CON register twice seems to do the trick. */
1196 for (i = 0; i < 2; i++)
1197 OMAP_MMC_WRITE(host, CON, dsor);
1198 slot->saved_con = dsor;
1199 if (ios->power_mode == MMC_POWER_ON) {
1200 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1201 int usecs = 250;
1202
1203 /* Send clock cycles, poll completion */
1204 OMAP_MMC_WRITE(host, IE, 0);
1205 OMAP_MMC_WRITE(host, STAT, 0xffff);
1206 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1207 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1208 udelay(1);
1209 usecs--;
1210 }
1211 OMAP_MMC_WRITE(host, STAT, 1);
1212 }
1213
1214exit:
1215 mmc_omap_release_slot(slot, clk_enabled);
1216}
1217
1218static const struct mmc_host_ops mmc_omap_ops = {
1219 .request = mmc_omap_request,
1220 .set_ios = mmc_omap_set_ios,
1221};
1222
1223static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1224{
1225 struct mmc_omap_slot *slot = NULL;
1226 struct mmc_host *mmc;
1227 int r;
1228
1229 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1230 if (mmc == NULL)
1231 return -ENOMEM;
1232
1233 slot = mmc_priv(mmc);
1234 slot->host = host;
1235 slot->mmc = mmc;
1236 slot->id = id;
1237 slot->pdata = &host->pdata->slots[id];
1238
1239 host->slots[id] = slot;
1240
1241 mmc->caps = 0;
1242 if (host->pdata->slots[id].wires >= 4)
1243 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_ERASE;
1244
1245 mmc->ops = &mmc_omap_ops;
1246 mmc->f_min = 400000;
1247
1248 if (mmc_omap2())
1249 mmc->f_max = 48000000;
1250 else
1251 mmc->f_max = 24000000;
1252 if (host->pdata->max_freq)
1253 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1254 mmc->ocr_avail = slot->pdata->ocr_mask;
1255
1256 /* Use scatterlist DMA to reduce per-transfer costs.
1257 * NOTE max_seg_size assumption that small blocks aren't
1258 * normally used (except e.g. for reading SD registers).
1259 */
1260 mmc->max_segs = 32;
1261 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1262 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1263 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1264 mmc->max_seg_size = mmc->max_req_size;
1265
1266 if (slot->pdata->get_cover_state != NULL) {
1267 timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0);
1268 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1269 (unsigned long)slot);
1270 }
1271
1272 r = mmc_add_host(mmc);
1273 if (r < 0)
1274 goto err_remove_host;
1275
1276 if (slot->pdata->name != NULL) {
1277 r = device_create_file(&mmc->class_dev,
1278 &dev_attr_slot_name);
1279 if (r < 0)
1280 goto err_remove_host;
1281 }
1282
1283 if (slot->pdata->get_cover_state != NULL) {
1284 r = device_create_file(&mmc->class_dev,
1285 &dev_attr_cover_switch);
1286 if (r < 0)
1287 goto err_remove_slot_name;
1288 tasklet_schedule(&slot->cover_tasklet);
1289 }
1290
1291 return 0;
1292
1293err_remove_slot_name:
1294 if (slot->pdata->name != NULL)
1295 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1296err_remove_host:
1297 mmc_remove_host(mmc);
1298 mmc_free_host(mmc);
1299 return r;
1300}
1301
1302static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1303{
1304 struct mmc_host *mmc = slot->mmc;
1305
1306 if (slot->pdata->name != NULL)
1307 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1308 if (slot->pdata->get_cover_state != NULL)
1309 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1310
1311 tasklet_kill(&slot->cover_tasklet);
1312 del_timer_sync(&slot->cover_timer);
1313 flush_workqueue(slot->host->mmc_omap_wq);
1314
1315 mmc_remove_host(mmc);
1316 mmc_free_host(mmc);
1317}
1318
1319static int mmc_omap_probe(struct platform_device *pdev)
1320{
1321 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1322 struct mmc_omap_host *host = NULL;
1323 struct resource *res;
1324 int i, ret = 0;
1325 int irq;
1326
1327 if (pdata == NULL) {
1328 dev_err(&pdev->dev, "platform data missing\n");
1329 return -ENXIO;
1330 }
1331 if (pdata->nr_slots == 0) {
1332 dev_err(&pdev->dev, "no slots\n");
1333 return -EPROBE_DEFER;
1334 }
1335
1336 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1337 GFP_KERNEL);
1338 if (host == NULL)
1339 return -ENOMEM;
1340
1341 irq = platform_get_irq(pdev, 0);
1342 if (irq < 0)
1343 return -ENXIO;
1344
1345 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1346 host->virt_base = devm_ioremap_resource(&pdev->dev, res);
1347 if (IS_ERR(host->virt_base))
1348 return PTR_ERR(host->virt_base);
1349
1350 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1351 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1352
1353 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1354 timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0);
1355
1356 spin_lock_init(&host->clk_lock);
1357 timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0);
1358
1359 spin_lock_init(&host->dma_lock);
1360 spin_lock_init(&host->slot_lock);
1361 init_waitqueue_head(&host->slot_wq);
1362
1363 host->pdata = pdata;
1364 host->features = host->pdata->slots[0].features;
1365 host->dev = &pdev->dev;
1366 platform_set_drvdata(pdev, host);
1367
1368 host->id = pdev->id;
1369 host->irq = irq;
1370 host->phys_base = res->start;
1371 host->iclk = clk_get(&pdev->dev, "ick");
1372 if (IS_ERR(host->iclk))
1373 return PTR_ERR(host->iclk);
1374 clk_enable(host->iclk);
1375
1376 host->fclk = clk_get(&pdev->dev, "fck");
1377 if (IS_ERR(host->fclk)) {
1378 ret = PTR_ERR(host->fclk);
1379 goto err_free_iclk;
1380 }
1381
1382 host->dma_tx_burst = -1;
1383 host->dma_rx_burst = -1;
1384
1385 host->dma_tx = dma_request_chan(&pdev->dev, "tx");
1386 if (IS_ERR(host->dma_tx)) {
1387 ret = PTR_ERR(host->dma_tx);
1388 if (ret == -EPROBE_DEFER) {
1389 clk_put(host->fclk);
1390 goto err_free_iclk;
1391 }
1392
1393 host->dma_tx = NULL;
1394 dev_warn(host->dev, "TX DMA channel request failed\n");
1395 }
1396
1397 host->dma_rx = dma_request_chan(&pdev->dev, "rx");
1398 if (IS_ERR(host->dma_rx)) {
1399 ret = PTR_ERR(host->dma_rx);
1400 if (ret == -EPROBE_DEFER) {
1401 if (host->dma_tx)
1402 dma_release_channel(host->dma_tx);
1403 clk_put(host->fclk);
1404 goto err_free_iclk;
1405 }
1406
1407 host->dma_rx = NULL;
1408 dev_warn(host->dev, "RX DMA channel request failed\n");
1409 }
1410
1411 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1412 if (ret)
1413 goto err_free_dma;
1414
1415 if (pdata->init != NULL) {
1416 ret = pdata->init(&pdev->dev);
1417 if (ret < 0)
1418 goto err_free_irq;
1419 }
1420
1421 host->nr_slots = pdata->nr_slots;
1422 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1423
1424 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1425 if (!host->mmc_omap_wq) {
1426 ret = -ENOMEM;
1427 goto err_plat_cleanup;
1428 }
1429
1430 for (i = 0; i < pdata->nr_slots; i++) {
1431 ret = mmc_omap_new_slot(host, i);
1432 if (ret < 0) {
1433 while (--i >= 0)
1434 mmc_omap_remove_slot(host->slots[i]);
1435
1436 goto err_destroy_wq;
1437 }
1438 }
1439
1440 return 0;
1441
1442err_destroy_wq:
1443 destroy_workqueue(host->mmc_omap_wq);
1444err_plat_cleanup:
1445 if (pdata->cleanup)
1446 pdata->cleanup(&pdev->dev);
1447err_free_irq:
1448 free_irq(host->irq, host);
1449err_free_dma:
1450 if (host->dma_tx)
1451 dma_release_channel(host->dma_tx);
1452 if (host->dma_rx)
1453 dma_release_channel(host->dma_rx);
1454 clk_put(host->fclk);
1455err_free_iclk:
1456 clk_disable(host->iclk);
1457 clk_put(host->iclk);
1458 return ret;
1459}
1460
1461static int mmc_omap_remove(struct platform_device *pdev)
1462{
1463 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1464 int i;
1465
1466 BUG_ON(host == NULL);
1467
1468 for (i = 0; i < host->nr_slots; i++)
1469 mmc_omap_remove_slot(host->slots[i]);
1470
1471 if (host->pdata->cleanup)
1472 host->pdata->cleanup(&pdev->dev);
1473
1474 mmc_omap_fclk_enable(host, 0);
1475 free_irq(host->irq, host);
1476 clk_put(host->fclk);
1477 clk_disable(host->iclk);
1478 clk_put(host->iclk);
1479
1480 if (host->dma_tx)
1481 dma_release_channel(host->dma_tx);
1482 if (host->dma_rx)
1483 dma_release_channel(host->dma_rx);
1484
1485 destroy_workqueue(host->mmc_omap_wq);
1486
1487 return 0;
1488}
1489
1490#if IS_BUILTIN(CONFIG_OF)
1491static const struct of_device_id mmc_omap_match[] = {
1492 { .compatible = "ti,omap2420-mmc", },
1493 { },
1494};
1495MODULE_DEVICE_TABLE(of, mmc_omap_match);
1496#endif
1497
1498static struct platform_driver mmc_omap_driver = {
1499 .probe = mmc_omap_probe,
1500 .remove = mmc_omap_remove,
1501 .driver = {
1502 .name = DRIVER_NAME,
1503 .of_match_table = of_match_ptr(mmc_omap_match),
1504 },
1505};
1506
1507module_platform_driver(mmc_omap_driver);
1508MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1509MODULE_LICENSE("GPL");
1510MODULE_ALIAS("platform:" DRIVER_NAME);
1511MODULE_AUTHOR("Juha Yrjölä");